2014-08-27 18:47:31 +02:00
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/*
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* Copyright (C) 2013, Freie Universitaet Berlin (FUB). All rights reserved.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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2010-09-22 15:10:42 +02:00
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2017-08-24 21:03:16 +02:00
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/**
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2023-06-13 15:56:24 +02:00
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* @ingroup cpu_msp430
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2017-08-24 21:03:16 +02:00
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* @{
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*
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* @file
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2019-10-23 21:13:53 +02:00
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* @brief Common CPU definitions for MSP430
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2017-08-24 21:03:16 +02:00
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*
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*/
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2017-05-23 18:19:52 +02:00
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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2010-09-22 15:10:42 +02:00
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2014-10-13 10:53:20 +02:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2020-06-25 21:32:17 +02:00
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/**
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* @brief This arch uses the inlined IRQ API.
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*/
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#define IRQ_API_INLINED (1)
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2010-09-22 15:10:42 +02:00
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/**
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2017-03-07 11:43:08 +01:00
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* @name Configure the internal flash memory
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* @{
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*/
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2019-08-05 14:04:30 +02:00
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#define FLASHPAGE_SIZE (512U)
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2017-03-07 11:43:08 +01:00
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#if defined (CPU_MODEL_MSP430F1611)
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#define CPU_FLASH_BASE (0x4000)
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2019-08-05 14:04:30 +02:00
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#define FLASHPAGE_NUMOF (96U) /* 48K */
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2017-03-07 11:43:08 +01:00
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#elif defined (CPU_MODEL_MSP430F1612)
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2019-10-05 21:47:23 +02:00
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#define CPU_FLASH_BASE (0x2600) /* first sector is only 256 byte, skip it*/
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#define FLASHPAGE_NUMOF (109U) /* 54.5K */
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2017-03-07 11:43:08 +01:00
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#elif defined (CPU_MODEL_MSP430F2617)
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2019-10-05 21:47:23 +02:00
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#define CPU_FLASH_BASE (0x3200) /* first sector is only 256 byte, skip it*/
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#define FLASHPAGE_NUMOF (103U) /* we can currently only access 51.5K */
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2023-06-03 21:46:55 +02:00
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#elif defined (CPU_MODEL_MSP430F2618)
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#define CPU_FLASH_BASE (0x3200) /* first sector is only 256 byte, skip it*/
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#define FLASHPAGE_NUMOF (103U) /* we can currently only access 51.5K */
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2017-03-07 11:43:08 +01:00
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#elif defined (CPU_MODEL_CC430F6137)
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#define CPU_FLASH_BASE (0x8000)
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2019-08-05 14:04:30 +02:00
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#define FLASHPAGE_NUMOF (64U) /* 32K */
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2017-03-07 11:43:08 +01:00
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#endif
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2019-08-04 11:39:27 +02:00
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/* The minimum block size which can be written is 1B. However, the erase
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* block is always FLASHPAGE_SIZE.
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*/
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2020-11-09 16:44:29 +01:00
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#define FLASHPAGE_WRITE_BLOCK_SIZE (1U)
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2019-08-04 11:39:27 +02:00
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/* Writing should be always 2 byte aligned */
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2020-11-09 16:44:29 +01:00
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#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (2U)
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2017-03-07 11:43:08 +01:00
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/** @} */
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/**
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* @name Kernel configuration
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2010-09-22 15:10:42 +02:00
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* @{
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*/
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2016-10-17 11:05:22 +02:00
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#ifndef THREAD_EXTRA_STACKSIZE_PRINTF
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# define THREAD_EXTRA_STACKSIZE_PRINTF (256)
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#endif
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#ifndef THREAD_EXTRA_STACKSIZE_PRINTF
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# define THREAD_EXTRA_STACKSIZE_PRINTF_FLOAT (THREAD_EXTRA_STACKSIZE_PRINTF)
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#endif
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2013-07-23 13:42:58 +02:00
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2015-04-28 20:02:05 +02:00
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#ifndef THREAD_STACKSIZE_DEFAULT
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2020-07-30 11:20:59 +02:00
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# define THREAD_STACKSIZE_DEFAULT (384)
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2010-09-22 15:10:42 +02:00
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#endif
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2016-10-17 11:05:22 +02:00
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#ifndef THREAD_STACKSIZE_IDLE
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# define THREAD_STACKSIZE_IDLE (96)
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#endif
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#ifndef ISR_STACKSIZE
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# define ISR_STACKSIZE (256)
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#endif
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2010-12-03 18:42:03 +01:00
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2020-05-11 15:44:40 +02:00
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#ifndef CONFIG_GNRC_PKTBUF_SIZE
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2016-10-17 11:05:22 +02:00
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/* TODO: Make this value overall MTU dependent */
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2020-05-11 15:44:40 +02:00
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# define CONFIG_GNRC_PKTBUF_SIZE (2560)
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2014-09-01 18:58:11 +02:00
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#endif
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2018-09-26 11:06:05 +02:00
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#ifndef GNRC_IPV6_STACK_SIZE
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# define GNRC_IPV6_STACK_SIZE (512)
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#endif
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2010-09-22 15:10:42 +02:00
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/** @} */
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2014-10-13 10:53:20 +02:00
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#ifdef __cplusplus
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}
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#endif
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2017-05-23 18:19:52 +02:00
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#endif /* CPU_CONF_H */
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2017-08-24 21:03:16 +02:00
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/** @} */
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