mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
cpu/msp430_common: add support for MSP432F2618
This commit is contained in:
Marian Buschsieweke
parent
6df03ecb93
commit
97857d2740
@ -42,6 +42,9 @@ extern "C" {
|
||||
#elif defined (CPU_MODEL_MSP430F2617)
|
||||
#define CPU_FLASH_BASE (0x3200) /* first sector is only 256 byte, skip it*/
|
||||
#define FLASHPAGE_NUMOF (103U) /* we can currently only access 51.5K */
|
||||
#elif defined (CPU_MODEL_MSP430F2618)
|
||||
#define CPU_FLASH_BASE (0x3200) /* first sector is only 256 byte, skip it*/
|
||||
#define FLASHPAGE_NUMOF (103U) /* we can currently only access 51.5K */
|
||||
#elif defined (CPU_MODEL_CC430F6137)
|
||||
#define CPU_FLASH_BASE (0x8000)
|
||||
#define FLASHPAGE_NUMOF (64U) /* 32K */
|
||||
|
||||
3
cpu/msp430_common/ldscripts/riot-msp430f2618.ld
Normal file
3
cpu/msp430_common/ldscripts/riot-msp430f2618.ld
Normal file
@ -0,0 +1,3 @@
|
||||
INCLUDE msp430f2618.ld
|
||||
INCLUDE msp430_common.ld
|
||||
INCLUDE xfa.ld
|
||||
1520
cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2618.h
vendored
Normal file
1520
cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2618.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
397
cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2618.ld
vendored
Normal file
397
cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2618.ld
vendored
Normal file
@ -0,0 +1,397 @@
|
||||
/* ============================================================================ */
|
||||
/* Copyright (c) 2021, Texas Instruments Incorporated */
|
||||
/* All rights reserved. */
|
||||
/* */
|
||||
/* Redistribution and use in source and binary forms, with or without */
|
||||
/* modification, are permitted provided that the following conditions */
|
||||
/* are met: */
|
||||
/* */
|
||||
/* * Redistributions of source code must retain the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer. */
|
||||
/* */
|
||||
/* * Redistributions in binary form must reproduce the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer in the */
|
||||
/* documentation and/or other materials provided with the distribution. */
|
||||
/* */
|
||||
/* * Neither the name of Texas Instruments Incorporated nor the names of */
|
||||
/* its contributors may be used to endorse or promote products derived */
|
||||
/* from this software without specific prior written permission. */
|
||||
/* */
|
||||
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
|
||||
/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
|
||||
/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
|
||||
/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
|
||||
/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
|
||||
/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
|
||||
/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
|
||||
/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
|
||||
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
|
||||
/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
|
||||
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/* ============================================================================ */
|
||||
|
||||
/* This file supports MSP430F2618 devices. */
|
||||
/* Version: 1.212 */
|
||||
/* Default linker script, for normal executables */
|
||||
|
||||
OUTPUT_ARCH(msp430)
|
||||
ENTRY(_start)
|
||||
|
||||
MEMORY {
|
||||
SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */
|
||||
RAM : ORIGIN = 0x1100, LENGTH = 0x2000 /* END=0x30FF, size 8192 */
|
||||
RAM_MIRROR : ORIGIN = 0x0200, LENGTH = 0x0800
|
||||
INFOMEM : ORIGIN = 0x1000, LENGTH = 0x0100 /* END=0x10FF, size 256 as 4 64-byte segments */
|
||||
INFOA : ORIGIN = 0x10C0, LENGTH = 0x0040 /* END=0x10FF, size 64 */
|
||||
INFOB : ORIGIN = 0x1080, LENGTH = 0x0040 /* END=0x10BF, size 64 */
|
||||
INFOC : ORIGIN = 0x1040, LENGTH = 0x0040 /* END=0x107F, size 64 */
|
||||
INFOD : ORIGIN = 0x1000, LENGTH = 0x0040 /* END=0x103F, size 64 */
|
||||
ROM (rx) : ORIGIN = 0x3100, LENGTH = 0xCEBE /* END=0xFFBD, size 52926 */
|
||||
HIROM (rx) : ORIGIN = 0x00010000, LENGTH = 0x0000FFFF
|
||||
BSLSIGNATURE : ORIGIN = 0xFFBE, LENGTH = 0x0002
|
||||
VECT1 : ORIGIN = 0xFFC0, LENGTH = 0x0002
|
||||
VECT2 : ORIGIN = 0xFFC2, LENGTH = 0x0002
|
||||
VECT3 : ORIGIN = 0xFFC4, LENGTH = 0x0002
|
||||
VECT4 : ORIGIN = 0xFFC6, LENGTH = 0x0002
|
||||
VECT5 : ORIGIN = 0xFFC8, LENGTH = 0x0002
|
||||
VECT6 : ORIGIN = 0xFFCA, LENGTH = 0x0002
|
||||
VECT7 : ORIGIN = 0xFFCC, LENGTH = 0x0002
|
||||
VECT8 : ORIGIN = 0xFFCE, LENGTH = 0x0002
|
||||
VECT9 : ORIGIN = 0xFFD0, LENGTH = 0x0002
|
||||
VECT10 : ORIGIN = 0xFFD2, LENGTH = 0x0002
|
||||
VECT11 : ORIGIN = 0xFFD4, LENGTH = 0x0002
|
||||
VECT12 : ORIGIN = 0xFFD6, LENGTH = 0x0002
|
||||
VECT13 : ORIGIN = 0xFFD8, LENGTH = 0x0002
|
||||
VECT14 : ORIGIN = 0xFFDA, LENGTH = 0x0002
|
||||
VECT15 : ORIGIN = 0xFFDC, LENGTH = 0x0002
|
||||
VECT16 : ORIGIN = 0xFFDE, LENGTH = 0x0002
|
||||
VECT17 : ORIGIN = 0xFFE0, LENGTH = 0x0002
|
||||
VECT18 : ORIGIN = 0xFFE2, LENGTH = 0x0002
|
||||
VECT19 : ORIGIN = 0xFFE4, LENGTH = 0x0002
|
||||
VECT20 : ORIGIN = 0xFFE6, LENGTH = 0x0002
|
||||
VECT21 : ORIGIN = 0xFFE8, LENGTH = 0x0002
|
||||
VECT22 : ORIGIN = 0xFFEA, LENGTH = 0x0002
|
||||
VECT23 : ORIGIN = 0xFFEC, LENGTH = 0x0002
|
||||
VECT24 : ORIGIN = 0xFFEE, LENGTH = 0x0002
|
||||
VECT25 : ORIGIN = 0xFFF0, LENGTH = 0x0002
|
||||
VECT26 : ORIGIN = 0xFFF2, LENGTH = 0x0002
|
||||
VECT27 : ORIGIN = 0xFFF4, LENGTH = 0x0002
|
||||
VECT28 : ORIGIN = 0xFFF6, LENGTH = 0x0002
|
||||
VECT29 : ORIGIN = 0xFFF8, LENGTH = 0x0002
|
||||
VECT30 : ORIGIN = 0xFFFA, LENGTH = 0x0002
|
||||
VECT31 : ORIGIN = 0xFFFC, LENGTH = 0x0002
|
||||
RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.bslsignature : {} > BSLSIGNATURE
|
||||
__interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) KEEP (*(__interrupt_vector_reserved0)) } > VECT1
|
||||
__interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) KEEP (*(__interrupt_vector_reserved1)) } > VECT2
|
||||
__interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) KEEP (*(__interrupt_vector_reserved2)) } > VECT3
|
||||
__interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) KEEP (*(__interrupt_vector_reserved3)) } > VECT4
|
||||
__interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) KEEP (*(__interrupt_vector_reserved4)) } > VECT5
|
||||
__interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) KEEP (*(__interrupt_vector_reserved5)) } > VECT6
|
||||
__interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) KEEP (*(__interrupt_vector_reserved6)) } > VECT7
|
||||
__interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) KEEP (*(__interrupt_vector_reserved7)) } > VECT8
|
||||
__interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) KEEP (*(__interrupt_vector_reserved8)) } > VECT9
|
||||
__interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) KEEP (*(__interrupt_vector_reserved9)) } > VECT10
|
||||
__interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) KEEP (*(__interrupt_vector_reserved10)) } > VECT11
|
||||
__interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) KEEP (*(__interrupt_vector_reserved11)) } > VECT12
|
||||
__interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) KEEP (*(__interrupt_vector_reserved12)) } > VECT13
|
||||
__interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) KEEP (*(__interrupt_vector_reserved13)) } > VECT14
|
||||
__interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) KEEP (*(__interrupt_vector_dac12)) } > VECT15
|
||||
__interrupt_vector_16 : { KEEP (*(__interrupt_vector_16)) KEEP (*(__interrupt_vector_dma)) } > VECT16
|
||||
__interrupt_vector_17 : { KEEP (*(__interrupt_vector_17)) KEEP (*(__interrupt_vector_usciab1tx)) } > VECT17
|
||||
__interrupt_vector_18 : { KEEP (*(__interrupt_vector_18)) KEEP (*(__interrupt_vector_usciab1rx)) } > VECT18
|
||||
__interrupt_vector_19 : { KEEP (*(__interrupt_vector_19)) KEEP (*(__interrupt_vector_port1)) } > VECT19
|
||||
__interrupt_vector_20 : { KEEP (*(__interrupt_vector_20)) KEEP (*(__interrupt_vector_port2)) } > VECT20
|
||||
__interrupt_vector_21 : { KEEP (*(__interrupt_vector_21)) KEEP (*(__interrupt_vector_reserved20)) } > VECT21
|
||||
__interrupt_vector_22 : { KEEP (*(__interrupt_vector_22)) KEEP (*(__interrupt_vector_adc12)) } > VECT22
|
||||
__interrupt_vector_23 : { KEEP (*(__interrupt_vector_23)) KEEP (*(__interrupt_vector_usciab0tx)) } > VECT23
|
||||
__interrupt_vector_24 : { KEEP (*(__interrupt_vector_24)) KEEP (*(__interrupt_vector_usciab0rx)) } > VECT24
|
||||
__interrupt_vector_25 : { KEEP (*(__interrupt_vector_25)) KEEP (*(__interrupt_vector_timera1)) } > VECT25
|
||||
__interrupt_vector_26 : { KEEP (*(__interrupt_vector_26)) KEEP (*(__interrupt_vector_timera0)) } > VECT26
|
||||
__interrupt_vector_27 : { KEEP (*(__interrupt_vector_27)) KEEP (*(__interrupt_vector_wdt)) } > VECT27
|
||||
__interrupt_vector_28 : { KEEP (*(__interrupt_vector_28)) KEEP (*(__interrupt_vector_comparatora)) } > VECT28
|
||||
__interrupt_vector_29 : { KEEP (*(__interrupt_vector_29)) KEEP (*(__interrupt_vector_timerb1)) } > VECT29
|
||||
__interrupt_vector_30 : { KEEP (*(__interrupt_vector_30)) KEEP (*(__interrupt_vector_timerb0)) } > VECT30
|
||||
__interrupt_vector_31 : { KEEP (*(__interrupt_vector_31)) KEEP (*(__interrupt_vector_nmi)) } > VECT31
|
||||
__reset_vector :
|
||||
{
|
||||
KEEP (*(__interrupt_vector_32))
|
||||
KEEP (*(__interrupt_vector_reset))
|
||||
KEEP (*(.resetvec))
|
||||
} > RESETVEC
|
||||
|
||||
.lower.rodata :
|
||||
{
|
||||
. = ALIGN(2);
|
||||
*(.lower.rodata.* .lower.rodata)
|
||||
} > ROM
|
||||
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(2);
|
||||
*(.plt)
|
||||
. = ALIGN(2);
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*)
|
||||
*(.rodata1)
|
||||
KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)
|
||||
} > ROM
|
||||
|
||||
/* Note: This is a separate .rodata section for sections which are
|
||||
read only but which older linkers treat as read-write.
|
||||
This prevents older linkers from marking the entire .rodata
|
||||
section as read-write. */
|
||||
.rodata2 :
|
||||
{
|
||||
. = ALIGN(2);
|
||||
PROVIDE (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE (__preinit_array_end = .);
|
||||
. = ALIGN(2);
|
||||
PROVIDE (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
PROVIDE (__init_array_end = .);
|
||||
. = ALIGN(2);
|
||||
PROVIDE (__fini_array_start = .);
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE (__fini_array_end = .);
|
||||
. = ALIGN(2);
|
||||
*(.eh_frame_hdr)
|
||||
KEEP (*(.eh_frame))
|
||||
|
||||
/* gcc uses crtbegin.o to find the start of the constructors, so
|
||||
we make sure it is first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not actually link against
|
||||
crtbegin.o; the linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it doesn't matter which
|
||||
directory crtbegin.o is in. */
|
||||
KEEP (*crtbegin*.o(.ctors))
|
||||
|
||||
/* We don't want to include the .ctor section from the crtend.o
|
||||
file until after the sorted ctors. The .ctor section from
|
||||
the crtend file contains the end of ctors marker and it must
|
||||
be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
|
||||
KEEP (*crtbegin*.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} > ROM
|
||||
|
||||
.upper.rodata :
|
||||
{
|
||||
*(.upper.rodata.* .upper.rodata)
|
||||
} > HIROM
|
||||
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(2);
|
||||
PROVIDE (__datastart = .);
|
||||
*(.lower.data.* .lower.data)
|
||||
|
||||
. = ALIGN(2);
|
||||
*(.either.data.* .either.data)
|
||||
|
||||
. = ALIGN(2);
|
||||
KEEP (*(.jcr))
|
||||
*(.data.rel.ro.local) *(.data.rel.ro*)
|
||||
*(.dynamic)
|
||||
|
||||
. = ALIGN(2);
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
KEEP (*(.gnu.linkonce.d.*personality*))
|
||||
SORT(CONSTRUCTORS)
|
||||
*(.data1)
|
||||
*(.got.plt) *(.got)
|
||||
|
||||
/* We want the small data sections together, so single-instruction offsets
|
||||
can access them all, and initialized data all before uninitialized, so
|
||||
we can shorten the on-disk segment size. */
|
||||
. = ALIGN(2);
|
||||
*(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)
|
||||
|
||||
. = ALIGN(2);
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
PROVIDE (__dataend = .);
|
||||
} > RAM AT> ROM
|
||||
|
||||
/* Note that crt0 assumes this is a multiple of two; all the
|
||||
start/stop symbols are also assumed word-aligned. */
|
||||
PROVIDE(__romdatastart = LOADADDR(.data));
|
||||
PROVIDE (__romdatacopysize = SIZEOF(.data));
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(2);
|
||||
PROVIDE (__bssstart = .);
|
||||
*(.lower.bss.* .lower.bss)
|
||||
. = ALIGN(2);
|
||||
*(.either.bss.* .either.bss)
|
||||
*(.dynbss)
|
||||
*(.sbss .sbss.*)
|
||||
*(.bss .bss.* .gnu.linkonce.b.*)
|
||||
. = ALIGN(2);
|
||||
*(COMMON)
|
||||
PROVIDE (__bssend = .);
|
||||
} > RAM
|
||||
PROVIDE (__bsssize = SIZEOF(.bss));
|
||||
|
||||
/* This section contains data that is not initialised during load
|
||||
or application reset. */
|
||||
.noinit (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(2);
|
||||
PROVIDE (__noinit_start = .);
|
||||
*(.noinit)
|
||||
. = ALIGN(2);
|
||||
PROVIDE (__noinit_end = .);
|
||||
} > RAM
|
||||
|
||||
/* We create this section so that "end" will always be in the
|
||||
RAM region (matching .stack below), even if the .bss
|
||||
section is empty. */
|
||||
.heap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(2);
|
||||
__heap_start__ = .;
|
||||
_end = __heap_start__;
|
||||
PROVIDE (end = .);
|
||||
KEEP (*(.heap))
|
||||
_end = .;
|
||||
PROVIDE (end = .);
|
||||
/* This word is here so that the section is not empty, and thus
|
||||
not discarded by the linker. The actual value does not matter
|
||||
and is ignored. */
|
||||
LONG(0);
|
||||
__heap_end__ = .;
|
||||
__HeapLimit = __heap_end__;
|
||||
} > RAM
|
||||
/* WARNING: Do not place anything in RAM here.
|
||||
The heap section must be the last section in RAM and the stack
|
||||
section must be placed at the very end of the RAM region. */
|
||||
|
||||
.stack (ORIGIN (RAM) + LENGTH(RAM)) :
|
||||
{
|
||||
PROVIDE (__stack = .);
|
||||
*(.stack)
|
||||
}
|
||||
|
||||
/* This is just for crt0.S and interrupt handlers. */
|
||||
.lowtext :
|
||||
{
|
||||
PROVIDE (_start = .);
|
||||
. = ALIGN(2);
|
||||
KEEP (*(SORT(.crt_*)))
|
||||
KEEP (*(.lowtext))
|
||||
} > ROM
|
||||
|
||||
.lower.text :
|
||||
{
|
||||
. = ALIGN(2);
|
||||
*(.lower.text.* .lower.text)
|
||||
} > ROM
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(2);
|
||||
*(.text .stub .text.* .gnu.linkonce.t.* .text:*)
|
||||
|
||||
KEEP (*(.text.*personality*))
|
||||
/* .gnu.warning sections are handled specially by elf32.em. */
|
||||
*(.gnu.warning)
|
||||
*(.interp .hash .dynsym .dynstr .gnu.version*)
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
. = ALIGN(2);
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
KEEP (*(.tm_clone_table))
|
||||
} > ROM
|
||||
|
||||
.upper.text :
|
||||
{
|
||||
. = ALIGN(2);
|
||||
*(.upper.text.* .upper.text)
|
||||
} > HIROM
|
||||
|
||||
.infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */
|
||||
.infoB : {} > INFOB
|
||||
.infoC : {} > INFOC
|
||||
.infoD : {} > INFOD
|
||||
|
||||
/* Make sure that upper data sections are not used. */
|
||||
.upper :
|
||||
{
|
||||
*(.upper.bss.* .upper.bss)
|
||||
*(.upper.data.* .upper.data)
|
||||
ASSERT (SIZEOF(.upper) == 0, "This MCU does not support placing read/write data into high memory");
|
||||
} > HIROM
|
||||
|
||||
/* The rest are all not normally part of the runtime image. */
|
||||
|
||||
.MSP430.attributes 0 :
|
||||
{
|
||||
KEEP (*(.MSP430.attributes))
|
||||
KEEP (*(.gnu.attributes))
|
||||
KEEP (*(__TI_build_attributes))
|
||||
}
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1. */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions. */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2. */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2. */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions. */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
/* DWARF 3 */
|
||||
.debug_pubtypes 0 : { *(.debug_pubtypes) }
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
/* DWARF Extension. */
|
||||
.debug_macro 0 : { *(.debug_macro) }
|
||||
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/* Include peripherals memory map */
|
||||
/****************************************************************************/
|
||||
|
||||
INCLUDE msp430f2618_symbols.ld
|
||||
|
||||
328
cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2618_symbols.ld
vendored
Normal file
328
cpu/msp430_common/vendor/msp430-gcc-support-files/include/msp430f2618_symbols.ld
vendored
Normal file
@ -0,0 +1,328 @@
|
||||
/* ============================================================================ */
|
||||
/* Copyright (c) 2021, Texas Instruments Incorporated */
|
||||
/* All rights reserved. */
|
||||
/* */
|
||||
/* Redistribution and use in source and binary forms, with or without */
|
||||
/* modification, are permitted provided that the following conditions */
|
||||
/* are met: */
|
||||
/* */
|
||||
/* * Redistributions of source code must retain the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer. */
|
||||
/* */
|
||||
/* * Redistributions in binary form must reproduce the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer in the */
|
||||
/* documentation and/or other materials provided with the distribution. */
|
||||
/* */
|
||||
/* * Neither the name of Texas Instruments Incorporated nor the names of */
|
||||
/* its contributors may be used to endorse or promote products derived */
|
||||
/* from this software without specific prior written permission. */
|
||||
/* */
|
||||
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
|
||||
/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
|
||||
/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
|
||||
/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
|
||||
/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
|
||||
/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
|
||||
/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
|
||||
/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
|
||||
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
|
||||
/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
|
||||
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/* ============================================================================ */
|
||||
|
||||
/* This file supports MSP430F2618 devices. */
|
||||
/* Version: 1.212 */
|
||||
|
||||
/************************************************************
|
||||
* STANDARD BITS
|
||||
************************************************************/
|
||||
/************************************************************
|
||||
* STATUS REGISTER BITS
|
||||
************************************************************/
|
||||
/************************************************************
|
||||
* PERIPHERAL FILE MAP
|
||||
************************************************************/
|
||||
/************************************************************
|
||||
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
|
||||
************************************************************/
|
||||
PROVIDE(IE1 = 0x0000);
|
||||
PROVIDE(IFG1 = 0x0002);
|
||||
PROVIDE(IE2 = 0x0001);
|
||||
PROVIDE(IFG2 = 0x0003);
|
||||
PROVIDE(UC1IE = 0x0006);
|
||||
PROVIDE(UC1IFG = 0x0007);
|
||||
/************************************************************
|
||||
* ADC12
|
||||
************************************************************/
|
||||
PROVIDE(ADC12CTL0 = 0x01A0);
|
||||
PROVIDE(ADC12CTL1 = 0x01A2);
|
||||
PROVIDE(ADC12IFG = 0x01A4);
|
||||
PROVIDE(ADC12IE = 0x01A6);
|
||||
PROVIDE(ADC12IV = 0x01A8);
|
||||
PROVIDE(ADC12MEM0 = 0x0140);
|
||||
PROVIDE(ADC12MEM1 = 0x0142);
|
||||
PROVIDE(ADC12MEM2 = 0x0144);
|
||||
PROVIDE(ADC12MEM3 = 0x0146);
|
||||
PROVIDE(ADC12MEM4 = 0x0148);
|
||||
PROVIDE(ADC12MEM5 = 0x014A);
|
||||
PROVIDE(ADC12MEM6 = 0x014C);
|
||||
PROVIDE(ADC12MEM7 = 0x014E);
|
||||
PROVIDE(ADC12MEM8 = 0x0150);
|
||||
PROVIDE(ADC12MEM9 = 0x0152);
|
||||
PROVIDE(ADC12MEM10 = 0x0154);
|
||||
PROVIDE(ADC12MEM11 = 0x0156);
|
||||
PROVIDE(ADC12MEM12 = 0x0158);
|
||||
PROVIDE(ADC12MEM13 = 0x015A);
|
||||
PROVIDE(ADC12MEM14 = 0x015C);
|
||||
PROVIDE(ADC12MEM15 = 0x015E);
|
||||
PROVIDE(ADC12MCTL0 = 0x0080);
|
||||
PROVIDE(ADC12MCTL1 = 0x0081);
|
||||
PROVIDE(ADC12MCTL2 = 0x0082);
|
||||
PROVIDE(ADC12MCTL3 = 0x0083);
|
||||
PROVIDE(ADC12MCTL4 = 0x0084);
|
||||
PROVIDE(ADC12MCTL5 = 0x0085);
|
||||
PROVIDE(ADC12MCTL6 = 0x0086);
|
||||
PROVIDE(ADC12MCTL7 = 0x0087);
|
||||
PROVIDE(ADC12MCTL8 = 0x0088);
|
||||
PROVIDE(ADC12MCTL9 = 0x0089);
|
||||
PROVIDE(ADC12MCTL10 = 0x008A);
|
||||
PROVIDE(ADC12MCTL11 = 0x008B);
|
||||
PROVIDE(ADC12MCTL12 = 0x008C);
|
||||
PROVIDE(ADC12MCTL13 = 0x008D);
|
||||
PROVIDE(ADC12MCTL14 = 0x008E);
|
||||
PROVIDE(ADC12MCTL15 = 0x008F);
|
||||
/************************************************************
|
||||
* Basic Clock Module
|
||||
************************************************************/
|
||||
PROVIDE(DCOCTL = 0x0056);
|
||||
PROVIDE(BCSCTL1 = 0x0057);
|
||||
PROVIDE(BCSCTL2 = 0x0058);
|
||||
PROVIDE(BCSCTL3 = 0x0053);
|
||||
/************************************************************
|
||||
* Comparator A
|
||||
************************************************************/
|
||||
PROVIDE(CACTL1 = 0x0059);
|
||||
PROVIDE(CACTL2 = 0x005A);
|
||||
PROVIDE(CAPD = 0x005B);
|
||||
/************************************************************
|
||||
* DAC12
|
||||
************************************************************/
|
||||
PROVIDE(DAC12_0CTL = 0x01C0);
|
||||
PROVIDE(DAC12_1CTL = 0x01C2);
|
||||
PROVIDE(DAC12_0DAT = 0x01C8);
|
||||
PROVIDE(DAC12_1DAT = 0x01CA);
|
||||
/************************************************************
|
||||
* DMA_X
|
||||
************************************************************/
|
||||
PROVIDE(DMACTL0 = 0x0122);
|
||||
PROVIDE(DMACTL1 = 0x0124);
|
||||
PROVIDE(DMAIV = 0x0126);
|
||||
PROVIDE(DMA0CTL = 0x01D0);
|
||||
PROVIDE(DMA1CTL = 0x01DC);
|
||||
PROVIDE(DMA2CTL = 0x01E8);
|
||||
PROVIDE(DMA0SA = 0x01D2);
|
||||
PROVIDE(DMA0SAL = 0x01D2);
|
||||
PROVIDE(DMA0DA = 0x01D6);
|
||||
PROVIDE(DMA0DAL = 0x01D6);
|
||||
PROVIDE(DMA0SZ = 0x01DA);
|
||||
PROVIDE(DMA1SA = 0x01DE);
|
||||
PROVIDE(DMA1SAL = 0x01DE);
|
||||
PROVIDE(DMA1DA = 0x01E2);
|
||||
PROVIDE(DMA1DAL = 0x01E2);
|
||||
PROVIDE(DMA1SZ = 0x01E6);
|
||||
PROVIDE(DMA2SA = 0x01EA);
|
||||
PROVIDE(DMA2SAL = 0x01EA);
|
||||
PROVIDE(DMA2DA = 0x01EE);
|
||||
PROVIDE(DMA2DAL = 0x01EE);
|
||||
PROVIDE(DMA2SZ = 0x01F2);
|
||||
/*************************************************************
|
||||
* Flash Memory
|
||||
*************************************************************/
|
||||
PROVIDE(FCTL1 = 0x0128);
|
||||
PROVIDE(FCTL2 = 0x012A);
|
||||
PROVIDE(FCTL3 = 0x012C);
|
||||
PROVIDE(FCTL4 = 0x01BE);
|
||||
/************************************************************
|
||||
* HARDWARE MULTIPLIER
|
||||
************************************************************/
|
||||
PROVIDE(MPY = 0x0130);
|
||||
PROVIDE(MPYS = 0x0132);
|
||||
PROVIDE(MAC = 0x0134);
|
||||
PROVIDE(MACS = 0x0136);
|
||||
PROVIDE(OP2 = 0x0138);
|
||||
PROVIDE(RESLO = 0x013A);
|
||||
PROVIDE(RESHI = 0x013C);
|
||||
PROVIDE(SUMEXT = 0x013E);
|
||||
/************************************************************
|
||||
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
|
||||
************************************************************/
|
||||
PROVIDE(P1IN = 0x0020);
|
||||
PROVIDE(P1OUT = 0x0021);
|
||||
PROVIDE(P1DIR = 0x0022);
|
||||
PROVIDE(P1IFG = 0x0023);
|
||||
PROVIDE(P1IES = 0x0024);
|
||||
PROVIDE(P1IE = 0x0025);
|
||||
PROVIDE(P1SEL = 0x0026);
|
||||
PROVIDE(P1REN = 0x0027);
|
||||
PROVIDE(P2IN = 0x0028);
|
||||
PROVIDE(P2OUT = 0x0029);
|
||||
PROVIDE(P2DIR = 0x002A);
|
||||
PROVIDE(P2IFG = 0x002B);
|
||||
PROVIDE(P2IES = 0x002C);
|
||||
PROVIDE(P2IE = 0x002D);
|
||||
PROVIDE(P2SEL = 0x002E);
|
||||
PROVIDE(P2REN = 0x002F);
|
||||
/************************************************************
|
||||
* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
|
||||
************************************************************/
|
||||
PROVIDE(P3IN = 0x0018);
|
||||
PROVIDE(P3OUT = 0x0019);
|
||||
PROVIDE(P3DIR = 0x001A);
|
||||
PROVIDE(P3SEL = 0x001B);
|
||||
PROVIDE(P3REN = 0x0010);
|
||||
PROVIDE(P4IN = 0x001C);
|
||||
PROVIDE(P4OUT = 0x001D);
|
||||
PROVIDE(P4DIR = 0x001E);
|
||||
PROVIDE(P4SEL = 0x001F);
|
||||
PROVIDE(P4REN = 0x0011);
|
||||
/************************************************************
|
||||
* DIGITAL I/O Port5/6 Pull up / Pull down Resistors
|
||||
************************************************************/
|
||||
PROVIDE(P5IN = 0x0030);
|
||||
PROVIDE(P5OUT = 0x0031);
|
||||
PROVIDE(P5DIR = 0x0032);
|
||||
PROVIDE(P5SEL = 0x0033);
|
||||
PROVIDE(P5REN = 0x0012);
|
||||
PROVIDE(P6IN = 0x0034);
|
||||
PROVIDE(P6OUT = 0x0035);
|
||||
PROVIDE(P6DIR = 0x0036);
|
||||
PROVIDE(P6SEL = 0x0037);
|
||||
PROVIDE(P6REN = 0x0013);
|
||||
/************************************************************
|
||||
* DIGITAL I/O Port7/8 Pull up / Pull down Resistors
|
||||
************************************************************/
|
||||
PROVIDE(P7IN = 0x0038);
|
||||
PROVIDE(P7OUT = 0x003A);
|
||||
PROVIDE(P7DIR = 0x003C);
|
||||
PROVIDE(P7SEL = 0x003E);
|
||||
PROVIDE(P7REN = 0x0014);
|
||||
PROVIDE(P8IN = 0x0039);
|
||||
PROVIDE(P8OUT = 0x003B);
|
||||
PROVIDE(P8DIR = 0x003D);
|
||||
PROVIDE(P8SEL = 0x003F);
|
||||
PROVIDE(P8REN = 0x0015);
|
||||
PROVIDE(PAIN = 0x0038);
|
||||
PROVIDE(PAOUT = 0x003A);
|
||||
PROVIDE(PADIR = 0x003C);
|
||||
PROVIDE(PASEL = 0x003E);
|
||||
PROVIDE(PAREN = 0x0014);
|
||||
/************************************************************
|
||||
* Brown-Out, Supply Voltage Supervision (SVS)
|
||||
************************************************************/
|
||||
PROVIDE(SVSCTL = 0x0055);
|
||||
/************************************************************
|
||||
* Timer A3
|
||||
************************************************************/
|
||||
PROVIDE(TAIV = 0x012E);
|
||||
PROVIDE(TACTL = 0x0160);
|
||||
PROVIDE(TACCTL0 = 0x0162);
|
||||
PROVIDE(TACCTL1 = 0x0164);
|
||||
PROVIDE(TACCTL2 = 0x0166);
|
||||
PROVIDE(TAR = 0x0170);
|
||||
PROVIDE(TACCR0 = 0x0172);
|
||||
PROVIDE(TACCR1 = 0x0174);
|
||||
PROVIDE(TACCR2 = 0x0176);
|
||||
/************************************************************
|
||||
* Timer B7
|
||||
************************************************************/
|
||||
PROVIDE(TBIV = 0x011E);
|
||||
PROVIDE(TBCTL = 0x0180);
|
||||
PROVIDE(TBCCTL0 = 0x0182);
|
||||
PROVIDE(TBCCTL1 = 0x0184);
|
||||
PROVIDE(TBCCTL2 = 0x0186);
|
||||
PROVIDE(TBCCTL3 = 0x0188);
|
||||
PROVIDE(TBCCTL4 = 0x018A);
|
||||
PROVIDE(TBCCTL5 = 0x018C);
|
||||
PROVIDE(TBCCTL6 = 0x018E);
|
||||
PROVIDE(TBR = 0x0190);
|
||||
PROVIDE(TBCCR0 = 0x0192);
|
||||
PROVIDE(TBCCR1 = 0x0194);
|
||||
PROVIDE(TBCCR2 = 0x0196);
|
||||
PROVIDE(TBCCR3 = 0x0198);
|
||||
PROVIDE(TBCCR4 = 0x019A);
|
||||
PROVIDE(TBCCR5 = 0x019C);
|
||||
PROVIDE(TBCCR6 = 0x019E);
|
||||
/************************************************************
|
||||
* USCI
|
||||
************************************************************/
|
||||
PROVIDE(UCA0CTL0 = 0x0060);
|
||||
PROVIDE(UCA0CTL1 = 0x0061);
|
||||
PROVIDE(UCA0BR0 = 0x0062);
|
||||
PROVIDE(UCA0BR1 = 0x0063);
|
||||
PROVIDE(UCA0MCTL = 0x0064);
|
||||
PROVIDE(UCA0STAT = 0x0065);
|
||||
PROVIDE(UCA0RXBUF = 0x0066);
|
||||
PROVIDE(UCA0TXBUF = 0x0067);
|
||||
PROVIDE(UCA0ABCTL = 0x005D);
|
||||
PROVIDE(UCA0IRTCTL = 0x005E);
|
||||
PROVIDE(UCA0IRRCTL = 0x005F);
|
||||
PROVIDE(UCB0CTL0 = 0x0068);
|
||||
PROVIDE(UCB0CTL1 = 0x0069);
|
||||
PROVIDE(UCB0BR0 = 0x006A);
|
||||
PROVIDE(UCB0BR1 = 0x006B);
|
||||
PROVIDE(UCB0I2CIE = 0x006C);
|
||||
PROVIDE(UCB0STAT = 0x006D);
|
||||
PROVIDE(UCB0RXBUF = 0x006E);
|
||||
PROVIDE(UCB0TXBUF = 0x006F);
|
||||
PROVIDE(UCB0I2COA = 0x0118);
|
||||
PROVIDE(UCB0I2CSA = 0x011A);
|
||||
PROVIDE(UCA1CTL0 = 0x00D0);
|
||||
PROVIDE(UCA1CTL1 = 0x00D1);
|
||||
PROVIDE(UCA1BR0 = 0x00D2);
|
||||
PROVIDE(UCA1BR1 = 0x00D3);
|
||||
PROVIDE(UCA1MCTL = 0x00D4);
|
||||
PROVIDE(UCA1STAT = 0x00D5);
|
||||
PROVIDE(UCA1RXBUF = 0x00D6);
|
||||
PROVIDE(UCA1TXBUF = 0x00D7);
|
||||
PROVIDE(UCA1ABCTL = 0x00CD);
|
||||
PROVIDE(UCA1IRTCTL = 0x00CE);
|
||||
PROVIDE(UCA1IRRCTL = 0x00CF);
|
||||
PROVIDE(UCB1CTL0 = 0x00D8);
|
||||
PROVIDE(UCB1CTL1 = 0x00D9);
|
||||
PROVIDE(UCB1BR0 = 0x00DA);
|
||||
PROVIDE(UCB1BR1 = 0x00DB);
|
||||
PROVIDE(UCB1I2CIE = 0x00DC);
|
||||
PROVIDE(UCB1STAT = 0x00DD);
|
||||
PROVIDE(UCB1RXBUF = 0x00DE);
|
||||
PROVIDE(UCB1TXBUF = 0x00DF);
|
||||
PROVIDE(UCB1I2COA = 0x017C);
|
||||
PROVIDE(UCB1I2CSA = 0x017E);
|
||||
/************************************************************
|
||||
* WATCHDOG TIMER
|
||||
************************************************************/
|
||||
PROVIDE(WDTCTL = 0x0120);
|
||||
/************************************************************
|
||||
* Calibration Data in Info Mem
|
||||
************************************************************/
|
||||
PROVIDE(TLV_CHECKSUM = 0x10C0);
|
||||
PROVIDE(TLV_DCO_30_TAG = 0x10F6);
|
||||
PROVIDE(TLV_DCO_30_LEN = 0x10F7);
|
||||
PROVIDE(TLV_ADC12_1_TAG = 0x10DA);
|
||||
PROVIDE(TLV_ADC12_1_LEN = 0x10DB);
|
||||
/************************************************************
|
||||
* Calibration Data in Info Mem
|
||||
************************************************************/
|
||||
PROVIDE(CALDCO_16MHZ = 0x10F8);
|
||||
PROVIDE(CALBC1_16MHZ = 0x10F9);
|
||||
PROVIDE(CALDCO_12MHZ = 0x10FA);
|
||||
PROVIDE(CALBC1_12MHZ = 0x10FB);
|
||||
PROVIDE(CALDCO_8MHZ = 0x10FC);
|
||||
PROVIDE(CALBC1_8MHZ = 0x10FD);
|
||||
PROVIDE(CALDCO_1MHZ = 0x10FE);
|
||||
PROVIDE(CALBC1_1MHZ = 0x10FF);
|
||||
/************************************************************
|
||||
* Interrupt Vectors (offset from 0xFFC0)
|
||||
************************************************************/
|
||||
/************************************************************
|
||||
* End of Modules
|
||||
************************************************************/
|
||||
@ -24,6 +24,10 @@ config CPU_MODEL_MSP430F2617
|
||||
bool
|
||||
select CPU_FAM_MSP430F
|
||||
|
||||
config CPU_MODEL_MSP430F2618
|
||||
bool
|
||||
select CPU_FAM_MSP430F
|
||||
|
||||
## Definition of specific features
|
||||
config HAS_CPU_MSP430FXYZ
|
||||
bool
|
||||
@ -38,6 +42,7 @@ config CPU_MODEL
|
||||
default "msp430f1611" if CPU_MODEL_MSP430F1611
|
||||
default "msp430f1612" if CPU_MODEL_MSP430F1612
|
||||
default "msp430f2617" if CPU_MODEL_MSP430F2617
|
||||
default "msp430f2618" if CPU_MODEL_MSP430F2618
|
||||
|
||||
config CPU
|
||||
default "msp430fxyz" if CPU_FAM_MSP430F
|
||||
|
||||
Loading…
Reference in New Issue
Block a user