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RIOT/cpu/samd5x/include/periph_cpu.h

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cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
/*
* Copyright (C) 2019 ML!PA Consulting GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_samd5x
* @brief CPU specific definitions for internal peripheral handling
* @{
*
* @file
* @brief CPU specific definitions for internal peripheral handling
*
* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
*/
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
#include <limits.h>
cpu/samd5x: use MHZ() macro
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#include "macros/units.h"
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
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#include "periph_cpu_common.h"
#ifdef __cplusplus
extern "C" {
#endif
cpu/samd5x: allow more flexible selection of CLOCK_CORECLOCK There are some constraints to the oscillators on the samd5x. - DFLL is fixed to run at 48 MHz - DPLL can run at 96 to 200 MHz Always use DFLL for frequencies <= 48 MHz. For frequencies >= 96 MHz, use DPLL directly. For frequencies < 96 MHz, clock DPLL at twice the desired frequency and use a divider.
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/**
* @brief DFLL runs at at fixed frequency of 48 MHz
*/
cpu/samd5x: use MHZ() macro
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#define SAM0_DFLL_FREQ_HZ MHZ(48)
cpu/samd5x: allow more flexible selection of CLOCK_CORECLOCK There are some constraints to the oscillators on the samd5x. - DFLL is fixed to run at 48 MHz - DPLL can run at 96 to 200 MHz Always use DFLL for frequencies <= 48 MHz. For frequencies >= 96 MHz, use DPLL directly. For frequencies < 96 MHz, clock DPLL at twice the desired frequency and use a divider.
2019-09-13 17:32:14 +02:00
cpu/samd5x: allow to use XOSC as clock source Allow to run the main clock and all peripheral clocks off XOSC. This is necessary if we want to use the buck voltage regulator.
2020-03-02 18:06:09 +01:00
/**
 * @brief XOSC is used to generate a fixed frequency of 48 MHz
 */
#define SAM0_XOSC_FREQ_HZ (XOSC0_FREQUENCY ? XOSC0_FREQUENCY : XOSC1_FREQUENCY)
cpu/samd5x: allow more flexible selection of CLOCK_CORECLOCK There are some constraints to the oscillators on the samd5x. - DFLL is fixed to run at 48 MHz - DPLL can run at 96 to 200 MHz Always use DFLL for frequencies <= 48 MHz. For frequencies >= 96 MHz, use DPLL directly. For frequencies < 96 MHz, clock DPLL at twice the desired frequency and use a divider.
2019-09-13 17:32:14 +02:00
/**
* @brief DPLL must run with at least 96 MHz
*/
cpu/samd5x: use MHZ() macro
2020-06-12 15:56:52 +02:00
#define SAM0_DPLL_FREQ_MIN_HZ MHZ(96)
cpu/samd5x: allow more flexible selection of CLOCK_CORECLOCK There are some constraints to the oscillators on the samd5x. - DFLL is fixed to run at 48 MHz - DPLL can run at 96 to 200 MHz Always use DFLL for frequencies <= 48 MHz. For frequencies >= 96 MHz, use DPLL directly. For frequencies < 96 MHz, clock DPLL at twice the desired frequency and use a divider.
2019-09-13 17:32:14 +02:00
/**
* @brief DPLL frequency must not exceed 200 MHz
*/
cpu/samd5x: use MHZ() macro
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#define SAM0_DPLL_FREQ_MAX_HZ MHZ(20)
cpu/samd5x: allow more flexible selection of CLOCK_CORECLOCK There are some constraints to the oscillators on the samd5x. - DFLL is fixed to run at 48 MHz - DPLL can run at 96 to 200 MHz Always use DFLL for frequencies <= 48 MHz. For frequencies >= 96 MHz, use DPLL directly. For frequencies < 96 MHz, clock DPLL at twice the desired frequency and use a divider.
2019-09-13 17:32:14 +02:00
cpu/sam0_common: distribute PM_NUM_MODES among siblings Also adapt the defines to the documentation - CPUs define up to 4 power modes (from zero, the lowest power mode, to PM_NUM_MODES-1, the highest) - >> there is an implicit extra idle mode (which has the number PM_NUM_MODES) << Previously on saml21 this would always generate pm_set(3) which is an illegal state. Now pm_layered will correctly generate pm_set(2) for IDLE modes. Idle power consumption dropped from 750µA to 368µA and wake-up from standby is also possible. (Before it would just enter STANDBY again as the mode register was never written with the illegal value.)
2020-02-25 16:14:15 +01:00
/**
* @name Power mode configuration
* @{
*/
#define PM_NUM_MODES (3)
/** @} */
cpu/sam0: use defines for GCLK IDs Give the clocks explicit names to better identify their meaning.
2019-12-16 19:41:16 +01:00
/**
* @name SAMD5x GCLK definitions
* @{
*/
enum {
cpu/samd5x: rename GCLK defines Now that the GCLK defines are not always at a fixed frequency, rename them to better reflect this.
2020-06-16 17:41:59 +02:00
SAM0_GCLK_MAIN = 0, /**< 120 MHz main clock */
SAM0_GCLK_32KHZ, /**< 32 kHz clock */
SAM0_GCLK_TIMER, /**< 4-8 MHz clock for xTimer */
SAM0_GCLK_PERIPH, /**< 12-48 MHz (DFLL) clock */
cpu/sam0: use defines for GCLK IDs Give the clocks explicit names to better identify their meaning.
2019-12-16 19:41:16 +01:00
};
/** @} */
cpu/samd5x: rename GCLK defines Now that the GCLK defines are not always at a fixed frequency, rename them to better reflect this.
2020-06-16 17:41:59 +02:00
/**
* @name GCLK compatibility definitions
* @{
*/
#define SAM0_GCLK_8MHZ SAM0_GCLK_TIMER
#define SAM0_GCLK_48MHZ SAM0_GCLK_PERIPH
/** @} */
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
/**
* @brief Override SPI hardware chip select macro
*
* As of now, we do not support HW CS, so we always set it to a fixed value
*/
#define SPI_HWCS(x) (UINT_MAX - 1)
cpu/samd5x: add ADC resolution type
2020-08-07 19:30:46 +02:00
#ifndef DOXYGEN
#define HAVE_ADC_RES_T
typedef enum {
ADC_RES_6BIT = 0xff, /**< not supported */
ADC_RES_8BIT = ADC_CTRLB_RESSEL_8BIT, /**< ADC resolution: 8 bit */
ADC_RES_10BIT = ADC_CTRLB_RESSEL_10BIT, /**< ADC resolution: 10 bit */
ADC_RES_12BIT = ADC_CTRLB_RESSEL_12BIT, /**< ADC resolution: 12 bit */
ADC_RES_14BIT = 0xfe, /**< not supported */
ADC_RES_16BIT = 0xfd /**< not supported */
} adc_res_t;
/** @} */
#endif /* DOXYGEN */
cpu/sam0_common: implement periph/dac The sam0 MCUs all have a DAC peripheral. The DAC has a resulution of 10 or 12 bits and can have one or two output channels. The output pins are always hard-wired to PA2 for DAC0 and PA5 for DAC1 if it exists. On the same54-xpro I would only get a max value of ~1V when using the internal reference, so I configured it to use an external voltage reference. The external reference pin is hard-wired to PA3, so you'll have to connect that to 3.3V to get results.
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/**
* @brief The MCU has a 12 bit DAC
*/
#define DAC_RES_BITS (12)
/**
* @brief The MCU has two DAC outputs.
*/
#define DAC_NUMOF (2)
cpu/samd5x: add unified rtt configuration
2020-06-17 12:42:39 +02:00
/**
* @name Real time counter configuration
* @{
*/
#define RTT_MAX_VALUE (0xffffffff)
#define RTT_CLOCK_FREQUENCY (32768U) /* in Hz */
#define RTT_MIN_FREQUENCY (RTT_CLOCK_FREQUENCY / 1024U) /* in Hz */
#define RTT_MAX_FREQUENCY (RTT_CLOCK_FREQUENCY) /* in Hz */
/** @} */
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CPU_H */
/** @} */
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