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If the board defines `FMC_RAM_ADDR` and `FMC_RAM_LEN`, the FMC RAM is used a additional heap if module `periph_fmc` is enabled. For that purpose - the linker symbols `_fmc_ram_addr` and `_fmc_ram_len` are set, - a memory region `fcmram` is added in linker script for the FMC RAM based on these `_fcm_ram_*` linker symbols - a section for the FMC RAM is defined in this memory region that defines the heap by setting `_sheap3` and `_eheap3` and - the number of heaps is set to 4 since to use `_sheap3` and `_eheap3` even though `_sheap1` and `_eheap1` (the backup RAM) and `_sheap2` and `_eheap2` (SRAM4) are not present.
52 lines
1.2 KiB
Plaintext
52 lines
1.2 KiB
Plaintext
/*
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* Copyright (C) 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @addtogroup cpu_cortexm_common
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* @{
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*
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* @file
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* @brief Memory definitions for the Cortex-M family
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*
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* @author Francisco Acosta <francisco.acosta@inria.fr>
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*
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* @}
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*/
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ccmram_length = DEFINED( _ccmram_len ) ? _ccmram_len : 0x0 ;
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sram4_addr = DEFINED( _sram4_length ) ? 0x28000000 : 0x0 ;
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sram4_length = DEFINED( _sram4_length ) ? _sram4_length : 0x0 ;
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fmc_ram_addr = DEFINED( _fmc_ram_addr ) ? _fmc_ram_addr : 0x0 ;
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fmc_ram_len = DEFINED( _fmc_ram_len ) ? _fmc_ram_len : 0x0 ;
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MEMORY
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{
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ccmram : ORIGIN = 0x10000000, LENGTH = ccmram_length
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sram4 : ORIGIN = sram4_addr, LENGTH = sram4_length
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fmcram : ORIGIN = fmc_ram_addr, LENGTH = fmc_ram_len
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}
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SECTIONS
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{
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.heap2 ALIGN(4) (NOLOAD) :
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{
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_sheap2 = ORIGIN(sram4);
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_eheap2 = ORIGIN(sram4) + LENGTH(sram4);
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} > sram4
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.heap4 ALIGN(4) (NOLOAD) :
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{
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_sheap3 = ORIGIN(fmcram);
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_eheap3 = ORIGIN(fmcram) + LENGTH(fmcram);
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} > fmcram
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}
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INCLUDE cortexm.ld
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