cpu/stm32: add FMC RAM as heap

If the board defines `FMC_RAM_ADDR` and `FMC_RAM_LEN`, the FMC RAM is used a additional heap if module `periph_fmc` is enabled.

For that purpose
- the linker symbols `_fmc_ram_addr` and `_fmc_ram_len` are set,
- a memory region `fcmram` is added in linker script for the FMC RAM based on these `_fcm_ram_*` linker symbols
- a section for the FMC RAM is defined in this memory region that defines the heap by setting `_sheap3` and `_eheap3` and
- the number of heaps is set to 4 since to use `_sheap3` and `_eheap3` even though `_sheap1` and `_eheap1` (the backup RAM) and `_sheap2` and `_eheap2` (SRAM4) are not present.

cpu/stm32/Makefile.include

@@ -57,7 +57,6 @@ info-stm32:
 	@$(COLOR_ECHO) "\tROM size:\t$(ROM_LEN) ($(FLASHSIZE) Bytes)"
 	@$(COLOR_ECHO) "\tRAM size:\t$(RAM_LEN_K)KiB"
 
-
 ifneq (,$(CCMRAM_LEN))
   LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_ccmram_length=$(CCMRAM_LEN)
 endif
@@ -65,6 +64,17 @@ ifneq (,$(SRAM4_LEN))
   LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_sram4_length=$(SRAM4_LEN)
 endif
 
+# if the board uses a FMC RAM, all 4 heaps have to be used even if
+# some of them are not available
+ifneq (,$(filter periph_fmc_sdram periph_fmc_nor_sram,$(USEMODULE)))
+  ifneq (,$(FMC_RAM_LEN))
+    LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_fmc_ram_addr=$(FMC_RAM_ADDR)
+    LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_fmc_ram_len=$(FMC_RAM_LEN)
+    CFLAGS += -DCPU_HAS_FMC_RAM=1
+    CFLAGS += -DNUM_HEAPS=4
+  endif
+endif
+
 VECTORS_O ?= $(BINDIR)/stm32_vectors/$(CPU_LINE).o
 VECTORS_FILE = $(RIOTCPU)/stm32/vectors/$(CPU_LINE).c
 BUILDDEPS += $(VECTORS_FILE)

cpu/stm32/ldscripts/stm32.ld

@@ -23,10 +23,14 @@ ccmram_length = DEFINED( _ccmram_len ) ? _ccmram_len : 0x0 ;
 sram4_addr = DEFINED( _sram4_length ) ? 0x28000000 : 0x0 ;
 sram4_length = DEFINED( _sram4_length ) ? _sram4_length : 0x0 ;
 
+fmc_ram_addr = DEFINED( _fmc_ram_addr ) ? _fmc_ram_addr : 0x0 ;
+fmc_ram_len = DEFINED( _fmc_ram_len ) ? _fmc_ram_len : 0x0 ;
+
 MEMORY
 {
     ccmram  : ORIGIN = 0x10000000, LENGTH = ccmram_length
     sram4   : ORIGIN = sram4_addr, LENGTH = sram4_length
+    fmcram  : ORIGIN = fmc_ram_addr, LENGTH = fmc_ram_len
 }
 
 SECTIONS
@@ -36,6 +40,12 @@ SECTIONS
         _sheap2 = ORIGIN(sram4);
         _eheap2 = ORIGIN(sram4) + LENGTH(sram4);
     } > sram4
+
+    .heap4 ALIGN(4) (NOLOAD) :
+    {
+        _sheap3 = ORIGIN(fmcram);
+        _eheap3 = ORIGIN(fmcram) + LENGTH(fmcram);
+    } > fmcram
 }
 
 INCLUDE cortexm.ld