mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
159 lines
3.8 KiB
C
159 lines
3.8 KiB
C
/*
|
|
* Copyright (C) 2019 Inria
|
|
*
|
|
* This file is subject to the terms and conditions of the GNU Lesser
|
|
* General Public License v2.1. See the file LICENSE in the top level
|
|
* directory for more details.
|
|
*/
|
|
|
|
/**
|
|
* @ingroup boards_lsn50
|
|
* @{
|
|
*
|
|
* @file
|
|
* @brief Peripheral MCU configuration for the LSN50 board
|
|
*
|
|
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
|
*/
|
|
|
|
#ifndef PERIPH_CONF_H
|
|
#define PERIPH_CONF_H
|
|
|
|
/* Add specific clock configuration (HSE, LSE) for this board here */
|
|
#ifndef CONFIG_BOARD_HAS_LSE
|
|
#define CONFIG_BOARD_HAS_LSE 1
|
|
#endif
|
|
|
|
#include "periph_cpu.h"
|
|
#include "clk_conf.h"
|
|
#include "cfg_rtt_default.h"
|
|
#include "cfg_timer_tim2.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
/**
|
|
* @name DMA streams configuration
|
|
* @{
|
|
*/
|
|
static const dma_conf_t dma_config[] = {
|
|
{ .stream = 1 }, /* channel 2 */
|
|
{ .stream = 2 }, /* channel 3 */
|
|
{ .stream = 3 }, /* channel 4 */
|
|
{ .stream = 4 }, /* channel 5 */
|
|
{ .stream = 5 }, /* channel 6 */
|
|
};
|
|
|
|
#define DMA_SHARED_ISR_0 isr_dma1_channel2_3
|
|
#define DMA_SHARED_ISR_0_STREAMS { 0, 1 } /* Indexes 0 and 1 of dma_config share the same isr */
|
|
#define DMA_SHARED_ISR_1 isr_dma1_channel4_5_6_7
|
|
#define DMA_SHARED_ISR_1_STREAMS { 2, 3, 4 } /* Indexes 2, 3 and 4 of dma_config share the same isr */
|
|
|
|
#define DMA_NUMOF ARRAY_SIZE(dma_config)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name UART configuration
|
|
* @{
|
|
*/
|
|
static const uart_conf_t uart_config[] = {
|
|
{
|
|
.dev = USART1,
|
|
.rcc_mask = RCC_APB2ENR_USART1EN,
|
|
.rx_pin = GPIO_PIN(PORT_A, 10),
|
|
.tx_pin = GPIO_PIN(PORT_A, 9),
|
|
.rx_af = GPIO_AF4,
|
|
.tx_af = GPIO_AF4,
|
|
.bus = APB2,
|
|
.irqn = USART1_IRQn,
|
|
.type = STM32_USART,
|
|
.clk_src = 0, /* Use APB clock */
|
|
#ifdef MODULE_PERIPH_DMA
|
|
.dma = 0,
|
|
.dma_chan = 3,
|
|
#endif
|
|
},
|
|
{
|
|
.dev = USART2,
|
|
.rcc_mask = RCC_APB1ENR_USART2EN,
|
|
.rx_pin = GPIO_PIN(PORT_A, 3),
|
|
.tx_pin = GPIO_PIN(PORT_A, 2),
|
|
.rx_af = GPIO_AF4,
|
|
.tx_af = GPIO_AF4,
|
|
.bus = APB1,
|
|
.irqn = USART2_IRQn,
|
|
.type = STM32_USART,
|
|
.clk_src = 0, /* Use APB clock */
|
|
#ifdef MODULE_PERIPH_DMA
|
|
.dma = 2,
|
|
.dma_chan = 4,
|
|
#endif
|
|
},
|
|
};
|
|
|
|
#define UART_0_ISR (isr_usart1)
|
|
#define UART_1_ISR (isr_usart2)
|
|
|
|
#define UART_NUMOF ARRAY_SIZE(uart_config)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name SPI configuration
|
|
* @{
|
|
*/
|
|
static const spi_conf_t spi_config[] = {
|
|
{
|
|
.dev = SPI1, /* connected to SX1276 */
|
|
.mosi_pin = GPIO_PIN(PORT_A, 7),
|
|
.miso_pin = GPIO_PIN(PORT_A, 6),
|
|
.sclk_pin = GPIO_PIN(PORT_A, 5),
|
|
.cs_pin = SPI_CS_UNDEF,
|
|
.mosi_af = GPIO_AF0,
|
|
.miso_af = GPIO_AF0,
|
|
.sclk_af = GPIO_AF0,
|
|
.cs_af = GPIO_AF0,
|
|
.rccmask = RCC_APB2ENR_SPI1EN,
|
|
.apbbus = APB2,
|
|
#ifdef MODULE_PERIPH_DMA
|
|
.tx_dma = 1,
|
|
.tx_dma_chan = 1,
|
|
.rx_dma = 0,
|
|
.rx_dma_chan = 1,
|
|
#endif
|
|
},
|
|
};
|
|
|
|
#define SPI_NUMOF ARRAY_SIZE(spi_config)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name I2C configuration
|
|
* @{
|
|
*/
|
|
static const i2c_conf_t i2c_config[] = {
|
|
{
|
|
.dev = I2C1,
|
|
.speed = I2C_SPEED_NORMAL,
|
|
.scl_pin = GPIO_PIN(PORT_B, 6),
|
|
.sda_pin = GPIO_PIN(PORT_B, 7),
|
|
.scl_af = GPIO_AF4,
|
|
.sda_af = GPIO_AF4,
|
|
.bus = APB1,
|
|
.rcc_mask = RCC_APB1ENR_I2C1EN,
|
|
.irqn = I2C1_IRQn
|
|
}
|
|
};
|
|
|
|
#define I2C_0_ISR isr_i2c1
|
|
|
|
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
|
|
/** @} */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* PERIPH_CONF_H */
|
|
/** @} */
|