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133 lines
3.5 KiB
C
133 lines
3.5 KiB
C
/*
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* Copyright (C) 2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Configure STM32G4 clock
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef G4_CFG_CLOCK_DEFAULT_H
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#define G4_CFG_CLOCK_DEFAULT_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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* @{
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*/
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#ifndef CONFIG_USE_CLOCK_PLL
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
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#define CONFIG_USE_CLOCK_PLL (0)
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#else
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#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#ifndef CONFIG_USE_CLOCK_HSE
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#define CONFIG_USE_CLOCK_HSE (0)
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#endif /* CONFIG_USE_CLOCK_HSE */
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#ifndef CONFIG_USE_CLOCK_HSI
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#define CONFIG_USE_CLOCK_HSI (0)
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#endif /* CONFIG_USE_CLOCK_HSI */
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#if CONFIG_USE_CLOCK_PLL && \
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(CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI)
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#error "Cannot use PLL as clock source with other clock configurations"
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#endif
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#if CONFIG_USE_CLOCK_HSE && \
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSI)
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#error "Cannot use HSE as clock source with other clock configurations"
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#endif
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#if CONFIG_USE_CLOCK_HSI && \
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE)
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#error "Cannot use HSI as clock source with other clock configurations"
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#endif
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE (0)
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#endif
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#ifndef CLOCK_HSE
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#define CLOCK_HSE MHZ(24)
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#endif
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#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
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#error "HSE clock frequency must be between 4MHz and 48MHz"
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#endif
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE (0)
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#endif
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#if CONFIG_BOARD_HAS_LSE
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#define CLOCK_LSE (1)
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#else
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#define CLOCK_LSE (0)
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#endif
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#define CLOCK_HSI MHZ(16)
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#if CONFIG_USE_CLOCK_HSI
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#define CLOCK_CORECLOCK (CLOCK_HSI)
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#elif CONFIG_USE_CLOCK_HSE
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#if CONFIG_BOARD_HAS_HSE == 0
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#error "The board doesn't provide an HSE oscillator"
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#endif
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#define CLOCK_CORECLOCK (CLOCK_HSE)
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#elif CONFIG_USE_CLOCK_PLL
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/* The following parameters configure a 170MHz system clock with HSI16 as input clock */
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#ifndef CONFIG_CLOCK_PLL_M
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#define CONFIG_CLOCK_PLL_M (4)
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#endif
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#ifndef CONFIG_CLOCK_PLL_N
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#define CONFIG_CLOCK_PLL_N (85)
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#endif
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#ifndef CONFIG_CLOCK_PLL_R
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#define CONFIG_CLOCK_PLL_R (2)
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#endif
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#if CONFIG_BOARD_HAS_HSE
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#define CLOCK_PLL_SRC (CLOCK_HSE)
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#else /* CLOCK_HSI */
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#define CLOCK_PLL_SRC (CLOCK_HSI)
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#endif
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#define CLOCK_CORECLOCK \
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((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
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#if CLOCK_CORECLOCK > MHZ(170)
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#error "SYSCLK cannot exceed 170MHz"
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#define CLOCK_AHB CLOCK_CORECLOCK /* max: 170MHz */
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (1)
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#endif
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#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 170MHz */
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (1)
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#endif
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#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 170MHz */
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#ifdef __cplusplus
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}
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#endif
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#endif /* G4_CFG_CLOCK_DEFAULT_H */
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/** @} */
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