mirror of
https://github.com/RIOT-OS/RIOT.git
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277 lines
5.5 KiB
Plaintext
277 lines
5.5 KiB
Plaintext
# Copyright (c) 2020 Inria
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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#
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menu "STM32 clock configuration"
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depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1
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choice
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bool "Clock source selection"
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default USE_CLOCK_PLL
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config USE_CLOCK_PLL
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bool "PLL"
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config USE_CLOCK_MSI
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bool "Use direct multi-speed frequency internal oscillator (MSI)"
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depends on CPU_FAM_L0 || CPU_FAM_L1
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config USE_CLOCK_HSE
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bool "Direct High frequency external oscillator (HSE)"
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depends on BOARD_HAS_HSE
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config USE_CLOCK_HSI
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bool "Direct High frequency internal oscillator (HSI16)"
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endchoice
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if CPU_FAM_G0 || CPU_FAM_G4
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config CLOCK_PLL_M
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int "M: PLLIN division factor" if USE_CLOCK_PLL
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default 1 if CPU_FAM_G0
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default 4 if CPU_FAM_G4
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default 6 if CPU_FAM_G4 && BOARD_HAS_HSE
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range 1 8 if CPU_FAM_G0
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range 1 16 if CPU_FAM_G4
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config CLOCK_PLL_N
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int "N: PLLIN multiply factor" if USE_CLOCK_PLL
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default 20 if CPU_FAM_G0
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default 40 if CPU_FAM_G4
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range 8 86 if CPU_FAM_G0
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range 8 127 if CPU_FAM_G4
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if CPU_FAM_G0
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config CLOCK_PLL_R
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int "Q: VCO division factor" if USE_CLOCK_PLL
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default 6 if BOARD_HAS_HSE
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default 5
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range 2 8
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endif # CPU_FAM_G0
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if CPU_FAM_G4
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choice
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bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if USE_CLOCK_PLL
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default PLL_R_DIV_2
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config PLL_R_DIV_2
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bool "Divide by 2"
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config PLL_R_DIV_4
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bool "Divide by 4"
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config PLL_R_DIV_6
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bool "Divide by 6"
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config PLL_R_DIV_8
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bool "Divide by 8"
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endchoice
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config CLOCK_PLL_R
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int
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default 2 if PLL_R_DIV_2
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default 4 if PLL_R_DIV_4
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default 6 if PLL_R_DIV_6
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default 8 if PLL_R_DIV_8
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endif # CPU_FAM_G4
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if CPU_FAM_G0
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choice
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bool "HSISYS division factor" if USE_CLOCK_HSI
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default CLOCK_HSISYS_DIV_1
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config CLOCK_HSISYS_DIV_1
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bool "Divide HSISYS by 1"
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config CLOCK_HSISYS_DIV_2
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bool "Divide HSISYS by 2"
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config CLOCK_HSISYS_DIV_4
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bool "Divide HSISYS by 4"
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config CLOCK_HSISYS_DIV_8
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bool "Divide HSISYS by 8"
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config CLOCK_HSISYS_DIV_16
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bool "Divide HSISYS by 16"
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config CLOCK_HSISYS_DIV_32
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bool "Divide HSISYS by 32"
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config CLOCK_HSISYS_DIV_64
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bool "Divide HSISYS by 64"
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config CLOCK_HSISYS_DIV_128
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bool "Divide HSISYS by 128"
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endchoice
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config CLOCK_HSISYS_DIV
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int
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default 1 if CLOCK_HSISYS_DIV_1
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default 2 if CLOCK_HSISYS_DIV_2
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default 4 if CLOCK_HSISYS_DIV_4
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default 8 if CLOCK_HSISYS_DIV_8
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default 16 if CLOCK_HSISYS_DIV_16
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default 32 if CLOCK_HSISYS_DIV_32
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default 64 if CLOCK_HSISYS_DIV_64
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default 128 if CLOCK_HSISYS_DIV_128
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endif # CPU_FAM_G0
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endif # CPU_FAM_G0 || CPU_FAM_G4
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if CPU_FAM_L0 || CPU_FAM_L1
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config CLOCK_PLL_DIV
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int "Main PLL division factor" if USE_CLOCK_PLL
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default 2
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range 2 4
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choice
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bool "Main PLL multiply factor" if USE_CLOCK_PLL
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default PLL_MUL_4
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config PLL_MUL_3
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bool "Multiply by 3"
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config PLL_MUL_4
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bool "Multiply by 4"
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config PLL_MUL_6
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bool "Multiply by 6"
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config PLL_MUL_8
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bool "Multiply by 8"
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config PLL_MUL_12
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bool "Multiply by 12"
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config PLL_MUL_16
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bool "Multiply by 16"
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config PLL_MUL_24
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bool "Multiply by 24"
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config PLL_MUL_32
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bool "Multiply by 32"
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config PLL_MUL_48
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bool "Multiply by 48"
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endchoice
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config CLOCK_PLL_MUL
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int
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default 3 if PLL_MUL_3
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default 4 if PLL_MUL_4
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default 6 if PLL_MUL_6
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default 8 if PLL_MUL_8
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default 12 if PLL_MUL_12
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default 16 if PLL_MUL_16
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default 24 if PLL_MUL_24
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default 32 if PLL_MUL_32
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default 48 if PLL_MUL_48
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choice
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bool "Desired MSI clock frequency" if USE_CLOCK_MSI
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default CLOCK_MSI_4MHZ
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config CLOCK_MSI_65KHZ
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bool "65.536kHz"
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config CLOCK_MSI_130KHZ
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bool "131.072kHz"
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config CLOCK_MSI_260KHZ
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bool "262.144kHz"
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config CLOCK_MSI_520KHZ
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bool "524.288kHz"
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config CLOCK_MSI_1MHZ
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bool "1.048MHz"
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config CLOCK_MSI_2MHZ
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bool "2.097MHz"
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config CLOCK_MSI_4MHZ
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bool "4.194MHz"
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endchoice
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config CLOCK_MSI
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int
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default 65536 if CLOCK_MSI_65KHZ
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default 131072 if CLOCK_MSI_130KHZ
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default 262144 if CLOCK_MSI_260KHZ
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default 524288 if CLOCK_MSI_520KHZ
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default 1048000 if CLOCK_MSI_1MHZ
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default 2097000 if CLOCK_MSI_2MHZ
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default 4194000 if CLOCK_MSI_4MHZ
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endif # CPU_FAM_L0 || CPU_FAM_L1
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choice
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bool "APB1 prescaler (division factor of HCLK to produce PCLK1)"
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default CLOCK_APB1_DIV_1
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config CLOCK_APB1_DIV_1
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bool "Divide HCLK by 1"
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config CLOCK_APB1_DIV_2
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bool "Divide HCLK by 2"
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config CLOCK_APB1_DIV_4
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bool "Divide HCLK by 4"
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config CLOCK_APB1_DIV_8
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bool "Divide HCLK by 8"
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config CLOCK_APB1_DIV_16
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bool "Divide HCLK by 16"
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endchoice
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config CLOCK_APB1_DIV
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int
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default 1 if CLOCK_APB1_DIV_1
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default 2 if CLOCK_APB1_DIV_2
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default 4 if CLOCK_APB1_DIV_4
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default 8 if CLOCK_APB1_DIV_8
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default 16 if CLOCK_APB1_DIV_16
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choice
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bool "APB2 prescaler (division factor of HCLK to produce PCLK2)"
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depends on CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1
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default CLOCK_APB2_DIV_1
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config CLOCK_APB2_DIV_1
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bool "Divide HCLK by 1"
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config CLOCK_APB2_DIV_2
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bool "Divide HCLK by 2"
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config CLOCK_APB2_DIV_4
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bool "Divide HCLK by 4"
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config CLOCK_APB2_DIV_8
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bool "Divide HCLK by 8"
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config CLOCK_APB2_DIV_16
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bool "Divide HCLK by 16"
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endchoice
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config CLOCK_APB2_DIV
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int
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default 1 if CLOCK_APB2_DIV_1
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default 2 if CLOCK_APB2_DIV_2
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default 4 if CLOCK_APB2_DIV_4
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default 8 if CLOCK_APB2_DIV_8
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default 16 if CLOCK_APB2_DIV_16
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endmenu
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