# Copyright (c) 2020 Inria # # This file is subject to the terms and conditions of the GNU Lesser # General Public License v2.1. See the file LICENSE in the top level # directory for more details. # menu "STM32 clock configuration" depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 choice bool "Clock source selection" default USE_CLOCK_PLL config USE_CLOCK_PLL bool "PLL" config USE_CLOCK_MSI bool "Use direct multi-speed frequency internal oscillator (MSI)" depends on CPU_FAM_L0 || CPU_FAM_L1 config USE_CLOCK_HSE bool "Direct High frequency external oscillator (HSE)" depends on BOARD_HAS_HSE config USE_CLOCK_HSI bool "Direct High frequency internal oscillator (HSI16)" endchoice if CPU_FAM_G0 || CPU_FAM_G4 config CLOCK_PLL_M int "M: PLLIN division factor" if USE_CLOCK_PLL default 1 if CPU_FAM_G0 default 4 if CPU_FAM_G4 default 6 if CPU_FAM_G4 && BOARD_HAS_HSE range 1 8 if CPU_FAM_G0 range 1 16 if CPU_FAM_G4 config CLOCK_PLL_N int "N: PLLIN multiply factor" if USE_CLOCK_PLL default 20 if CPU_FAM_G0 default 40 if CPU_FAM_G4 range 8 86 if CPU_FAM_G0 range 8 127 if CPU_FAM_G4 if CPU_FAM_G0 config CLOCK_PLL_R int "Q: VCO division factor" if USE_CLOCK_PLL default 6 if BOARD_HAS_HSE default 5 range 2 8 endif # CPU_FAM_G0 if CPU_FAM_G4 choice bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if USE_CLOCK_PLL default PLL_R_DIV_2 config PLL_R_DIV_2 bool "Divide by 2" config PLL_R_DIV_4 bool "Divide by 4" config PLL_R_DIV_6 bool "Divide by 6" config PLL_R_DIV_8 bool "Divide by 8" endchoice config CLOCK_PLL_R int default 2 if PLL_R_DIV_2 default 4 if PLL_R_DIV_4 default 6 if PLL_R_DIV_6 default 8 if PLL_R_DIV_8 endif # CPU_FAM_G4 if CPU_FAM_G0 choice bool "HSISYS division factor" if USE_CLOCK_HSI default CLOCK_HSISYS_DIV_1 config CLOCK_HSISYS_DIV_1 bool "Divide HSISYS by 1" config CLOCK_HSISYS_DIV_2 bool "Divide HSISYS by 2" config CLOCK_HSISYS_DIV_4 bool "Divide HSISYS by 4" config CLOCK_HSISYS_DIV_8 bool "Divide HSISYS by 8" config CLOCK_HSISYS_DIV_16 bool "Divide HSISYS by 16" config CLOCK_HSISYS_DIV_32 bool "Divide HSISYS by 32" config CLOCK_HSISYS_DIV_64 bool "Divide HSISYS by 64" config CLOCK_HSISYS_DIV_128 bool "Divide HSISYS by 128" endchoice config CLOCK_HSISYS_DIV int default 1 if CLOCK_HSISYS_DIV_1 default 2 if CLOCK_HSISYS_DIV_2 default 4 if CLOCK_HSISYS_DIV_4 default 8 if CLOCK_HSISYS_DIV_8 default 16 if CLOCK_HSISYS_DIV_16 default 32 if CLOCK_HSISYS_DIV_32 default 64 if CLOCK_HSISYS_DIV_64 default 128 if CLOCK_HSISYS_DIV_128 endif # CPU_FAM_G0 endif # CPU_FAM_G0 || CPU_FAM_G4 if CPU_FAM_L0 || CPU_FAM_L1 config CLOCK_PLL_DIV int "Main PLL division factor" if USE_CLOCK_PLL default 2 range 2 4 choice bool "Main PLL multiply factor" if USE_CLOCK_PLL default PLL_MUL_4 config PLL_MUL_3 bool "Multiply by 3" config PLL_MUL_4 bool "Multiply by 4" config PLL_MUL_6 bool "Multiply by 6" config PLL_MUL_8 bool "Multiply by 8" config PLL_MUL_12 bool "Multiply by 12" config PLL_MUL_16 bool "Multiply by 16" config PLL_MUL_24 bool "Multiply by 24" config PLL_MUL_32 bool "Multiply by 32" config PLL_MUL_48 bool "Multiply by 48" endchoice config CLOCK_PLL_MUL int default 3 if PLL_MUL_3 default 4 if PLL_MUL_4 default 6 if PLL_MUL_6 default 8 if PLL_MUL_8 default 12 if PLL_MUL_12 default 16 if PLL_MUL_16 default 24 if PLL_MUL_24 default 32 if PLL_MUL_32 default 48 if PLL_MUL_48 choice bool "Desired MSI clock frequency" if USE_CLOCK_MSI default CLOCK_MSI_4MHZ config CLOCK_MSI_65KHZ bool "65.536kHz" config CLOCK_MSI_130KHZ bool "131.072kHz" config CLOCK_MSI_260KHZ bool "262.144kHz" config CLOCK_MSI_520KHZ bool "524.288kHz" config CLOCK_MSI_1MHZ bool "1.048MHz" config CLOCK_MSI_2MHZ bool "2.097MHz" config CLOCK_MSI_4MHZ bool "4.194MHz" endchoice config CLOCK_MSI int default 65536 if CLOCK_MSI_65KHZ default 131072 if CLOCK_MSI_130KHZ default 262144 if CLOCK_MSI_260KHZ default 524288 if CLOCK_MSI_520KHZ default 1048000 if CLOCK_MSI_1MHZ default 2097000 if CLOCK_MSI_2MHZ default 4194000 if CLOCK_MSI_4MHZ endif # CPU_FAM_L0 || CPU_FAM_L1 choice bool "APB1 prescaler (division factor of HCLK to produce PCLK1)" default CLOCK_APB1_DIV_1 config CLOCK_APB1_DIV_1 bool "Divide HCLK by 1" config CLOCK_APB1_DIV_2 bool "Divide HCLK by 2" config CLOCK_APB1_DIV_4 bool "Divide HCLK by 4" config CLOCK_APB1_DIV_8 bool "Divide HCLK by 8" config CLOCK_APB1_DIV_16 bool "Divide HCLK by 16" endchoice config CLOCK_APB1_DIV int default 1 if CLOCK_APB1_DIV_1 default 2 if CLOCK_APB1_DIV_2 default 4 if CLOCK_APB1_DIV_4 default 8 if CLOCK_APB1_DIV_8 default 16 if CLOCK_APB1_DIV_16 choice bool "APB2 prescaler (division factor of HCLK to produce PCLK2)" depends on CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 default CLOCK_APB2_DIV_1 config CLOCK_APB2_DIV_1 bool "Divide HCLK by 1" config CLOCK_APB2_DIV_2 bool "Divide HCLK by 2" config CLOCK_APB2_DIV_4 bool "Divide HCLK by 4" config CLOCK_APB2_DIV_8 bool "Divide HCLK by 8" config CLOCK_APB2_DIV_16 bool "Divide HCLK by 16" endchoice config CLOCK_APB2_DIV int default 1 if CLOCK_APB2_DIV_1 default 2 if CLOCK_APB2_DIV_2 default 4 if CLOCK_APB2_DIV_4 default 8 if CLOCK_APB2_DIV_8 default 16 if CLOCK_APB2_DIV_16 endmenu