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21fd1f9258
In preparation for adding support for the QN908x cpus, this patch adds a pristine copy of the vendor SDK files needed for initial support. The only modification to these files is to add '#ifdef __cplusplus' guards to all the header files, even if not needed or already present as '#if defined(__cplusplus)', to make sure ./dist/tools/externc/check.sh check passes. These files are located under vendor/ directories (both cpu/qn908x/include/vendor/ and cpu/qn908x/vendor/) and are part of NXP's SDK for the QN908x family available for download from: https://mcuxpresso.nxp.com/en/builder The files included in these vendor/ directories are released by NXP under an Open Source license as described in each file, but only the files used by the next patch are included here.
260 lines
8.2 KiB
C
260 lines
8.2 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_IOCON_H_
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#define _FSL_IOCON_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup qn_iocon
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* @{
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*/
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/*! @file */
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define IOCON SYSCON
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/*! @name Driver version */
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/*@{*/
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/*! @brief IOCON driver version 2.0.0. */
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#define LPC_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
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/*@}*/
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/**
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* @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format
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*/
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typedef struct _iocon_group
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{
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uint32_t port : 8; /* Pin port */
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uint32_t pin : 8; /* Pin number */
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uint32_t modefunc : 16; /* Function and mode */
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} iocon_group_t;
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/**
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* @brief IOCON function, mode and drive selection definitions
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* @note See the User Manual for specific drive levels, modes and functions supported by the various pins.
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*/
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#define IOCON_FUNC0 0x0U /*!< Selects pin function 0 */
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#define IOCON_FUNC1 0x1U /*!< Selects pin function 1 */
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#define IOCON_FUNC2 0x2U /*!< Selects pin function 2 */
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#define IOCON_FUNC3 0x3U /*!< Selects pin function 3 */
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#define IOCON_FUNC4 0x4U /*!< Selects pin function 4 */
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#define IOCON_FUNC5 0x5U /*!< Selects pin function 5 */
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#define IOCON_FUNC6 0x6U /*!< Selects pin function 6 */
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#define IOCON_FUNC7 0x7U /*!< Selects pin function 7 */
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#define IOCON_MODE_HIGHZ (0x0U << 4U) /*!< Selects High-Z function */
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#define IOCON_MODE_PULLDOWN (0x1U << 4U) /*!< Selects pull-down function */
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#define IOCON_MODE_PULLUP (0x2U << 4U) /*!< Selects pull-up function */
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#define IOCON_DRIVE_LOW (0x0U << 6U) /*!< Enable low drive strength */
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#define IOCON_DRIVE_HIGH (0x1U << 6U) /*!< Enable high drive strength */
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#define IOCON_DRIVE_EXTRA (0x1U << 7U) /*!< Enable extra drive, only valid for PA06/PA11/PA19/PA26/PA27 */
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/**
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* @brief Pull mode
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*/
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typedef enum _iocon_pull_mode
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{
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kIOCON_HighZ = 0U, /*!< High Z */
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kIOCON_PullDown, /*!< Pull down */
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kIOCON_PullUp /*!< Pull up */
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} iocon_pull_mode_t;
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/**
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* @brief Drive strength
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*/
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typedef enum _iocon_drive_strength
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{
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kIOCON_LowDriveStrength = 0U, /*!< Low-drive */
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kIOCON_HighDriveStrength, /*!< High-drive */
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kIOCON_LowDriveWithExtraStrength, /*!< Low-drive with extra */
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kIOCON_HighDriveWithExtraStrength, /*!< High-drive with extra */
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} iocon_drive_strength_t;
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Sets I/O control pin mux
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* @param base The base of SYSCON peripheral on the chip
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* @param port GPIO port to mux (value from 0 ~ 1)
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* @param pin GPIO pin to mux (value from 0 ~ 31)
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* @param modeFunc OR'ed values of type IOCON_*
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* @return Nothing
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*/
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__STATIC_INLINE void IOCON_PinMuxSet(SYSCON_Type *base, uint8_t port, uint8_t pin, uint32_t modeFunc)
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{
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assert(((port == 0U) && (pin <= 31U)) || ((port == 1U) && (pin <= 2U)));
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uint8_t pinMuxIndex = (pin >> 3U);
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uint8_t pinMuxLocation = ((pin & 0x7U) << 2U);
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uint8_t pinPullIndex = (pin >> 4U);
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uint8_t pinPullLocation = ((pin & 0xFU) << 1U);
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if (port == 0U)
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{
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base->PIO_FUNC_CFG[pinMuxIndex] &= ~(0x07U << pinMuxLocation);
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base->PIO_FUNC_CFG[pinMuxIndex] |= (modeFunc & 0x07U) << pinMuxLocation;
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pinPullIndex = (pin >> 4U);
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}
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else if (port == 1U)
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{
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pinPullIndex = 2U;
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if ((pin == 0U) || (pin == 1U))
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{
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base->PIO_CFG_MISC &= ~(1U << pin);
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base->PIO_CFG_MISC |= (modeFunc & 0x01U) << pin;
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}
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else if (pin == 2U)
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{
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base->PIO_CFG_MISC &= ~(1U << 16U);
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base->PIO_CFG_MISC |= (modeFunc & 0x01U) << 16U;
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}
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else
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{
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return;
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}
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}
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else
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{
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return;
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}
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base->PIO_PULL_CFG[pinPullIndex] &= ~(0x03U << pinPullLocation);
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base->PIO_PULL_CFG[pinPullIndex] |= ((modeFunc >> 4U) & 0x03U) << pinPullLocation;
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base->PIO_DRV_CFG[port] &= ~(1U << pin);
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base->PIO_DRV_CFG[port] |= (((modeFunc >> 6U) & 0x01U)) << pin;
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if ((port == 0U) && ((pin == 6U) || (pin == 11U) || (pin == 19U) || (pin == 26U) || (pin == 27U)))
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{
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base->PIO_DRV_CFG[2U] &= ~(1U << pin);
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base->PIO_DRV_CFG[2U] |= (((modeFunc >> 7U) & 0x01U)) << pin;
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}
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}
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/**
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* @brief Set all I/O control pin muxing
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* @param base The base of SYSCON peripheral on the chip
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* @param pinArray Pointer to array of pin mux selections
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* @param arrayLength Number of entries in pinArray
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* @return Nothing
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*/
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__STATIC_INLINE void IOCON_SetPinMuxing(SYSCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength)
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{
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uint32_t i;
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for (i = 0U; i < arrayLength; i++)
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{
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IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc);
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}
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}
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/**
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* @brief Sets I/O control pin function
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* @param base The base of SYSCON peripheral on the chip
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* @param port GPIO port (value from 0 ~ 1)
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* @param pin GPIO pin (value from 0 ~ 31)
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* @param func Pin fucntion (value from 0 ~ 7)
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* @return Nothing
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*/
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__STATIC_INLINE void IOCON_FuncSet(SYSCON_Type *base, uint8_t port, uint8_t pin, uint8_t func)
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{
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assert(((port == 0U) && (pin <= 31U)) || ((port == 1U) && (pin <= 2U)));
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uint8_t index = (pin >> 3);
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uint8_t pinLocation = ((pin & 0x7U) << 2U);
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if (port == 0U)
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{
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base->PIO_FUNC_CFG[index] &= ~(0x07U << pinLocation);
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base->PIO_FUNC_CFG[index] |= (func & 0x07U) << pinLocation;
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}
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else if (port == 1U)
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{
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if ((pin == 0U) || (pin == 1U))
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{
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base->PIO_CFG_MISC &= ~(1U << pin);
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base->PIO_CFG_MISC |= (func & 0x01U) << pin;
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}
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else if (pin == 2U)
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{
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base->PIO_CFG_MISC &= ~(1U << 16U);
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base->PIO_CFG_MISC |= (func & 0x01U) << 16U;
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}
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else
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{
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return;
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}
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}
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else
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{
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return;
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}
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}
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/**
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* @brief Sets I/O control drive capability
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* @param base The base of SYSCON peripheral on the chip
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* @param port GPIO port (value from 0 ~ 1)
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* @param pin GPIO pin (value from 0 ~ 31)
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* @param strength Drive strength (Extra option is only valid for PA06/PA11/PA19/PA26/PA27)
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* - kIOCON_LowDriveStrength = 0U - Low-drive strength is configured.
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* - kIOCON_HighDriveStrength = 1U - High-drive strength is configured
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* - kIOCON_LowDriveWithExtraStrength = 2U - Low-drive with extra strength is configured
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* - kIOCON_HighDriveWithExtraStrength = 3U - High-drive with extra strength is configured
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* @return Nothing
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*/
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__STATIC_INLINE void IOCON_DriveSet(SYSCON_Type *base, uint8_t port, uint8_t pin, uint8_t strength)
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{
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assert(((port == 0U) && (pin <= 31U)) || ((port == 1U) && (pin <= 2U)));
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base->PIO_DRV_CFG[port] &= ~(1U << pin);
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base->PIO_DRV_CFG[port] |= (strength & 0x01U) << pin;
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if ((port == 0U) && ((pin == 6U) || (pin == 11U) || (pin == 19U) || (pin == 26U) || (pin == 27U)))
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{
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base->PIO_DRV_CFG[2U] &= ~(1U << pin);
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base->PIO_DRV_CFG[2U] |= (((strength >> 1U) & 0x01U)) << pin;
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}
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}
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/**
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* @brief Sets I/O control pull configuration
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* @param base The base of SYSCON peripheral on the chip
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* @param port GPIO port (value from 0 ~ 1)
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* @param pin GPIO pin (value from 0 ~ 31)
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* @param pullMode Pull mode
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* - kIOCON_HighZ = 0U - High Z is configured.
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* - kIOCON_PullDown = 1U - Pull-down is configured
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* - kIOCON_PullUp = 2U - Pull-up is configured
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* @return Nothing
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*/
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__STATIC_INLINE void IOCON_PullSet(SYSCON_Type *base, uint8_t port, uint8_t pin, uint8_t pullMode)
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{
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assert(((port == 0U) && (pin <= 31U)) || ((port == 1U) && (pin <= 2U)));
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uint8_t index = (port == 1U) ? 2U : (pin >> 4U);
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uint8_t pinLocation = ((pin & 0xFU) << 1U);
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base->PIO_PULL_CFG[index] &= ~(0x03U << pinLocation);
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base->PIO_PULL_CFG[index] |= (uint32_t)pullMode << pinLocation;
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}
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/* @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _FSL_IOCON_H_ */
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