mirror of
https://github.com/RIOT-OS/RIOT.git
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263 lines
10 KiB
C
263 lines
10 KiB
C
/*
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* Copyright (C) 2016 Leon George
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc26xx_cc13xx_definitions
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* @{
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*
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* @file
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* @brief CC26xx/CC13xx VIMS register definitions
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*/
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#ifndef CC26XX_CC13XX_VIMS_H
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#define CC26XX_CC13XX_VIMS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief FLASH registers
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*/
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typedef struct {
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reg32_t __reserved1[7]; /**< Reserved */
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reg32_t STAT; /**< FMC and efuse status */
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reg32_t __reserved2; /**< Reserved */
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reg32_t CFG; /**< Config */
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reg32_t SYSCODE_START; /**< syscode start address offset config */
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reg32_t FLASH_SIZE; /**< flash size config */
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reg32_t __reserved3[3]; /**< Reserved */
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reg32_t FWLOCK; /**< firmware lock */
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reg32_t FWFLAG; /**< firmware flags */
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reg32_t __reserved4[0x3EF]; /**< Reserved */
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reg32_t EFUSE; /**< efuse instruction */
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reg32_t EFUSEADDR; /**< efuse address */
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reg32_t DATAUPPER; /**< efuse data - upper */
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reg32_t DATALOWER; /**< efuse data - lower */
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reg32_t EFUSECFG; /**< OCP sysconf */
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reg32_t EFUSESTAT; /**< system status */
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reg32_t ACC; /**< arbitrary instruction count */
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reg32_t BOUNDARY; /**< boundary test register to drive I/O */
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reg32_t EFUSEFLAG; /**< efuse key loaded flag */
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reg32_t EFUSEKEY; /**< efuse key */
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reg32_t EFUSERELEASE; /**< efuese release */
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reg32_t EFUSEPINS; /**< efuse pins */
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reg32_t EFUSECRA; /**< efuse column repair address */
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reg32_t EFUSEREAD; /**< efuse read */
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reg32_t EFUSEPROGRAM; /**< efuse program */
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reg32_t EFUSEERROR; /**< efuse error */
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reg32_t SINGLEBIT; /**< single-bit error status */
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reg32_t TWOBIT; /**< two-bit error status */
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reg32_t SELFTESTCYC; /**< self-test cycles */
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reg32_t SELFTESTSIGN; /**< self-test signature */
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reg32_t __reserved5[0x3ec]; /**< Reserved */
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reg32_t FRDCTL; /**< FMC read control */
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reg32_t FSPRD; /**< FMC read margin control */
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reg32_t FEDACCTL1; /**< FMC error correction control 1 */
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reg32_t __reserved6[4]; /**< Reserved */
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reg32_t FEDACSTAT; /**< FMC error status */
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reg32_t __reserved7[4]; /**< Reserved */
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reg32_t FBPROT; /**< FMC bank protection */
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reg32_t FBSE; /**< FMC sector enable */
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reg32_t FBBUSY; /**< FMC bank busy */
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reg32_t FBAC; /**< FMC bank access control */
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reg32_t FBFALLBACK; /**< FMC bank fallback power */
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reg32_t FBPRDY; /**< FMC bank/pump ready */
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reg32_t FPAC1; /**< FMC pump access control 1 */
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reg32_t FPAC2; /**< FMC pump access control 2 */
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reg32_t FMAC; /**< FMC module access control */
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reg32_t FMSTAT; /**< FMC module status */
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reg32_t __reserved8[3]; /**< Reserved */
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reg32_t FLOCK; /**< FMC flash lock */
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reg32_t __reserved9[6]; /**< Reserved */
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reg32_t FVREADCT; /**< FMC VREADCT trim */
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reg32_t FVHVCT1; /**< FMC VHVCT1 trim */
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reg32_t FVHVCT2; /**< FMC VHVCT2 trim */
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reg32_t FVHVCT3; /**< FMC VHVCT3 trim */
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reg32_t FVNVCT; /**< FMC VNVCT trim */
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reg32_t FVSLP; /**< FMC VSL_P trim */
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reg32_t FVWLCT; /**< FMC VWLCT trim */
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reg32_t FEFUSECTL; /**< FMC efuse control */
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reg32_t FEFUSESTAT; /**< FMC efuse status */
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reg32_t FEFUSEDATA; /**< FMC efuse data */
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reg32_t FSEQPMP; /**< FMC sequential pump information */
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reg32_t __reserved10[21]; /**< Reserved */
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reg32_t FBSTROBES; /**< FMC bank signal strobe */
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reg32_t FPSTROBES; /**< FMC pump signal strobe */
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reg32_t FBMODE; /**< FMC bank and pump mode */
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reg32_t FTCR; /**< FMC test command control */
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reg32_t FADDR; /**< FMC bank address */
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reg32_t __reserved11[2]; /**< Reserved */
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reg32_t FTCTL; /**< FMC test control */
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reg32_t FWPWRITE0; /**< FMC flash wide programming write data 0 */
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reg32_t FWPWRITE1; /**< FMC flash wide programming write data 1 */
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reg32_t FWPWRITE2; /**< FMC flash wide programming write data 2 */
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reg32_t FWPWRITE3; /**< FMC flash wide programming write data 3 */
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reg32_t FWPWRITE4; /**< FMC flash wide programming write data 4 */
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reg32_t FWPWRITE5; /**< FMC flash wide programming write data 5 */
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reg32_t FWPWRITE6; /**< FMC flash wide programming write data 6 */
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reg32_t FWPWRITE7; /**< FMC flash wide programming write data 7 */
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reg32_t FWPWRITE_ECC; /**< FMC flash wide programming ECC */
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reg32_t FSWSTAT; /**< FMC software interface status */
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reg32_t __reserved12[0x2E]; /**< Reserved */
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reg32_t FSM_GLBCTL; /**< FMC FSM global control */
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reg32_t FSM_STATE; /**< FMC FSM state status */
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reg32_t FSM_STAT; /**< FMC FSM status */
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reg32_t FSM_CMD; /**< FMC FSM command */
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reg32_t FSM_PE_OSU; /**< FMC FSM program/erase operation setup */
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reg32_t FSM_VSTAT; /**< FMC FSM voltage status setup */
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reg32_t FSM_PE_VSU; /**< FMC FSM program/erase verify setup */
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reg32_t FSM_CMP_VSU; /**< FMC FSM compare verify setup */
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reg32_t FSM_EX_VAL; /**< FMC FSM EXECUTEZ to valid data */
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reg32_t FSM_RD_H; /**< FMC FSM read mode hold */
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reg32_t FSM_P_OH; /**< FMC FSM program hold */
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reg32_t FSM_ERA_OH; /**< FMC FSM erase operation hold */
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reg32_t FSM_SAV_PPUL; /**< FMC FSM saved program pulses */
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reg32_t FSM_PE_VH; /**< FMC FSM program/erase verify hold */
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reg32_t __reserved13[2]; /**< Reserved */
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reg32_t FSM_PRG_PW; /**< FMC FSM program pulse width */
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reg32_t FSM_ERA_PW; /**< FMC FSM erase pulse width */
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reg32_t __reserved14[3]; /**< Reserved */
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reg32_t FSM_SAV_ERA_PUL; /**< FMC FSM saved erased pulses */
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reg32_t FSM_TIMER; /**< FMC FSM timer */
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reg32_t FSM_MODE; /**< FMC FSM MODE */
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reg32_t FSM_PGM; /**< FMC FSM program bits */
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reg32_t FSM_ERA; /**< FMC FSM erase bits */
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reg32_t FSM_PRG_PUL; /**< FMC FSM maximum programming pulses */
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reg32_t FSM_ERA_PUL; /**< FMC FSM maximum erase pulses */
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reg32_t FSM_STEP_SIZE; /**< FMC FSM EC step size */
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reg32_t FSM_PUL_CNTR; /**< FMC FSM pulse counter */
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reg32_t FSM_EC_STEP_HEIGHT; /**< FMC FSM EC step height */
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reg32_t FSM_ST_MACHINE; /**< FMC FSM ST MACHINE */
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reg32_t FSM_FLES; /**< FMC FSM FLES memory control bits */
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reg32_t __reserved15; /**< Reserved */
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reg32_t FSM_WR_ENA; /**< FMC FSM register write enable */
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reg32_t FSM_ACC_PP; /**< FMC FSM accumulate program pulses */
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reg32_t FSM_ACC_EP; /**< FMC FSM accumulate erase pulses */
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reg32_t __reserved16[3]; /**< Reserved */
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reg32_t FSM_ADDR; /**< FMC FSM address */
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reg32_t FSM_SECTOR; /**< FMC sectors erased */
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reg32_t FMC_REV_ID; /**< FMC revision identification */
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reg32_t FSM_ERR_ADDR; /**< FSM error address */
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reg32_t FSM_PGM_MAXPUL; /**< FMC FSM maximum program pulse */
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reg32_t FSM_EXECUTE; /**< FMC FSM command execute */
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reg32_t __reserved17[2]; /**< Reserved */
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reg32_t FSM_SECTOR1; /**< FMC FSM sector erased 1 */
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reg32_t FSM_SECTOR2; /**< FMC FSM sector erased 2 */
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reg32_t __reserved18[6]; /**< Reserved */
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reg32_t FSM_BSLE0; /**< FMC FSM bank sector lock erase 0 */
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reg32_t FSM_BSLE1; /**< FMC FSM bank sector lock erase 1 */
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reg32_t __reserved19[2]; /**< Reserved */
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reg32_t FSM_BSLP0; /**< FMC FSM bank sector lock program 0 */
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reg32_t FSM_BSLP1; /**< FMC FSM bank sector lock program 1 */
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reg32_t FSM_PGM_128; /**< Enable 128-bit programming. CC26x2_CC13x2 only */
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reg32_t __reserved20[0x41]; /**< Reserved */
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reg32_t FCFG_BANK; /**< FMC flash configuration bank */
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reg32_t FCFG_WRAPPER; /**< FMC flash wrapper configuration */
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reg32_t FCFG_BNK_TYPE; /**< FMC flash bank type */
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reg32_t __reserved21; /**< Reserved */
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reg32_t FCFG_B0_START; /**< FMC flash bank 0 starting address */
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reg32_t FCFG_B1_START; /**< FMC flash bank 1 starting address */
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reg32_t FCFG_B2_START; /**< FMC flash bank 2 starting address */
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reg32_t FCFG_B3_START; /**< FMC flash bank 3 starting address */
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reg32_t FCFG_B4_START; /**< FMC flash bank 4 starting address */
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reg32_t FCFG_B5_START; /**< FMC flash bank 5 starting address */
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reg32_t FCFG_B6_START; /**< FMC flash bank 6 starting address */
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reg32_t FCFG_B7_START; /**< FMC flash bank 7 starting address */
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reg32_t FCFG_B0_SSIZE0; /**< FMC flash bank 0 sector size */
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} flash_regs_t;
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/**
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* @brief FLASH register values
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* @{
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*/
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#define FLASH_CFG_DIS_STANDBY 0x00000002
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#define FLASH_CFG_DIS_EFUSECLK 0x00000020
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#define FLASH_FPAC1_PSLEEPTDIS_m 0x0FFF0000
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#define FLASH_FPAC1_PSLEEPTDIS_s 16
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/** @} */
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief FLASH base address
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*/
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#define FLASH_BASEADDR (PERIPH_BASE + 0x30000)
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/** @} */
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/**
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* @brief FLASH register bank
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*/
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#define FLASH ((flash_regs_t *) (FLASH_BASEADDR))
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/**
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* @brief VIMS registers
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*/
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typedef struct {
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reg32_t STAT; /**< Status */
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reg32_t CTL; /**< Control */
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} vims_regs_t;
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief VIMS base address
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*/
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#define VIMS_BASE (PERIPH_BASE + 0x34000)
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/** @} */
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/**
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* @brief VIMS register bank
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*/
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#define VIMS ((vims_regs_t *) (VIMS_BASE))
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/**
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* @brief VIMS register values
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* @{
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*/
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#define VIMS_CTL_STATS_CLR 0x80000000
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#define VIMS_CTL_STATS_CLR_m 0x80000000
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#define VIMS_CTL_STATS_EN 0x40000000
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#define VIMS_CTL_STATS_EN_m 0x40000000
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#define VIMS_CTL_DYN_CG_EN 0x20000000
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#define VIMS_CTL_DYN_CG_EN_m 0x20000000
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#define VIMS_CTL_IDCODE_LB_DIS 0x00000020
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#define VIMS_CTL_IDCODE_LB_DIS_m 0x00000020
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#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010
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#define VIMS_CTL_SYSBUS_LB_DIS_m 0x00000010
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#define VIMS_CTL_ARB_CFG 0x00000008
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#define VIMS_CTL_ARB_CFG_m 0x00000008
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#define VIMS_CTL_PREF_EN 0x00000004
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#define VIMS_CTL_PREF_EN_m 0x00000004
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#define VIMS_CTL_MODE_GPRAM 0x00000000
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#define VIMS_CTL_MODE_CACHE 0x00000001
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#define VIMS_CTL_MODE_SPLIT 0x00000002
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#define VIMS_CTL_MODE_OFF 0x00000003
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#define VIMS_CTL_MODE_m 0x00000003
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#define VIMS_STAT_MODE_CHANGING 0x00000008
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CC26XX_CC13XX_VIMS_H */
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/** @} */
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