mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
129 lines
3.1 KiB
C
129 lines
3.1 KiB
C
/*
|
|
* Copyright (C) 2017 Freie Universität Berlin
|
|
* 2017 Inria
|
|
*
|
|
* This file is subject to the terms and conditions of the GNU Lesser
|
|
* General Public License v2.1. See the file LICENSE in the top level
|
|
* directory for more details.
|
|
*/
|
|
|
|
/**
|
|
* @ingroup boards_nucleo-l031k6
|
|
* @{
|
|
*
|
|
* @file
|
|
* @brief Peripheral MCU configuration for the nucleo-l031k6 board
|
|
*
|
|
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
|
* @author Alexandre Aabdie <alexandre.abadie@inria.fr>
|
|
*/
|
|
|
|
#ifndef PERIPH_CONF_H
|
|
#define PERIPH_CONF_H
|
|
|
|
/* Add specific clock configuration (HSE, LSE) for this board here */
|
|
#ifndef CONFIG_BOARD_HAS_LSE
|
|
#define CONFIG_BOARD_HAS_LSE 1
|
|
#endif
|
|
|
|
#include "periph_cpu.h"
|
|
#include "clk_conf.h"
|
|
#include "cfg_i2c1_pb6_pb7.h"
|
|
#include "cfg_rtt_default.h"
|
|
#include "cfg_timer_tim2.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
/**
|
|
* @name UART configuration
|
|
* @{
|
|
*/
|
|
static const uart_conf_t uart_config[] = {
|
|
{
|
|
.dev = USART2,
|
|
.rcc_mask = RCC_APB1ENR_USART2EN,
|
|
.rx_pin = GPIO_PIN(PORT_A, 15),
|
|
.tx_pin = GPIO_PIN(PORT_A, 2),
|
|
.rx_af = GPIO_AF4,
|
|
.tx_af = GPIO_AF4,
|
|
.bus = APB1,
|
|
.irqn = USART2_IRQn,
|
|
.type = STM32_USART,
|
|
.clk_src = 0, /* Use APB clock */
|
|
}
|
|
};
|
|
|
|
#define UART_0_ISR (isr_usart2)
|
|
|
|
#define UART_NUMOF ARRAY_SIZE(uart_config)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name PWM configuration
|
|
* @{
|
|
*/
|
|
static const pwm_conf_t pwm_config[] = {
|
|
{
|
|
.dev = TIM21,
|
|
.rcc_mask = RCC_APB2ENR_TIM21EN,
|
|
.chan = { { .pin = GPIO_PIN(PORT_B, 6) /* D5 */, .cc_chan = 0 },
|
|
{ .pin = GPIO_UNDEF, .cc_chan = 0 },
|
|
{ .pin = GPIO_UNDEF, .cc_chan = 0 },
|
|
{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
|
|
.af = GPIO_AF5,
|
|
.bus = APB2
|
|
}
|
|
};
|
|
|
|
#define PWM_NUMOF ARRAY_SIZE(pwm_config)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name SPI configuration
|
|
* @{
|
|
*/
|
|
static const spi_conf_t spi_config[] = {
|
|
{
|
|
.dev = SPI1,
|
|
.mosi_pin = GPIO_PIN(PORT_B, 5),
|
|
.miso_pin = GPIO_PIN(PORT_B, 4),
|
|
.sclk_pin = GPIO_PIN(PORT_B, 3),
|
|
.cs_pin = SPI_CS_UNDEF,
|
|
.mosi_af = GPIO_AF0,
|
|
.miso_af = GPIO_AF0,
|
|
.sclk_af = GPIO_AF0,
|
|
.cs_af = GPIO_AF0,
|
|
.rccmask = RCC_APB2ENR_SPI1EN,
|
|
.apbbus = APB2
|
|
}
|
|
};
|
|
|
|
#define SPI_NUMOF ARRAY_SIZE(spi_config)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name ADC configuration
|
|
* @{
|
|
*/
|
|
static const adc_conf_t adc_config[] = {
|
|
{ GPIO_PIN(PORT_A, 0), 0 }, /* Pin A0 */
|
|
{ GPIO_PIN(PORT_A, 1), 1 }, /* Pin A1 */
|
|
{ GPIO_PIN(PORT_A, 3), 3 }, /* Pin A2 */
|
|
{ GPIO_PIN(PORT_A, 4), 4 }, /* Pin A3 */
|
|
{ GPIO_PIN(PORT_A, 5), 5 }, /* Pin A4 */
|
|
{ GPIO_PIN(PORT_A, 6), 6 }, /* Pin A5 */
|
|
{ GPIO_PIN(PORT_A, 7), 7 }, /* Pin A6 */
|
|
};
|
|
|
|
#define ADC_NUMOF ARRAY_SIZE(adc_config)
|
|
/** @} */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* PERIPH_CONF_H */
|
|
/** @} */
|