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150 lines
12 KiB
C
150 lines
12 KiB
C
/**************************************************************************//**
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* @file
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* @brief EFR32ZG23 MAILBOX register and bit field definitions
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******************************************************************************
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* # License
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* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
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******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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*****************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef EFR32ZG23_MAILBOX_H
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#define EFR32ZG23_MAILBOX_H
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#define MAILBOX_HAS_SET_CLEAR
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/**************************************************************************//**
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* @addtogroup Parts
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* @{
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******************************************************************************/
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/**************************************************************************//**
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* @defgroup EFR32ZG23_MAILBOX MAILBOX
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* @{
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* @brief EFR32ZG23 MAILBOX Register Declaration.
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*****************************************************************************/
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/** MAILBOX MSGPTRS Register Group Declaration. */
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typedef struct {
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__IOM uint32_t MSGPTR; /**< Message Pointer */
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} MAILBOX_MSGPTRS_TypeDef;
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/** MAILBOX Register Declaration. */
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typedef struct {
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MAILBOX_MSGPTRS_TypeDef MSGPTRS[4U]; /**< Message Pointers */
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uint32_t RESERVED0[12U]; /**< Reserved for future use */
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__IOM uint32_t IF; /**< Interrupt Flag register */
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__IOM uint32_t IEN; /**< Interrupt Enable register */
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uint32_t RESERVED1[1006U]; /**< Reserved for future use */
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MAILBOX_MSGPTRS_TypeDef MSGPTRS_SET[4U]; /**< Message Pointers */
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uint32_t RESERVED2[12U]; /**< Reserved for future use */
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__IOM uint32_t IF_SET; /**< Interrupt Flag register */
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__IOM uint32_t IEN_SET; /**< Interrupt Enable register */
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uint32_t RESERVED3[1006U]; /**< Reserved for future use */
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MAILBOX_MSGPTRS_TypeDef MSGPTRS_CLR[4U]; /**< Message Pointers */
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uint32_t RESERVED4[12U]; /**< Reserved for future use */
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__IOM uint32_t IF_CLR; /**< Interrupt Flag register */
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__IOM uint32_t IEN_CLR; /**< Interrupt Enable register */
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uint32_t RESERVED5[1006U]; /**< Reserved for future use */
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MAILBOX_MSGPTRS_TypeDef MSGPTRS_TGL[4U]; /**< Message Pointers */
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uint32_t RESERVED6[12U]; /**< Reserved for future use */
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__IOM uint32_t IF_TGL; /**< Interrupt Flag register */
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__IOM uint32_t IEN_TGL; /**< Interrupt Enable register */
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} MAILBOX_TypeDef;
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/** @} End of group EFR32ZG23_MAILBOX */
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/**************************************************************************//**
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* @addtogroup EFR32ZG23_MAILBOX
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* @{
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* @defgroup EFR32ZG23_MAILBOX_BitFields MAILBOX Bit Fields
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* @{
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*****************************************************************************/
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/* Bit fields for MAILBOX MSGPTR */
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#define _MAILBOX_MSGPTR_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_MSGPTR */
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#define _MAILBOX_MSGPTR_MASK 0xFFFFFFFFUL /**< Mask for MAILBOX_MSGPTR */
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#define _MAILBOX_MSGPTR_PTR_SHIFT 0 /**< Shift value for MAILBOX_PTR */
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#define _MAILBOX_MSGPTR_PTR_MASK 0xFFFFFFFFUL /**< Bit mask for MAILBOX_PTR */
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#define _MAILBOX_MSGPTR_PTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_MSGPTR */
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#define MAILBOX_MSGPTR_PTR_DEFAULT (_MAILBOX_MSGPTR_PTR_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_MSGPTR */
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/* Bit fields for MAILBOX IF */
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#define _MAILBOX_IF_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IF */
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#define _MAILBOX_IF_MASK 0x0000000FUL /**< Mask for MAILBOX_IF */
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#define MAILBOX_IF_MBOXIF0 (0x1UL << 0) /**< Mailbox Interupt Flag */
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#define _MAILBOX_IF_MBOXIF0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIF0 */
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#define _MAILBOX_IF_MBOXIF0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIF0 */
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#define _MAILBOX_IF_MBOXIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */
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#define MAILBOX_IF_MBOXIF0_DEFAULT (_MAILBOX_IF_MBOXIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IF */
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#define MAILBOX_IF_MBOXIF1 (0x1UL << 1) /**< Mailbox Interupt Flag */
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#define _MAILBOX_IF_MBOXIF1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIF1 */
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#define _MAILBOX_IF_MBOXIF1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIF1 */
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#define _MAILBOX_IF_MBOXIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */
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#define MAILBOX_IF_MBOXIF1_DEFAULT (_MAILBOX_IF_MBOXIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IF */
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#define MAILBOX_IF_MBOXIF2 (0x1UL << 2) /**< Mailbox Interupt Flag */
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#define _MAILBOX_IF_MBOXIF2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIF2 */
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#define _MAILBOX_IF_MBOXIF2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIF2 */
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#define _MAILBOX_IF_MBOXIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */
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#define MAILBOX_IF_MBOXIF2_DEFAULT (_MAILBOX_IF_MBOXIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IF */
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#define MAILBOX_IF_MBOXIF3 (0x1UL << 3) /**< Mailbox Interupt Flag */
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#define _MAILBOX_IF_MBOXIF3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIF3 */
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#define _MAILBOX_IF_MBOXIF3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIF3 */
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#define _MAILBOX_IF_MBOXIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */
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#define MAILBOX_IF_MBOXIF3_DEFAULT (_MAILBOX_IF_MBOXIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IF */
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/* Bit fields for MAILBOX IEN */
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#define _MAILBOX_IEN_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IEN */
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#define _MAILBOX_IEN_MASK 0x0000000FUL /**< Mask for MAILBOX_IEN */
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#define MAILBOX_IEN_MBOXIEN0 (0x1UL << 0) /**< Mailbox Interrupt Enable */
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#define _MAILBOX_IEN_MBOXIEN0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIEN0 */
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#define _MAILBOX_IEN_MBOXIEN0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIEN0 */
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#define _MAILBOX_IEN_MBOXIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */
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#define MAILBOX_IEN_MBOXIEN0_DEFAULT (_MAILBOX_IEN_MBOXIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IEN */
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#define MAILBOX_IEN_MBOXIEN1 (0x1UL << 1) /**< Mailbox Interrupt Enable */
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#define _MAILBOX_IEN_MBOXIEN1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIEN1 */
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#define _MAILBOX_IEN_MBOXIEN1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIEN1 */
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#define _MAILBOX_IEN_MBOXIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */
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#define MAILBOX_IEN_MBOXIEN1_DEFAULT (_MAILBOX_IEN_MBOXIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IEN */
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#define MAILBOX_IEN_MBOXIEN2 (0x1UL << 2) /**< Mailbox Interrupt Enable */
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#define _MAILBOX_IEN_MBOXIEN2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIEN2 */
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#define _MAILBOX_IEN_MBOXIEN2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIEN2 */
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#define _MAILBOX_IEN_MBOXIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */
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#define MAILBOX_IEN_MBOXIEN2_DEFAULT (_MAILBOX_IEN_MBOXIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IEN */
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#define MAILBOX_IEN_MBOXIEN3 (0x1UL << 3) /**< Mailbox Interrupt Enable */
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#define _MAILBOX_IEN_MBOXIEN3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIEN3 */
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#define _MAILBOX_IEN_MBOXIEN3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIEN3 */
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#define _MAILBOX_IEN_MBOXIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */
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#define MAILBOX_IEN_MBOXIEN3_DEFAULT (_MAILBOX_IEN_MBOXIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IEN */
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/** @} End of group EFR32ZG23_MAILBOX_BitFields */
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/** @} End of group EFR32ZG23_MAILBOX */
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/** @} End of group Parts */
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#endif /* EFR32ZG23_MAILBOX_H */
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#ifdef __cplusplus
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}
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#endif
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