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cpu/efm32: add efr32zg23 family

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Generated with the EFM2RIOT tool: https://github.com/basilfx/EFM2RIOT
This commit is contained in:
Jue 2022-10-17 22:52:06 +02:00
parent 2ce1df5cd6
commit ee2f5e981c
67 changed files with 45433 additions and 0 deletions
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3
cpu/efm32/Makefile
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@ -34,6 +34,9 @@ endif
ifneq (,$(filter cpu_efr32mg12p,$(USEMODULE)))
DIRS += families/efr32mg12p
endif
ifneq (,$(filter cpu_efr32zg23,$(USEMODULE)))
DIRS += families/efr32zg23
endif
ifneq (,$(filter cpu_ezr32wg,$(USEMODULE)))
DIRS += families/ezr32wg
endif

78
cpu/efm32/families/efr32zg23/Kconfig Normal file
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@ -0,0 +1,78 @@
# Copyright (c) 2020 HAW Hamburg
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
config CPU_FAM_EFR32ZG23
bool
select CPU_CORE_CORTEX_M33
select CPU_COMMON_EFM32
select CPU_EFM32_SERIES2
select HAS_PERIPH_HWRNG
select HAS_CORTEXM_MPU
config MODULE_CPU_EFR32ZG23
bool
depends on CPU_FAM_EFR32ZG23
depends on TEST_KCONFIG
default y
help
EFR32ZG23 family-specific code.
## CPU Models
config CPU_MODEL_EFR32ZG23B020F512IM40
bool
select CPU_FAM_EFR32ZG23
config CPU_MODEL_EFR32ZG23B020F512IM48
bool
select CPU_FAM_EFR32ZG23
config CPU_MODEL_EFR32ZG23A010F512GM48
bool
select CPU_FAM_EFR32ZG23
config CPU_MODEL_EFR32ZG23A010F512GM40
bool
select CPU_FAM_EFR32ZG23
config CPU_MODEL_EFR32ZG23A020F512GM48
bool
select CPU_FAM_EFR32ZG23
config CPU_MODEL_EFR32ZG23B010F512IM40
bool
select CPU_FAM_EFR32ZG23
config CPU_MODEL_EFR32ZG23A020F512GM40
bool
select CPU_FAM_EFR32ZG23
config CPU_MODEL_EFR32ZG23B011F512IM40
bool
select CPU_FAM_EFR32ZG23
config CPU_MODEL_EFR32ZG23B010F512IM48
bool
select CPU_FAM_EFR32ZG23
config CPU_MODEL_EFR32ZG23B021F512IM40
bool
select CPU_FAM_EFR32ZG23
## Common CPU symbols
config CPU_FAM
default "efr32zg23" if CPU_FAM_EFR32ZG23
config CPU_MODEL
default "efr32zg23b020f512im40" if CPU_MODEL_EFR32ZG23B020F512IM40
default "efr32zg23b020f512im48" if CPU_MODEL_EFR32ZG23B020F512IM48
default "efr32zg23a010f512gm48" if CPU_MODEL_EFR32ZG23A010F512GM48
default "efr32zg23a010f512gm40" if CPU_MODEL_EFR32ZG23A010F512GM40
default "efr32zg23a020f512gm48" if CPU_MODEL_EFR32ZG23A020F512GM48
default "efr32zg23b010f512im40" if CPU_MODEL_EFR32ZG23B010F512IM40
default "efr32zg23a020f512gm40" if CPU_MODEL_EFR32ZG23A020F512GM40
default "efr32zg23b011f512im40" if CPU_MODEL_EFR32ZG23B011F512IM40
default "efr32zg23b010f512im48" if CPU_MODEL_EFR32ZG23B010F512IM48
default "efr32zg23b021f512im40" if CPU_MODEL_EFR32ZG23B021F512IM40

6
cpu/efm32/families/efr32zg23/Makefile Normal file
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@ -0,0 +1,6 @@
MODULE = cpu_efr32zg23
# (file triggers compiler bug. see #5775)
SRC_NOLTO += vectors.c
include $(RIOTBASE)/Makefile.base

9
cpu/efm32/families/efr32zg23/Makefile.include Normal file
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@ -0,0 +1,9 @@
# Find the header file that should exist if the CPU is supported. Only headers
# for supported boards are included, but to support another CPU, it should be
# as easy as adding the header file only.
EFM32_HEADER = $(wildcard $(RIOTCPU)/efm32/families/efr32zg23/include/vendor/$(CPU_MODEL).h)
# include vendor device headers
INCLUDES += -I$(RIOTCPU)/efm32/families/efr32zg23/include/vendor
CFLAGS += -mcmse

15
cpu/efm32/families/efr32zg23/efm32-info.mk Normal file
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@ -0,0 +1,15 @@
# This file is automatically generated, and should not be changed. There is
# probably little reason to edit this file anyway, since it should already
# contain all information for the EFR32ZG23 family of CPUs.
# Series - Architecture - Flash base - Flash size - SRAM base - SRAM size - Crypto? - TRNG? - Radio?
EFM32_INFO_efr32zg23b020f512im40 = 2 cortex-m33 0x08000000 0x00080000 0x20000000 0x00010000 1 1 1
EFM32_INFO_efr32zg23b020f512im48 = 2 cortex-m33 0x08000000 0x00080000 0x20000000 0x00010000 1 1 1
EFM32_INFO_efr32zg23a010f512gm48 = 2 cortex-m33 0x08000000 0x00080000 0x20000000 0x00010000 1 1 1
EFM32_INFO_efr32zg23a010f512gm40 = 2 cortex-m33 0x08000000 0x00080000 0x20000000 0x00010000 1 1 1
EFM32_INFO_efr32zg23a020f512gm48 = 2 cortex-m33 0x08000000 0x00080000 0x20000000 0x00010000 1 1 1
EFM32_INFO_efr32zg23b010f512im40 = 2 cortex-m33 0x08000000 0x00080000 0x20000000 0x00010000 1 1 1
EFM32_INFO_efr32zg23a020f512gm40 = 2 cortex-m33 0x08000000 0x00080000 0x20000000 0x00010000 1 1 1
EFM32_INFO_efr32zg23b011f512im40 = 2 cortex-m33 0x08000000 0x00080000 0x20000000 0x00010000 1 1 1
EFM32_INFO_efr32zg23b010f512im48 = 2 cortex-m33 0x08000000 0x00080000 0x20000000 0x00010000 1 1 1
EFM32_INFO_efr32zg23b021f512im40 = 2 cortex-m33 0x08000000 0x00080000 0x20000000 0x00010000 1 1 1

663
cpu/efm32/families/efr32zg23/include/vendor/efr32zg23_acmp.h vendored Normal file
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@ -0,0 +1,663 @@
/**************************************************************************//**
* @file
* @brief EFR32ZG23 ACMP register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_ACMP_H
#define EFR32ZG23_ACMP_H
#define ACMP_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_ACMP ACMP
* @{
* @brief EFR32ZG23 ACMP Register Declaration.
*****************************************************************************/
/** ACMP Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP version ID */
__IOM uint32_t EN; /**< ACMP enable */
__IOM uint32_t SWRST; /**< Software reset */
__IOM uint32_t CFG; /**< Configuration register */
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t INPUTCTRL; /**< Input Control Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IM uint32_t SYNCBUSY; /**< Syncbusy */
uint32_t RESERVED0[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP version ID */
__IOM uint32_t EN_SET; /**< ACMP enable */
__IOM uint32_t SWRST_SET; /**< Software reset */
__IOM uint32_t CFG_SET; /**< Configuration register */
__IOM uint32_t CTRL_SET; /**< Control Register */
__IOM uint32_t INPUTCTRL_SET; /**< Input Control Register */
__IM uint32_t STATUS_SET; /**< Status Register */
__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
__IM uint32_t SYNCBUSY_SET; /**< Syncbusy */
uint32_t RESERVED1[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP version ID */
__IOM uint32_t EN_CLR; /**< ACMP enable */
__IOM uint32_t SWRST_CLR; /**< Software reset */
__IOM uint32_t CFG_CLR; /**< Configuration register */
__IOM uint32_t CTRL_CLR; /**< Control Register */
__IOM uint32_t INPUTCTRL_CLR; /**< Input Control Register */
__IM uint32_t STATUS_CLR; /**< Status Register */
__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
__IM uint32_t SYNCBUSY_CLR; /**< Syncbusy */
uint32_t RESERVED2[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP version ID */
__IOM uint32_t EN_TGL; /**< ACMP enable */
__IOM uint32_t SWRST_TGL; /**< Software reset */
__IOM uint32_t CFG_TGL; /**< Configuration register */
__IOM uint32_t CTRL_TGL; /**< Control Register */
__IOM uint32_t INPUTCTRL_TGL; /**< Input Control Register */
__IM uint32_t STATUS_TGL; /**< Status Register */
__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
__IM uint32_t SYNCBUSY_TGL; /**< Syncbusy */
} ACMP_TypeDef;
/** @} End of group EFR32ZG23_ACMP */
/**************************************************************************//**
* @addtogroup EFR32ZG23_ACMP
* @{
* @defgroup EFR32ZG23_ACMP_BitFields ACMP Bit Fields
* @{
*****************************************************************************/
/* Bit fields for ACMP IPVERSION */
#define _ACMP_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ACMP_IPVERSION */
#define _ACMP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ACMP_IPVERSION */
#define _ACMP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ACMP_IPVERSION */
#define _ACMP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ACMP_IPVERSION */
#define _ACMP_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_IPVERSION */
#define ACMP_IPVERSION_IPVERSION_DEFAULT (_ACMP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IPVERSION */
/* Bit fields for ACMP EN */
#define _ACMP_EN_RESETVALUE 0x00000000UL /**< Default value for ACMP_EN */
#define _ACMP_EN_MASK 0x00000003UL /**< Mask for ACMP_EN */
#define ACMP_EN_EN (0x1UL << 0) /**< Module enable */
#define _ACMP_EN_EN_SHIFT 0 /**< Shift value for ACMP_EN */
#define _ACMP_EN_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */
#define _ACMP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */
#define ACMP_EN_EN_DEFAULT (_ACMP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EN */
#define ACMP_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
#define _ACMP_EN_DISABLING_SHIFT 1 /**< Shift value for ACMP_DISABLING */
#define _ACMP_EN_DISABLING_MASK 0x2UL /**< Bit mask for ACMP_DISABLING */
#define _ACMP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */
#define ACMP_EN_DISABLING_DEFAULT (_ACMP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_EN */
/* Bit fields for ACMP SWRST */
#define _ACMP_SWRST_RESETVALUE 0x00000000UL /**< Default value for ACMP_SWRST */
#define _ACMP_SWRST_MASK 0x00000003UL /**< Mask for ACMP_SWRST */
#define ACMP_SWRST_SWRST (0x1UL << 0) /**< Software reset */
#define _ACMP_SWRST_SWRST_SHIFT 0 /**< Shift value for ACMP_SWRST */
#define _ACMP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ACMP_SWRST */
#define _ACMP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */
#define ACMP_SWRST_SWRST_DEFAULT (_ACMP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SWRST */
#define ACMP_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */
#define _ACMP_SWRST_RESETTING_SHIFT 1 /**< Shift value for ACMP_RESETTING */
#define _ACMP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ACMP_RESETTING */
#define _ACMP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */
#define ACMP_SWRST_RESETTING_DEFAULT (_ACMP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_SWRST */
/* Bit fields for ACMP CFG */
#define _ACMP_CFG_RESETVALUE 0x00000004UL /**< Default value for ACMP_CFG */
#define _ACMP_CFG_MASK 0x00030F07UL /**< Mask for ACMP_CFG */
#define _ACMP_CFG_BIAS_SHIFT 0 /**< Shift value for ACMP_BIAS */
#define _ACMP_CFG_BIAS_MASK 0x7UL /**< Bit mask for ACMP_BIAS */
#define _ACMP_CFG_BIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_CFG */
#define ACMP_CFG_BIAS_DEFAULT (_ACMP_CFG_BIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CFG */
#define _ACMP_CFG_HYST_SHIFT 8 /**< Shift value for ACMP_HYST */
#define _ACMP_CFG_HYST_MASK 0xF00UL /**< Bit mask for ACMP_HYST */
#define _ACMP_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */
#define _ACMP_CFG_HYST_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CFG */
#define _ACMP_CFG_HYST_SYM10MV 0x00000001UL /**< Mode SYM10MV for ACMP_CFG */
#define _ACMP_CFG_HYST_SYM20MV 0x00000002UL /**< Mode SYM20MV for ACMP_CFG */
#define _ACMP_CFG_HYST_SYM30MV 0x00000003UL /**< Mode SYM30MV for ACMP_CFG */
#define _ACMP_CFG_HYST_POS10MV 0x00000004UL /**< Mode POS10MV for ACMP_CFG */
#define _ACMP_CFG_HYST_POS20MV 0x00000005UL /**< Mode POS20MV for ACMP_CFG */
#define _ACMP_CFG_HYST_POS30MV 0x00000006UL /**< Mode POS30MV for ACMP_CFG */
#define _ACMP_CFG_HYST_NEG10MV 0x00000008UL /**< Mode NEG10MV for ACMP_CFG */
#define _ACMP_CFG_HYST_NEG20MV 0x00000009UL /**< Mode NEG20MV for ACMP_CFG */
#define _ACMP_CFG_HYST_NEG30MV 0x0000000AUL /**< Mode NEG30MV for ACMP_CFG */
#define ACMP_CFG_HYST_DEFAULT (_ACMP_CFG_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CFG */
#define ACMP_CFG_HYST_DISABLED (_ACMP_CFG_HYST_DISABLED << 8) /**< Shifted mode DISABLED for ACMP_CFG */
#define ACMP_CFG_HYST_SYM10MV (_ACMP_CFG_HYST_SYM10MV << 8) /**< Shifted mode SYM10MV for ACMP_CFG */
#define ACMP_CFG_HYST_SYM20MV (_ACMP_CFG_HYST_SYM20MV << 8) /**< Shifted mode SYM20MV for ACMP_CFG */
#define ACMP_CFG_HYST_SYM30MV (_ACMP_CFG_HYST_SYM30MV << 8) /**< Shifted mode SYM30MV for ACMP_CFG */
#define ACMP_CFG_HYST_POS10MV (_ACMP_CFG_HYST_POS10MV << 8) /**< Shifted mode POS10MV for ACMP_CFG */
#define ACMP_CFG_HYST_POS20MV (_ACMP_CFG_HYST_POS20MV << 8) /**< Shifted mode POS20MV for ACMP_CFG */
#define ACMP_CFG_HYST_POS30MV (_ACMP_CFG_HYST_POS30MV << 8) /**< Shifted mode POS30MV for ACMP_CFG */
#define ACMP_CFG_HYST_NEG10MV (_ACMP_CFG_HYST_NEG10MV << 8) /**< Shifted mode NEG10MV for ACMP_CFG */
#define ACMP_CFG_HYST_NEG20MV (_ACMP_CFG_HYST_NEG20MV << 8) /**< Shifted mode NEG20MV for ACMP_CFG */
#define ACMP_CFG_HYST_NEG30MV (_ACMP_CFG_HYST_NEG30MV << 8) /**< Shifted mode NEG30MV for ACMP_CFG */
#define ACMP_CFG_INPUTRANGE (0x1UL << 16) /**< Input Range */
#define _ACMP_CFG_INPUTRANGE_SHIFT 16 /**< Shift value for ACMP_INPUTRANGE */
#define _ACMP_CFG_INPUTRANGE_MASK 0x10000UL /**< Bit mask for ACMP_INPUTRANGE */
#define _ACMP_CFG_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */
#define _ACMP_CFG_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CFG */
#define _ACMP_CFG_INPUTRANGE_REDUCED 0x00000001UL /**< Mode REDUCED for ACMP_CFG */
#define ACMP_CFG_INPUTRANGE_DEFAULT (_ACMP_CFG_INPUTRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CFG */
#define ACMP_CFG_INPUTRANGE_FULL (_ACMP_CFG_INPUTRANGE_FULL << 16) /**< Shifted mode FULL for ACMP_CFG */
#define ACMP_CFG_INPUTRANGE_REDUCED (_ACMP_CFG_INPUTRANGE_REDUCED << 16) /**< Shifted mode REDUCED for ACMP_CFG */
#define ACMP_CFG_ACCURACY (0x1UL << 17) /**< ACMP accuracy mode */
#define _ACMP_CFG_ACCURACY_SHIFT 17 /**< Shift value for ACMP_ACCURACY */
#define _ACMP_CFG_ACCURACY_MASK 0x20000UL /**< Bit mask for ACMP_ACCURACY */
#define _ACMP_CFG_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */
#define _ACMP_CFG_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CFG */
#define _ACMP_CFG_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CFG */
#define ACMP_CFG_ACCURACY_DEFAULT (_ACMP_CFG_ACCURACY_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CFG */
#define ACMP_CFG_ACCURACY_LOW (_ACMP_CFG_ACCURACY_LOW << 17) /**< Shifted mode LOW for ACMP_CFG */
#define ACMP_CFG_ACCURACY_HIGH (_ACMP_CFG_ACCURACY_HIGH << 17) /**< Shifted mode HIGH for ACMP_CFG */
/* Bit fields for ACMP CTRL */
#define _ACMP_CTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_CTRL */
#define _ACMP_CTRL_MASK 0x00000003UL /**< Mask for ACMP_CTRL */
#define ACMP_CTRL_NOTRDYVAL (0x1UL << 0) /**< Not Ready Value */
#define _ACMP_CTRL_NOTRDYVAL_SHIFT 0 /**< Shift value for ACMP_NOTRDYVAL */
#define _ACMP_CTRL_NOTRDYVAL_MASK 0x1UL /**< Bit mask for ACMP_NOTRDYVAL */
#define _ACMP_CTRL_NOTRDYVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_NOTRDYVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */
#define _ACMP_CTRL_NOTRDYVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */
#define ACMP_CTRL_NOTRDYVAL_DEFAULT (_ACMP_CTRL_NOTRDYVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_NOTRDYVAL_LOW (_ACMP_CTRL_NOTRDYVAL_LOW << 0) /**< Shifted mode LOW for ACMP_CTRL */
#define ACMP_CTRL_NOTRDYVAL_HIGH (_ACMP_CTRL_NOTRDYVAL_HIGH << 0) /**< Shifted mode HIGH for ACMP_CTRL */
#define ACMP_CTRL_GPIOINV (0x1UL << 1) /**< Comparator GPIO Output Invert */
#define _ACMP_CTRL_GPIOINV_SHIFT 1 /**< Shift value for ACMP_GPIOINV */
#define _ACMP_CTRL_GPIOINV_MASK 0x2UL /**< Bit mask for ACMP_GPIOINV */
#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */
#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */
#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 1) /**< Shifted mode NOTINV for ACMP_CTRL */
#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 1) /**< Shifted mode INV for ACMP_CTRL */
/* Bit fields for ACMP INPUTCTRL */
#define _ACMP_INPUTCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_MASK 0x703FFFFFUL /**< Mask for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */
#define _ACMP_INPUTCTRL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */
#define _ACMP_INPUTCTRL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_VDACOUT0 0x00000040UL /**< Mode VDACOUT0 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_VDACOUT1 0x00000041UL /**< Mode VDACOUT1 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_EXTPA 0x00000050UL /**< Mode EXTPA for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_EXTPB 0x00000051UL /**< Mode EXTPB for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_EXTPC 0x00000052UL /**< Mode EXTPC for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_EXTPD 0x00000053UL /**< Mode EXTPD for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_POSSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_DEFAULT (_ACMP_INPUTCTRL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_VSS (_ACMP_INPUTCTRL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD << 0) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP << 0) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/
#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 << 0) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP << 0) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/
#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 << 0) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP << 0) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/
#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 << 0) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/
#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP << 0) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/
#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 << 0) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/
#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP << 0) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/
#define ACMP_INPUTCTRL_POSSEL_VDACOUT0 (_ACMP_INPUTCTRL_POSSEL_VDACOUT0 << 0) /**< Shifted mode VDACOUT0 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_VDACOUT1 (_ACMP_INPUTCTRL_POSSEL_VDACOUT1 << 0) /**< Shifted mode VDACOUT1 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_EXTPA (_ACMP_INPUTCTRL_POSSEL_EXTPA << 0) /**< Shifted mode EXTPA for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_EXTPB (_ACMP_INPUTCTRL_POSSEL_EXTPB << 0) /**< Shifted mode EXTPB for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_EXTPC (_ACMP_INPUTCTRL_POSSEL_EXTPC << 0) /**< Shifted mode EXTPC for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_EXTPD (_ACMP_INPUTCTRL_POSSEL_EXTPD << 0) /**< Shifted mode EXTPD for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA0 (_ACMP_INPUTCTRL_POSSEL_PA0 << 0) /**< Shifted mode PA0 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA1 (_ACMP_INPUTCTRL_POSSEL_PA1 << 0) /**< Shifted mode PA1 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA2 (_ACMP_INPUTCTRL_POSSEL_PA2 << 0) /**< Shifted mode PA2 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA3 (_ACMP_INPUTCTRL_POSSEL_PA3 << 0) /**< Shifted mode PA3 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA4 (_ACMP_INPUTCTRL_POSSEL_PA4 << 0) /**< Shifted mode PA4 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA5 (_ACMP_INPUTCTRL_POSSEL_PA5 << 0) /**< Shifted mode PA5 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA6 (_ACMP_INPUTCTRL_POSSEL_PA6 << 0) /**< Shifted mode PA6 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA7 (_ACMP_INPUTCTRL_POSSEL_PA7 << 0) /**< Shifted mode PA7 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA8 (_ACMP_INPUTCTRL_POSSEL_PA8 << 0) /**< Shifted mode PA8 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA9 (_ACMP_INPUTCTRL_POSSEL_PA9 << 0) /**< Shifted mode PA9 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA10 (_ACMP_INPUTCTRL_POSSEL_PA10 << 0) /**< Shifted mode PA10 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA11 (_ACMP_INPUTCTRL_POSSEL_PA11 << 0) /**< Shifted mode PA11 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA12 (_ACMP_INPUTCTRL_POSSEL_PA12 << 0) /**< Shifted mode PA12 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA13 (_ACMP_INPUTCTRL_POSSEL_PA13 << 0) /**< Shifted mode PA13 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA14 (_ACMP_INPUTCTRL_POSSEL_PA14 << 0) /**< Shifted mode PA14 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PA15 (_ACMP_INPUTCTRL_POSSEL_PA15 << 0) /**< Shifted mode PA15 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB0 (_ACMP_INPUTCTRL_POSSEL_PB0 << 0) /**< Shifted mode PB0 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB1 (_ACMP_INPUTCTRL_POSSEL_PB1 << 0) /**< Shifted mode PB1 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB2 (_ACMP_INPUTCTRL_POSSEL_PB2 << 0) /**< Shifted mode PB2 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB3 (_ACMP_INPUTCTRL_POSSEL_PB3 << 0) /**< Shifted mode PB3 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB4 (_ACMP_INPUTCTRL_POSSEL_PB4 << 0) /**< Shifted mode PB4 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB5 (_ACMP_INPUTCTRL_POSSEL_PB5 << 0) /**< Shifted mode PB5 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB6 (_ACMP_INPUTCTRL_POSSEL_PB6 << 0) /**< Shifted mode PB6 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB7 (_ACMP_INPUTCTRL_POSSEL_PB7 << 0) /**< Shifted mode PB7 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB8 (_ACMP_INPUTCTRL_POSSEL_PB8 << 0) /**< Shifted mode PB8 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB9 (_ACMP_INPUTCTRL_POSSEL_PB9 << 0) /**< Shifted mode PB9 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB10 (_ACMP_INPUTCTRL_POSSEL_PB10 << 0) /**< Shifted mode PB10 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB11 (_ACMP_INPUTCTRL_POSSEL_PB11 << 0) /**< Shifted mode PB11 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB12 (_ACMP_INPUTCTRL_POSSEL_PB12 << 0) /**< Shifted mode PB12 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB13 (_ACMP_INPUTCTRL_POSSEL_PB13 << 0) /**< Shifted mode PB13 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB14 (_ACMP_INPUTCTRL_POSSEL_PB14 << 0) /**< Shifted mode PB14 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PB15 (_ACMP_INPUTCTRL_POSSEL_PB15 << 0) /**< Shifted mode PB15 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC0 (_ACMP_INPUTCTRL_POSSEL_PC0 << 0) /**< Shifted mode PC0 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC1 (_ACMP_INPUTCTRL_POSSEL_PC1 << 0) /**< Shifted mode PC1 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC2 (_ACMP_INPUTCTRL_POSSEL_PC2 << 0) /**< Shifted mode PC2 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC3 (_ACMP_INPUTCTRL_POSSEL_PC3 << 0) /**< Shifted mode PC3 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC4 (_ACMP_INPUTCTRL_POSSEL_PC4 << 0) /**< Shifted mode PC4 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC5 (_ACMP_INPUTCTRL_POSSEL_PC5 << 0) /**< Shifted mode PC5 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC6 (_ACMP_INPUTCTRL_POSSEL_PC6 << 0) /**< Shifted mode PC6 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC7 (_ACMP_INPUTCTRL_POSSEL_PC7 << 0) /**< Shifted mode PC7 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC8 (_ACMP_INPUTCTRL_POSSEL_PC8 << 0) /**< Shifted mode PC8 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC9 (_ACMP_INPUTCTRL_POSSEL_PC9 << 0) /**< Shifted mode PC9 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC10 (_ACMP_INPUTCTRL_POSSEL_PC10 << 0) /**< Shifted mode PC10 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC11 (_ACMP_INPUTCTRL_POSSEL_PC11 << 0) /**< Shifted mode PC11 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC12 (_ACMP_INPUTCTRL_POSSEL_PC12 << 0) /**< Shifted mode PC12 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC13 (_ACMP_INPUTCTRL_POSSEL_PC13 << 0) /**< Shifted mode PC13 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC14 (_ACMP_INPUTCTRL_POSSEL_PC14 << 0) /**< Shifted mode PC14 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PC15 (_ACMP_INPUTCTRL_POSSEL_PC15 << 0) /**< Shifted mode PC15 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD0 (_ACMP_INPUTCTRL_POSSEL_PD0 << 0) /**< Shifted mode PD0 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD1 (_ACMP_INPUTCTRL_POSSEL_PD1 << 0) /**< Shifted mode PD1 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD2 (_ACMP_INPUTCTRL_POSSEL_PD2 << 0) /**< Shifted mode PD2 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD3 (_ACMP_INPUTCTRL_POSSEL_PD3 << 0) /**< Shifted mode PD3 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD4 (_ACMP_INPUTCTRL_POSSEL_PD4 << 0) /**< Shifted mode PD4 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD5 (_ACMP_INPUTCTRL_POSSEL_PD5 << 0) /**< Shifted mode PD5 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD6 (_ACMP_INPUTCTRL_POSSEL_PD6 << 0) /**< Shifted mode PD6 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD7 (_ACMP_INPUTCTRL_POSSEL_PD7 << 0) /**< Shifted mode PD7 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD8 (_ACMP_INPUTCTRL_POSSEL_PD8 << 0) /**< Shifted mode PD8 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD9 (_ACMP_INPUTCTRL_POSSEL_PD9 << 0) /**< Shifted mode PD9 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD10 (_ACMP_INPUTCTRL_POSSEL_PD10 << 0) /**< Shifted mode PD10 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD11 (_ACMP_INPUTCTRL_POSSEL_PD11 << 0) /**< Shifted mode PD11 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD12 (_ACMP_INPUTCTRL_POSSEL_PD12 << 0) /**< Shifted mode PD12 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD13 (_ACMP_INPUTCTRL_POSSEL_PD13 << 0) /**< Shifted mode PD13 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD14 (_ACMP_INPUTCTRL_POSSEL_PD14 << 0) /**< Shifted mode PD14 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_POSSEL_PD15 (_ACMP_INPUTCTRL_POSSEL_PD15 << 0) /**< Shifted mode PD15 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */
#define _ACMP_INPUTCTRL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */
#define _ACMP_INPUTCTRL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_CAPSENSE 0x00000030UL /**< Mode CAPSENSE for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_VDACOUT0 0x00000040UL /**< Mode VDACOUT0 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_VDACOUT1 0x00000041UL /**< Mode VDACOUT1 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_NEGSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_DEFAULT (_ACMP_INPUTCTRL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_VSS (_ACMP_INPUTCTRL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD << 8) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP << 8) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/
#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 << 8) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP << 8) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/
#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 << 8) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP << 8) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/
#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 << 8) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/
#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP << 8) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/
#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 << 8) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/
#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP << 8) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/
#define ACMP_INPUTCTRL_NEGSEL_CAPSENSE (_ACMP_INPUTCTRL_NEGSEL_CAPSENSE << 8) /**< Shifted mode CAPSENSE for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_VDACOUT0 (_ACMP_INPUTCTRL_NEGSEL_VDACOUT0 << 8) /**< Shifted mode VDACOUT0 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_VDACOUT1 (_ACMP_INPUTCTRL_NEGSEL_VDACOUT1 << 8) /**< Shifted mode VDACOUT1 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA0 (_ACMP_INPUTCTRL_NEGSEL_PA0 << 8) /**< Shifted mode PA0 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA1 (_ACMP_INPUTCTRL_NEGSEL_PA1 << 8) /**< Shifted mode PA1 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA2 (_ACMP_INPUTCTRL_NEGSEL_PA2 << 8) /**< Shifted mode PA2 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA3 (_ACMP_INPUTCTRL_NEGSEL_PA3 << 8) /**< Shifted mode PA3 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA4 (_ACMP_INPUTCTRL_NEGSEL_PA4 << 8) /**< Shifted mode PA4 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA5 (_ACMP_INPUTCTRL_NEGSEL_PA5 << 8) /**< Shifted mode PA5 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA6 (_ACMP_INPUTCTRL_NEGSEL_PA6 << 8) /**< Shifted mode PA6 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA7 (_ACMP_INPUTCTRL_NEGSEL_PA7 << 8) /**< Shifted mode PA7 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA8 (_ACMP_INPUTCTRL_NEGSEL_PA8 << 8) /**< Shifted mode PA8 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA9 (_ACMP_INPUTCTRL_NEGSEL_PA9 << 8) /**< Shifted mode PA9 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA10 (_ACMP_INPUTCTRL_NEGSEL_PA10 << 8) /**< Shifted mode PA10 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA11 (_ACMP_INPUTCTRL_NEGSEL_PA11 << 8) /**< Shifted mode PA11 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA12 (_ACMP_INPUTCTRL_NEGSEL_PA12 << 8) /**< Shifted mode PA12 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA13 (_ACMP_INPUTCTRL_NEGSEL_PA13 << 8) /**< Shifted mode PA13 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA14 (_ACMP_INPUTCTRL_NEGSEL_PA14 << 8) /**< Shifted mode PA14 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PA15 (_ACMP_INPUTCTRL_NEGSEL_PA15 << 8) /**< Shifted mode PA15 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB0 (_ACMP_INPUTCTRL_NEGSEL_PB0 << 8) /**< Shifted mode PB0 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB1 (_ACMP_INPUTCTRL_NEGSEL_PB1 << 8) /**< Shifted mode PB1 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB2 (_ACMP_INPUTCTRL_NEGSEL_PB2 << 8) /**< Shifted mode PB2 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB3 (_ACMP_INPUTCTRL_NEGSEL_PB3 << 8) /**< Shifted mode PB3 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB4 (_ACMP_INPUTCTRL_NEGSEL_PB4 << 8) /**< Shifted mode PB4 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB5 (_ACMP_INPUTCTRL_NEGSEL_PB5 << 8) /**< Shifted mode PB5 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB6 (_ACMP_INPUTCTRL_NEGSEL_PB6 << 8) /**< Shifted mode PB6 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB7 (_ACMP_INPUTCTRL_NEGSEL_PB7 << 8) /**< Shifted mode PB7 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB8 (_ACMP_INPUTCTRL_NEGSEL_PB8 << 8) /**< Shifted mode PB8 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB9 (_ACMP_INPUTCTRL_NEGSEL_PB9 << 8) /**< Shifted mode PB9 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB10 (_ACMP_INPUTCTRL_NEGSEL_PB10 << 8) /**< Shifted mode PB10 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB11 (_ACMP_INPUTCTRL_NEGSEL_PB11 << 8) /**< Shifted mode PB11 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB12 (_ACMP_INPUTCTRL_NEGSEL_PB12 << 8) /**< Shifted mode PB12 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB13 (_ACMP_INPUTCTRL_NEGSEL_PB13 << 8) /**< Shifted mode PB13 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB14 (_ACMP_INPUTCTRL_NEGSEL_PB14 << 8) /**< Shifted mode PB14 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PB15 (_ACMP_INPUTCTRL_NEGSEL_PB15 << 8) /**< Shifted mode PB15 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC0 (_ACMP_INPUTCTRL_NEGSEL_PC0 << 8) /**< Shifted mode PC0 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC1 (_ACMP_INPUTCTRL_NEGSEL_PC1 << 8) /**< Shifted mode PC1 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC2 (_ACMP_INPUTCTRL_NEGSEL_PC2 << 8) /**< Shifted mode PC2 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC3 (_ACMP_INPUTCTRL_NEGSEL_PC3 << 8) /**< Shifted mode PC3 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC4 (_ACMP_INPUTCTRL_NEGSEL_PC4 << 8) /**< Shifted mode PC4 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC5 (_ACMP_INPUTCTRL_NEGSEL_PC5 << 8) /**< Shifted mode PC5 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC6 (_ACMP_INPUTCTRL_NEGSEL_PC6 << 8) /**< Shifted mode PC6 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC7 (_ACMP_INPUTCTRL_NEGSEL_PC7 << 8) /**< Shifted mode PC7 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC8 (_ACMP_INPUTCTRL_NEGSEL_PC8 << 8) /**< Shifted mode PC8 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC9 (_ACMP_INPUTCTRL_NEGSEL_PC9 << 8) /**< Shifted mode PC9 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC10 (_ACMP_INPUTCTRL_NEGSEL_PC10 << 8) /**< Shifted mode PC10 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC11 (_ACMP_INPUTCTRL_NEGSEL_PC11 << 8) /**< Shifted mode PC11 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC12 (_ACMP_INPUTCTRL_NEGSEL_PC12 << 8) /**< Shifted mode PC12 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC13 (_ACMP_INPUTCTRL_NEGSEL_PC13 << 8) /**< Shifted mode PC13 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC14 (_ACMP_INPUTCTRL_NEGSEL_PC14 << 8) /**< Shifted mode PC14 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PC15 (_ACMP_INPUTCTRL_NEGSEL_PC15 << 8) /**< Shifted mode PC15 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD0 (_ACMP_INPUTCTRL_NEGSEL_PD0 << 8) /**< Shifted mode PD0 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD1 (_ACMP_INPUTCTRL_NEGSEL_PD1 << 8) /**< Shifted mode PD1 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD2 (_ACMP_INPUTCTRL_NEGSEL_PD2 << 8) /**< Shifted mode PD2 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD3 (_ACMP_INPUTCTRL_NEGSEL_PD3 << 8) /**< Shifted mode PD3 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD4 (_ACMP_INPUTCTRL_NEGSEL_PD4 << 8) /**< Shifted mode PD4 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD5 (_ACMP_INPUTCTRL_NEGSEL_PD5 << 8) /**< Shifted mode PD5 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD6 (_ACMP_INPUTCTRL_NEGSEL_PD6 << 8) /**< Shifted mode PD6 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD7 (_ACMP_INPUTCTRL_NEGSEL_PD7 << 8) /**< Shifted mode PD7 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD8 (_ACMP_INPUTCTRL_NEGSEL_PD8 << 8) /**< Shifted mode PD8 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD9 (_ACMP_INPUTCTRL_NEGSEL_PD9 << 8) /**< Shifted mode PD9 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD10 (_ACMP_INPUTCTRL_NEGSEL_PD10 << 8) /**< Shifted mode PD10 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD11 (_ACMP_INPUTCTRL_NEGSEL_PD11 << 8) /**< Shifted mode PD11 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD12 (_ACMP_INPUTCTRL_NEGSEL_PD12 << 8) /**< Shifted mode PD12 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD13 (_ACMP_INPUTCTRL_NEGSEL_PD13 << 8) /**< Shifted mode PD13 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD14 (_ACMP_INPUTCTRL_NEGSEL_PD14 << 8) /**< Shifted mode PD14 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_NEGSEL_PD15 (_ACMP_INPUTCTRL_NEGSEL_PD15 << 8) /**< Shifted mode PD15 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_VREFDIV_SHIFT 16 /**< Shift value for ACMP_VREFDIV */
#define _ACMP_INPUTCTRL_VREFDIV_MASK 0x3F0000UL /**< Bit mask for ACMP_VREFDIV */
#define _ACMP_INPUTCTRL_VREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_VREFDIV_DEFAULT (_ACMP_INPUTCTRL_VREFDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */
#define _ACMP_INPUTCTRL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */
#define _ACMP_INPUTCTRL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTCTRL */
#define _ACMP_INPUTCTRL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_CSRESSEL_DEFAULT (_ACMP_INPUTCTRL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_CSRESSEL_RES0 (_ACMP_INPUTCTRL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_CSRESSEL_RES1 (_ACMP_INPUTCTRL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_CSRESSEL_RES2 (_ACMP_INPUTCTRL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_CSRESSEL_RES3 (_ACMP_INPUTCTRL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_CSRESSEL_RES4 (_ACMP_INPUTCTRL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_CSRESSEL_RES5 (_ACMP_INPUTCTRL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTCTRL */
#define ACMP_INPUTCTRL_CSRESSEL_RES6 (_ACMP_INPUTCTRL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTCTRL */
/* Bit fields for ACMP STATUS */
#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */
#define _ACMP_STATUS_MASK 0x0000001DUL /**< Mask for ACMP_STATUS */
#define ACMP_STATUS_ACMPOUT (0x1UL << 0) /**< Analog Comparator Output */
#define _ACMP_STATUS_ACMPOUT_SHIFT 0 /**< Shift value for ACMP_ACMPOUT */
#define _ACMP_STATUS_ACMPOUT_MASK 0x1UL /**< Bit mask for ACMP_ACMPOUT */
#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */
#define ACMP_STATUS_ACMPRDY (0x1UL << 2) /**< Analog Comparator Ready */
#define _ACMP_STATUS_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */
#define _ACMP_STATUS_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */
#define _ACMP_STATUS_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
#define ACMP_STATUS_ACMPRDY_DEFAULT (_ACMP_STATUS_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */
#define ACMP_STATUS_INPUTCONFLICT (0x1UL << 3) /**< INPUT conflict */
#define _ACMP_STATUS_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */
#define _ACMP_STATUS_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */
#define _ACMP_STATUS_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
#define ACMP_STATUS_INPUTCONFLICT_DEFAULT (_ACMP_STATUS_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */
#define ACMP_STATUS_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */
#define _ACMP_STATUS_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */
#define _ACMP_STATUS_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */
#define _ACMP_STATUS_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
#define ACMP_STATUS_PORTALLOCERR_DEFAULT (_ACMP_STATUS_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_STATUS */
/* Bit fields for ACMP IF */
#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */
#define _ACMP_IF_MASK 0x0000001FUL /**< Mask for ACMP_IF */
#define ACMP_IF_RISE (0x1UL << 0) /**< Rising Edge Triggered Interrupt Flag */
#define _ACMP_IF_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */
#define _ACMP_IF_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */
#define _ACMP_IF_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
#define ACMP_IF_RISE_DEFAULT (_ACMP_IF_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */
#define ACMP_IF_FALL (0x1UL << 1) /**< Falling Edge Triggered Interrupt Flag */
#define _ACMP_IF_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */
#define _ACMP_IF_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */
#define _ACMP_IF_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
#define ACMP_IF_FALL_DEFAULT (_ACMP_IF_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */
#define ACMP_IF_ACMPRDY (0x1UL << 2) /**< ACMP ready Interrupt flag */
#define _ACMP_IF_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */
#define _ACMP_IF_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */
#define _ACMP_IF_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
#define ACMP_IF_ACMPRDY_DEFAULT (_ACMP_IF_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */
#define ACMP_IF_INPUTCONFLICT (0x1UL << 3) /**< Input conflict */
#define _ACMP_IF_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */
#define _ACMP_IF_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */
#define _ACMP_IF_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
#define ACMP_IF_INPUTCONFLICT_DEFAULT (_ACMP_IF_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IF */
#define ACMP_IF_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */
#define _ACMP_IF_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */
#define _ACMP_IF_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */
#define _ACMP_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
#define ACMP_IF_PORTALLOCERR_DEFAULT (_ACMP_IF_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IF */
/* Bit fields for ACMP IEN */
#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */
#define _ACMP_IEN_MASK 0x0000001FUL /**< Mask for ACMP_IEN */
#define ACMP_IEN_RISE (0x1UL << 0) /**< Rising edge interrupt enable */
#define _ACMP_IEN_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */
#define _ACMP_IEN_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */
#define _ACMP_IEN_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_RISE_DEFAULT (_ACMP_IEN_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_FALL (0x1UL << 1) /**< Falling edge interrupt enable */
#define _ACMP_IEN_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */
#define _ACMP_IEN_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */
#define _ACMP_IEN_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_FALL_DEFAULT (_ACMP_IEN_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_ACMPRDY (0x1UL << 2) /**< ACMP ready interrupt enable */
#define _ACMP_IEN_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */
#define _ACMP_IEN_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */
#define _ACMP_IEN_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_ACMPRDY_DEFAULT (_ACMP_IEN_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_INPUTCONFLICT (0x1UL << 3) /**< Input conflict interrupt enable */
#define _ACMP_IEN_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */
#define _ACMP_IEN_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */
#define _ACMP_IEN_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_INPUTCONFLICT_DEFAULT (_ACMP_IEN_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_PORTALLOCERR (0x1UL << 4) /**< Port allocation error interrupt enable */
#define _ACMP_IEN_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */
#define _ACMP_IEN_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */
#define _ACMP_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_PORTALLOCERR_DEFAULT (_ACMP_IEN_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IEN */
/* Bit fields for ACMP SYNCBUSY */
#define _ACMP_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ACMP_SYNCBUSY */
#define _ACMP_SYNCBUSY_MASK 0x00000001UL /**< Mask for ACMP_SYNCBUSY */
#define ACMP_SYNCBUSY_INPUTCTRL (0x1UL << 0) /**< Syncbusy for INPUTCTRL */
#define _ACMP_SYNCBUSY_INPUTCTRL_SHIFT 0 /**< Shift value for ACMP_INPUTCTRL */
#define _ACMP_SYNCBUSY_INPUTCTRL_MASK 0x1UL /**< Bit mask for ACMP_INPUTCTRL */
#define _ACMP_SYNCBUSY_INPUTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SYNCBUSY */
#define ACMP_SYNCBUSY_INPUTCTRL_DEFAULT (_ACMP_SYNCBUSY_INPUTCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SYNCBUSY */
/** @} End of group EFR32ZG23_ACMP_BitFields */
/** @} End of group EFR32ZG23_ACMP */
/** @} End of group Parts */
#endif /* EFR32ZG23_ACMP_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 AES register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_AES_H
#define EFR32ZG23_AES_H
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_AES AES
* @{
* @brief EFR32ZG23 AES Register Declaration.
*****************************************************************************/
/** AES Register Declaration. */
typedef struct {
__IOM uint32_t FETCHADDR; /**< Fetcher Address */
uint32_t RESERVED0[1U]; /**< Reserved for future use */
__IOM uint32_t FETCHLEN; /**< Fetcher Length */
__IOM uint32_t FETCHTAG; /**< Fetcher Tag */
__IOM uint32_t PUSHADDR; /**< Pusher Address */
uint32_t RESERVED1[1U]; /**< Reserved for future use */
__IOM uint32_t PUSHLEN; /**< Pusher Length */
__IOM uint32_t IEN; /**< Interrupt Enable */
uint32_t RESERVED2[2U]; /**< Reserved for future use */
__IM uint32_t IF; /**< Interrupt Flags */
uint32_t RESERVED3[1U]; /**< Reserved for future use */
__IOM uint32_t IF_CLR; /**< Interrupt status clear */
__IOM uint32_t CTRL; /**< Control register */
__IOM uint32_t CMD; /**< Command register */
__IM uint32_t STATUS; /**< Status register */
uint32_t RESERVED4[240U]; /**< Reserved for future use */
__IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */
__IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */
__IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */
__IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */
__IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */
__IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */
} AES_TypeDef;
/** @} End of group EFR32ZG23_AES */
/**************************************************************************//**
* @addtogroup EFR32ZG23_AES
* @{
* @defgroup EFR32ZG23_AES_BitFields AES Bit Fields
* @{
*****************************************************************************/
/* Bit fields for AES FETCHADDR */
#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */
#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */
#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */
#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */
#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */
#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */
/* Bit fields for AES FETCHLEN */
#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */
#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */
#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */
#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */
#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */
#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */
#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */
#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */
#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */
#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */
#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */
#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */
#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */
#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */
#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */
#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */
/* Bit fields for AES FETCHTAG */
#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */
#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */
#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */
#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */
#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */
#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */
/* Bit fields for AES PUSHADDR */
#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */
#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */
#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */
#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */
#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */
#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */
/* Bit fields for AES PUSHLEN */
#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */
#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */
#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */
#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */
#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */
#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */
#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */
#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */
#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */
#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */
#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */
#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */
#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */
#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */
#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */
#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */
#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */
#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */
#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */
#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */
#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */
/* Bit fields for AES IEN */
#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */
#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */
#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */
#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */
#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */
#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */
#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */
#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */
#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */
#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */
#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */
#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */
#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */
#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */
#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */
#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */
#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */
#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */
#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */
#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */
#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */
#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */
#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */
#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */
#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */
#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */
/* Bit fields for AES IF */
#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */
#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */
#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */
#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */
#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */
#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */
#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */
#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */
#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */
#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */
#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */
#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */
#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */
#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */
#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */
#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */
#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */
#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */
#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */
#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */
#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */
#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */
#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */
#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */
#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */
#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */
/* Bit fields for AES IF_CLR */
#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */
#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */
#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */
#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */
#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */
#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */
#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */
#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */
#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */
#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */
#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */
#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */
#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */
#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */
#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */
#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */
#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */
#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */
#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */
#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */
#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */
#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */
#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */
#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */
#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */
#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */
#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */
#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */
#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */
#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */
#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */
#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */
/* Bit fields for AES CTRL */
#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */
#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */
#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */
#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */
#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */
#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */
#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */
#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */
#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */
#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */
#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */
#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */
#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */
#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */
#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */
#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */
#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */
#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */
/* Bit fields for AES CMD */
#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */
#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */
#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */
#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */
#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */
#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */
#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */
#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */
#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */
#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */
/* Bit fields for AES STATUS */
#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */
#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */
#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */
#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */
#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */
#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */
#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */
#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */
#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */
#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */
#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */
#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */
#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */
#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */
#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */
#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */
#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */
#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */
#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */
#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */
#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */
#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */
#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */
#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */
#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */
/* Bit fields for AES INCL_IPS_HW_CFG */
#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */
#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */
#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */
#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */
#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */
#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */
#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */
#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */
#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */
#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */
#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */
#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */
#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */
#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */
#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */
#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */
#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */
#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */
#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */
#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */
#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */
#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */
#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */
#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */
#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */
#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */
#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */
#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */
#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */
#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */
#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */
#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */
#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */
#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */
#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */
#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
/* Bit fields for AES BA411E_HW_CFG_1 */
#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */
#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */
#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */
#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */
#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */
#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/
#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */
#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */
#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */
#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */
#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/
#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */
#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */
#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */
#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */
#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/
#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */
#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */
#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */
#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/
/* Bit fields for AES BA411E_HW_CFG_2 */
#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */
#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */
#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */
#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */
#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */
#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/
/* Bit fields for AES BA413_HW_CFG */
#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */
#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */
#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */
#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */
#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */
#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */
#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */
#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */
#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */
#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */
#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */
#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */
#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */
#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */
#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */
#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */
#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */
#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */
#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */
#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */
#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */
/* Bit fields for AES BA418_HW_CFG */
#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */
#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */
#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */
#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */
#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */
#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */
#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */
/* Bit fields for AES BA419_HW_CFG */
#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */
#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */
#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */
#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */
#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */
#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */
/** @} End of group EFR32ZG23_AES_BitFields */
/** @} End of group EFR32ZG23_AES */
/** @} End of group Parts */
#endif /* EFR32ZG23_AES_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 AMUXCP register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_AMUXCP_H
#define EFR32ZG23_AMUXCP_H
#define AMUXCP_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_AMUXCP AMUXCP
* @{
* @brief EFR32ZG23 AMUXCP Register Declaration.
*****************************************************************************/
/** AMUXCP Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IPVERSION */
uint32_t RESERVED0[1U]; /**< Reserved for future use */
__IOM uint32_t CTRL; /**< Control */
__IM uint32_t STATUS; /**< Status */
__IOM uint32_t TEST; /**< Test */
__IOM uint32_t TRIM; /**< Trim */
uint32_t RESERVED1[1018U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IPVERSION */
uint32_t RESERVED2[1U]; /**< Reserved for future use */
__IOM uint32_t CTRL_SET; /**< Control */
__IM uint32_t STATUS_SET; /**< Status */
__IOM uint32_t TEST_SET; /**< Test */
__IOM uint32_t TRIM_SET; /**< Trim */
uint32_t RESERVED3[1018U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IPVERSION */
uint32_t RESERVED4[1U]; /**< Reserved for future use */
__IOM uint32_t CTRL_CLR; /**< Control */
__IM uint32_t STATUS_CLR; /**< Status */
__IOM uint32_t TEST_CLR; /**< Test */
__IOM uint32_t TRIM_CLR; /**< Trim */
uint32_t RESERVED5[1018U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IPVERSION */
uint32_t RESERVED6[1U]; /**< Reserved for future use */
__IOM uint32_t CTRL_TGL; /**< Control */
__IM uint32_t STATUS_TGL; /**< Status */
__IOM uint32_t TEST_TGL; /**< Test */
__IOM uint32_t TRIM_TGL; /**< Trim */
} AMUXCP_TypeDef;
/** @} End of group EFR32ZG23_AMUXCP */
/**************************************************************************//**
* @addtogroup EFR32ZG23_AMUXCP
* @{
* @defgroup EFR32ZG23_AMUXCP_BitFields AMUXCP Bit Fields
* @{
*****************************************************************************/
/* Bit fields for AMUXCP IPVERSION */
#define _AMUXCP_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for AMUXCP_IPVERSION */
#define _AMUXCP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for AMUXCP_IPVERSION */
#define _AMUXCP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for AMUXCP_IPVERSION */
#define _AMUXCP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for AMUXCP_IPVERSION */
#define _AMUXCP_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_IPVERSION */
#define AMUXCP_IPVERSION_IPVERSION_DEFAULT (_AMUXCP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_IPVERSION */
/* Bit fields for AMUXCP CTRL */
#define _AMUXCP_CTRL_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_CTRL */
#define _AMUXCP_CTRL_MASK 0x00000033UL /**< Mask for AMUXCP_CTRL */
#define AMUXCP_CTRL_FORCEHP (0x1UL << 0) /**< Force High Power */
#define _AMUXCP_CTRL_FORCEHP_SHIFT 0 /**< Shift value for AMUXCP_FORCEHP */
#define _AMUXCP_CTRL_FORCEHP_MASK 0x1UL /**< Bit mask for AMUXCP_FORCEHP */
#define _AMUXCP_CTRL_FORCEHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */
#define AMUXCP_CTRL_FORCEHP_DEFAULT (_AMUXCP_CTRL_FORCEHP_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_CTRL */
#define AMUXCP_CTRL_FORCELP (0x1UL << 1) /**< Force Low Power */
#define _AMUXCP_CTRL_FORCELP_SHIFT 1 /**< Shift value for AMUXCP_FORCELP */
#define _AMUXCP_CTRL_FORCELP_MASK 0x2UL /**< Bit mask for AMUXCP_FORCELP */
#define _AMUXCP_CTRL_FORCELP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */
#define AMUXCP_CTRL_FORCELP_DEFAULT (_AMUXCP_CTRL_FORCELP_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_CTRL */
#define AMUXCP_CTRL_FORCERUN (0x1UL << 4) /**< Force run */
#define _AMUXCP_CTRL_FORCERUN_SHIFT 4 /**< Shift value for AMUXCP_FORCERUN */
#define _AMUXCP_CTRL_FORCERUN_MASK 0x10UL /**< Bit mask for AMUXCP_FORCERUN */
#define _AMUXCP_CTRL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */
#define AMUXCP_CTRL_FORCERUN_DEFAULT (_AMUXCP_CTRL_FORCERUN_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_CTRL */
#define AMUXCP_CTRL_FORCESTOP (0x1UL << 5) /**< Force stop */
#define _AMUXCP_CTRL_FORCESTOP_SHIFT 5 /**< Shift value for AMUXCP_FORCESTOP */
#define _AMUXCP_CTRL_FORCESTOP_MASK 0x20UL /**< Bit mask for AMUXCP_FORCESTOP */
#define _AMUXCP_CTRL_FORCESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */
#define AMUXCP_CTRL_FORCESTOP_DEFAULT (_AMUXCP_CTRL_FORCESTOP_DEFAULT << 5) /**< Shifted mode DEFAULT for AMUXCP_CTRL */
/* Bit fields for AMUXCP STATUS */
#define _AMUXCP_STATUS_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_STATUS */
#define _AMUXCP_STATUS_MASK 0x00000003UL /**< Mask for AMUXCP_STATUS */
#define AMUXCP_STATUS_RUN (0x1UL << 0) /**< running */
#define _AMUXCP_STATUS_RUN_SHIFT 0 /**< Shift value for AMUXCP_RUN */
#define _AMUXCP_STATUS_RUN_MASK 0x1UL /**< Bit mask for AMUXCP_RUN */
#define _AMUXCP_STATUS_RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_STATUS */
#define AMUXCP_STATUS_RUN_DEFAULT (_AMUXCP_STATUS_RUN_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_STATUS */
#define AMUXCP_STATUS_HICAP (0x1UL << 1) /**< high cap */
#define _AMUXCP_STATUS_HICAP_SHIFT 1 /**< Shift value for AMUXCP_HICAP */
#define _AMUXCP_STATUS_HICAP_MASK 0x2UL /**< Bit mask for AMUXCP_HICAP */
#define _AMUXCP_STATUS_HICAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_STATUS */
#define AMUXCP_STATUS_HICAP_DEFAULT (_AMUXCP_STATUS_HICAP_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_STATUS */
/* Bit fields for AMUXCP TEST */
#define _AMUXCP_TEST_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_TEST */
#define _AMUXCP_TEST_MASK 0x80003313UL /**< Mask for AMUXCP_TEST */
#define AMUXCP_TEST_SYNCCLK (0x1UL << 0) /**< Sync Clock */
#define _AMUXCP_TEST_SYNCCLK_SHIFT 0 /**< Shift value for AMUXCP_SYNCCLK */
#define _AMUXCP_TEST_SYNCCLK_MASK 0x1UL /**< Bit mask for AMUXCP_SYNCCLK */
#define _AMUXCP_TEST_SYNCCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_SYNCCLK_DEFAULT (_AMUXCP_TEST_SYNCCLK_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_SYNCMODE (0x1UL << 1) /**< Sync Mode */
#define _AMUXCP_TEST_SYNCMODE_SHIFT 1 /**< Shift value for AMUXCP_SYNCMODE */
#define _AMUXCP_TEST_SYNCMODE_MASK 0x2UL /**< Bit mask for AMUXCP_SYNCMODE */
#define _AMUXCP_TEST_SYNCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_SYNCMODE_DEFAULT (_AMUXCP_TEST_SYNCMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_FORCEREQUEST (0x1UL << 4) /**< Force Request */
#define _AMUXCP_TEST_FORCEREQUEST_SHIFT 4 /**< Shift value for AMUXCP_FORCEREQUEST */
#define _AMUXCP_TEST_FORCEREQUEST_MASK 0x10UL /**< Bit mask for AMUXCP_FORCEREQUEST */
#define _AMUXCP_TEST_FORCEREQUEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_FORCEREQUEST_DEFAULT (_AMUXCP_TEST_FORCEREQUEST_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_FORCEHICAP (0x1UL << 8) /**< Force high capacitance driver */
#define _AMUXCP_TEST_FORCEHICAP_SHIFT 8 /**< Shift value for AMUXCP_FORCEHICAP */
#define _AMUXCP_TEST_FORCEHICAP_MASK 0x100UL /**< Bit mask for AMUXCP_FORCEHICAP */
#define _AMUXCP_TEST_FORCEHICAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_FORCEHICAP_DEFAULT (_AMUXCP_TEST_FORCEHICAP_DEFAULT << 8) /**< Shifted mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_FORCELOCAP (0x1UL << 9) /**< Force low capacitance driver */
#define _AMUXCP_TEST_FORCELOCAP_SHIFT 9 /**< Shift value for AMUXCP_FORCELOCAP */
#define _AMUXCP_TEST_FORCELOCAP_MASK 0x200UL /**< Bit mask for AMUXCP_FORCELOCAP */
#define _AMUXCP_TEST_FORCELOCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_FORCELOCAP_DEFAULT (_AMUXCP_TEST_FORCELOCAP_DEFAULT << 9) /**< Shifted mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_FORCEBOOSTON (0x1UL << 12) /**< Force Boost On */
#define _AMUXCP_TEST_FORCEBOOSTON_SHIFT 12 /**< Shift value for AMUXCP_FORCEBOOSTON */
#define _AMUXCP_TEST_FORCEBOOSTON_MASK 0x1000UL /**< Bit mask for AMUXCP_FORCEBOOSTON */
#define _AMUXCP_TEST_FORCEBOOSTON_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_FORCEBOOSTON_DEFAULT (_AMUXCP_TEST_FORCEBOOSTON_DEFAULT << 12) /**< Shifted mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_FORCEBOOSTOFF (0x1UL << 13) /**< Force Boost Off */
#define _AMUXCP_TEST_FORCEBOOSTOFF_SHIFT 13 /**< Shift value for AMUXCP_FORCEBOOSTOFF */
#define _AMUXCP_TEST_FORCEBOOSTOFF_MASK 0x2000UL /**< Bit mask for AMUXCP_FORCEBOOSTOFF */
#define _AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT (_AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT << 13) /**< Shifted mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_STATUSEN (0x1UL << 31) /**< Enable write to status bits */
#define _AMUXCP_TEST_STATUSEN_SHIFT 31 /**< Shift value for AMUXCP_STATUSEN */
#define _AMUXCP_TEST_STATUSEN_MASK 0x80000000UL /**< Bit mask for AMUXCP_STATUSEN */
#define _AMUXCP_TEST_STATUSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
#define AMUXCP_TEST_STATUSEN_DEFAULT (_AMUXCP_TEST_STATUSEN_DEFAULT << 31) /**< Shifted mode DEFAULT for AMUXCP_TEST */
/* Bit fields for AMUXCP TRIM */
#define _AMUXCP_TRIM_RESETVALUE 0x77E44AA1UL /**< Default value for AMUXCP_TRIM */
#define _AMUXCP_TRIM_MASK 0x77FFEFFFUL /**< Mask for AMUXCP_TRIM */
#define _AMUXCP_TRIM_WARMUPTIME_SHIFT 0 /**< Shift value for AMUXCP_WARMUPTIME */
#define _AMUXCP_TRIM_WARMUPTIME_MASK 0x3UL /**< Bit mask for AMUXCP_WARMUPTIME */
#define _AMUXCP_TRIM_WARMUPTIME_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 0x00000000UL /**< Mode WUCYCLES72 for AMUXCP_TRIM */
#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 0x00000001UL /**< Mode WUCYCLES96 for AMUXCP_TRIM */
#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 0x00000002UL /**< Mode WUCYCLES128 for AMUXCP_TRIM */
#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 0x00000003UL /**< Mode WUCYCLES160 for AMUXCP_TRIM */
#define AMUXCP_TRIM_WARMUPTIME_DEFAULT (_AMUXCP_TRIM_WARMUPTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 << 0) /**< Shifted mode WUCYCLES72 for AMUXCP_TRIM */
#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 << 0) /**< Shifted mode WUCYCLES96 for AMUXCP_TRIM */
#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 << 0) /**< Shifted mode WUCYCLES128 for AMUXCP_TRIM */
#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 << 0) /**< Shifted mode WUCYCLES160 for AMUXCP_TRIM */
#define AMUXCP_TRIM_FLOATVDDCPLO (0x1UL << 2) /**< Float VDDCP Low Power */
#define _AMUXCP_TRIM_FLOATVDDCPLO_SHIFT 2 /**< Shift value for AMUXCP_FLOATVDDCPLO */
#define _AMUXCP_TRIM_FLOATVDDCPLO_MASK 0x4UL /**< Bit mask for AMUXCP_FLOATVDDCPLO */
#define _AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT (_AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT << 2) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_FLOATVDDCPHI (0x1UL << 3) /**< Float VDDCP High Power */
#define _AMUXCP_TRIM_FLOATVDDCPHI_SHIFT 3 /**< Shift value for AMUXCP_FLOATVDDCPHI */
#define _AMUXCP_TRIM_FLOATVDDCPHI_MASK 0x8UL /**< Bit mask for AMUXCP_FLOATVDDCPHI */
#define _AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT (_AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT << 3) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BYPASSDIV2LO (0x1UL << 4) /**< Bypass Div2 Low Power */
#define _AMUXCP_TRIM_BYPASSDIV2LO_SHIFT 4 /**< Shift value for AMUXCP_BYPASSDIV2LO */
#define _AMUXCP_TRIM_BYPASSDIV2LO_MASK 0x10UL /**< Bit mask for AMUXCP_BYPASSDIV2LO */
#define _AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT (_AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BYPASSDIV2HI (0x1UL << 5) /**< Bypass Div2 High Power */
#define _AMUXCP_TRIM_BYPASSDIV2HI_SHIFT 5 /**< Shift value for AMUXCP_BYPASSDIV2HI */
#define _AMUXCP_TRIM_BYPASSDIV2HI_MASK 0x20UL /**< Bit mask for AMUXCP_BYPASSDIV2HI */
#define _AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT (_AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT << 5) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BUMP0P5XLO (0x1UL << 6) /**< Bump 0.5X Low Power */
#define _AMUXCP_TRIM_BUMP0P5XLO_SHIFT 6 /**< Shift value for AMUXCP_BUMP0P5XLO */
#define _AMUXCP_TRIM_BUMP0P5XLO_MASK 0x40UL /**< Bit mask for AMUXCP_BUMP0P5XLO */
#define _AMUXCP_TRIM_BUMP0P5XLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BUMP0P5XLO_DEFAULT (_AMUXCP_TRIM_BUMP0P5XLO_DEFAULT << 6) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BUMP0P5XHI (0x1UL << 7) /**< Bump 0.5X High Power */
#define _AMUXCP_TRIM_BUMP0P5XHI_SHIFT 7 /**< Shift value for AMUXCP_BUMP0P5XHI */
#define _AMUXCP_TRIM_BUMP0P5XHI_MASK 0x80UL /**< Bit mask for AMUXCP_BUMP0P5XHI */
#define _AMUXCP_TRIM_BUMP0P5XHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BUMP0P5XHI_DEFAULT (_AMUXCP_TRIM_BUMP0P5XHI_DEFAULT << 7) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BIAS2XLO (0x1UL << 8) /**< Bias 2x Low Power */
#define _AMUXCP_TRIM_BIAS2XLO_SHIFT 8 /**< Shift value for AMUXCP_BIAS2XLO */
#define _AMUXCP_TRIM_BIAS2XLO_MASK 0x100UL /**< Bit mask for AMUXCP_BIAS2XLO */
#define _AMUXCP_TRIM_BIAS2XLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BIAS2XLO_DEFAULT (_AMUXCP_TRIM_BIAS2XLO_DEFAULT << 8) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BIAS2XHI (0x1UL << 9) /**< Bias 2x High Power */
#define _AMUXCP_TRIM_BIAS2XHI_SHIFT 9 /**< Shift value for AMUXCP_BIAS2XHI */
#define _AMUXCP_TRIM_BIAS2XHI_MASK 0x200UL /**< Bit mask for AMUXCP_BIAS2XHI */
#define _AMUXCP_TRIM_BIAS2XHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BIAS2XHI_DEFAULT (_AMUXCP_TRIM_BIAS2XHI_DEFAULT << 9) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define _AMUXCP_TRIM_VOLTAGECTRLLO_SHIFT 10 /**< Shift value for AMUXCP_VOLTAGECTRLLO */
#define _AMUXCP_TRIM_VOLTAGECTRLLO_MASK 0xC00UL /**< Bit mask for AMUXCP_VOLTAGECTRLLO */
#define _AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT 0x00000002UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT (_AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT << 10) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define _AMUXCP_TRIM_VOLTAGECTRLHI_SHIFT 13 /**< Shift value for AMUXCP_VOLTAGECTRLHI */
#define _AMUXCP_TRIM_VOLTAGECTRLHI_MASK 0x6000UL /**< Bit mask for AMUXCP_VOLTAGECTRLHI */
#define _AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT 0x00000002UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT (_AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT << 13) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define _AMUXCP_TRIM_BIASCTRLLO_SHIFT 15 /**< Shift value for AMUXCP_BIASCTRLLO */
#define _AMUXCP_TRIM_BIASCTRLLO_MASK 0x38000UL /**< Bit mask for AMUXCP_BIASCTRLLO */
#define _AMUXCP_TRIM_BIASCTRLLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BIASCTRLLO_DEFAULT (_AMUXCP_TRIM_BIASCTRLLO_DEFAULT << 15) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define _AMUXCP_TRIM_BIASCTRLLOCONT_SHIFT 18 /**< Shift value for AMUXCP_BIASCTRLLOCONT */
#define _AMUXCP_TRIM_BIASCTRLLOCONT_MASK 0x1C0000UL /**< Bit mask for AMUXCP_BIASCTRLLOCONT */
#define _AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT (_AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT << 18) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define _AMUXCP_TRIM_BIASCTRLHI_SHIFT 21 /**< Shift value for AMUXCP_BIASCTRLHI */
#define _AMUXCP_TRIM_BIASCTRLHI_MASK 0xE00000UL /**< Bit mask for AMUXCP_BIASCTRLHI */
#define _AMUXCP_TRIM_BIASCTRLHI_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_BIASCTRLHI_DEFAULT (_AMUXCP_TRIM_BIASCTRLHI_DEFAULT << 21) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define _AMUXCP_TRIM_PUMPCAPLO_SHIFT 24 /**< Shift value for AMUXCP_PUMPCAPLO */
#define _AMUXCP_TRIM_PUMPCAPLO_MASK 0x7000000UL /**< Bit mask for AMUXCP_PUMPCAPLO */
#define _AMUXCP_TRIM_PUMPCAPLO_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_PUMPCAPLO_DEFAULT (_AMUXCP_TRIM_PUMPCAPLO_DEFAULT << 24) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
#define _AMUXCP_TRIM_PUMPCAPHI_SHIFT 28 /**< Shift value for AMUXCP_PUMPCAPHI */
#define _AMUXCP_TRIM_PUMPCAPHI_MASK 0x70000000UL /**< Bit mask for AMUXCP_PUMPCAPHI */
#define _AMUXCP_TRIM_PUMPCAPHI_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */
#define AMUXCP_TRIM_PUMPCAPHI_DEFAULT (_AMUXCP_TRIM_PUMPCAPHI_DEFAULT << 28) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
/** @} End of group EFR32ZG23_AMUXCP_BitFields */
/** @} End of group EFR32ZG23_AMUXCP */
/** @} End of group Parts */
#endif /* EFR32ZG23_AMUXCP_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 BURAM register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_BURAM_H
#define EFR32ZG23_BURAM_H
#define BURAM_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_BURAM BURAM
* @{
* @brief EFR32ZG23 BURAM Register Declaration.
*****************************************************************************/
/** BURAM RET Register Group Declaration. */
typedef struct {
__IOM uint32_t REG; /**< Retention Register */
} BURAM_RET_TypeDef;
/** BURAM Register Declaration. */
typedef struct {
BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */
uint32_t RESERVED0[992U]; /**< Reserved for future use */
BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */
uint32_t RESERVED1[992U]; /**< Reserved for future use */
BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */
uint32_t RESERVED2[992U]; /**< Reserved for future use */
BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */
} BURAM_TypeDef;
/** @} End of group EFR32ZG23_BURAM */
/**************************************************************************//**
* @addtogroup EFR32ZG23_BURAM
* @{
* @defgroup EFR32ZG23_BURAM_BitFields BURAM Bit Fields
* @{
*****************************************************************************/
/* Bit fields for BURAM RET_REG */
#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */
#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */
#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */
#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */
#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */
#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */
/** @} End of group EFR32ZG23_BURAM_BitFields */
/** @} End of group EFR32ZG23_BURAM */
/** @} End of group Parts */
#endif /* EFR32ZG23_BURAM_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 BURTC register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_BURTC_H
#define EFR32ZG23_BURTC_H
#define BURTC_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_BURTC BURTC
* @{
* @brief EFR32ZG23 BURTC Register Declaration.
*****************************************************************************/
/** BURTC Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP version ID */
__IOM uint32_t EN; /**< Module Enable Register */
__IOM uint32_t CFG; /**< Configuration Register */
__IOM uint32_t CMD; /**< Command Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IOM uint32_t PRECNT; /**< Pre-Counter Value Register */
__IOM uint32_t CNT; /**< Counter Value Register */
__IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
__IOM uint32_t LOCK; /**< Configuration Lock Register */
__IOM uint32_t COMP; /**< Compare Value Register */
uint32_t RESERVED0[1011U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP version ID */
__IOM uint32_t EN_SET; /**< Module Enable Register */
__IOM uint32_t CFG_SET; /**< Configuration Register */
__IOM uint32_t CMD_SET; /**< Command Register */
__IM uint32_t STATUS_SET; /**< Status Register */
__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
__IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */
__IOM uint32_t CNT_SET; /**< Counter Value Register */
__IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */
__IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */
__IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
__IOM uint32_t COMP_SET; /**< Compare Value Register */
uint32_t RESERVED1[1011U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP version ID */
__IOM uint32_t EN_CLR; /**< Module Enable Register */
__IOM uint32_t CFG_CLR; /**< Configuration Register */
__IOM uint32_t CMD_CLR; /**< Command Register */
__IM uint32_t STATUS_CLR; /**< Status Register */
__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
__IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */
__IOM uint32_t CNT_CLR; /**< Counter Value Register */
__IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */
__IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */
__IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
__IOM uint32_t COMP_CLR; /**< Compare Value Register */
uint32_t RESERVED2[1011U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP version ID */
__IOM uint32_t EN_TGL; /**< Module Enable Register */
__IOM uint32_t CFG_TGL; /**< Configuration Register */
__IOM uint32_t CMD_TGL; /**< Command Register */
__IM uint32_t STATUS_TGL; /**< Status Register */
__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
__IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */
__IOM uint32_t CNT_TGL; /**< Counter Value Register */
__IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */
__IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */
__IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
__IOM uint32_t COMP_TGL; /**< Compare Value Register */
} BURTC_TypeDef;
/** @} End of group EFR32ZG23_BURTC */
/**************************************************************************//**
* @addtogroup EFR32ZG23_BURTC
* @{
* @defgroup EFR32ZG23_BURTC_BitFields BURTC Bit Fields
* @{
*****************************************************************************/
/* Bit fields for BURTC IPVERSION */
#define _BURTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for BURTC_IPVERSION */
#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */
#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */
#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */
#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_IPVERSION */
#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */
/* Bit fields for BURTC EN */
#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */
#define _BURTC_EN_MASK 0x00000003UL /**< Mask for BURTC_EN */
#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */
#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */
#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */
#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */
#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */
#define BURTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
#define _BURTC_EN_DISABLING_SHIFT 1 /**< Shift value for BURTC_DISABLING */
#define _BURTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for BURTC_DISABLING */
#define _BURTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */
#define BURTC_EN_DISABLING_DEFAULT (_BURTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EN */
/* Bit fields for BURTC CFG */
#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */
#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */
#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */
#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */
#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */
#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */
#define _BURTC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for BURTC_CFG */
#define _BURTC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for BURTC_CFG */
#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */
#define BURTC_CFG_DEBUGRUN_X0 (_BURTC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for BURTC_CFG */
#define BURTC_CFG_DEBUGRUN_X1 (_BURTC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for BURTC_CFG */
#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */
#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */
#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */
#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */
#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */
#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */
#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */
#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */
#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */
#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */
#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */
#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */
#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */
/* Bit fields for BURTC CMD */
#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */
#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */
#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */
#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */
#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */
#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */
#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */
#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */
#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */
#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */
#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */
#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */
/* Bit fields for BURTC STATUS */
#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */
#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */
#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */
#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */
#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */
#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */
#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */
#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */
#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */
#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */
#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */
#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */
#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */
#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */
#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */
#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */
/* Bit fields for BURTC IF */
#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */
#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */
#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */
#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */
#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */
#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */
#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */
#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */
#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */
#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */
/* Bit fields for BURTC IEN */
#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */
#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */
#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */
#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */
#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */
#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */
#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */
#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */
#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */
#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */
/* Bit fields for BURTC PRECNT */
#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */
#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */
#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */
#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */
#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */
#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */
/* Bit fields for BURTC CNT */
#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */
#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */
#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */
#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */
#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */
#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */
/* Bit fields for BURTC EM4WUEN */
#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */
#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */
#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */
#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */
#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */
#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */
#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */
#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */
#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */
#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */
#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */
#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */
/* Bit fields for BURTC SYNCBUSY */
#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */
#define _BURTC_SYNCBUSY_MASK 0x0000001FUL /**< Mask for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */
#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */
#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */
#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */
#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */
#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */
#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */
#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */
#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */
#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */
#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */
#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */
#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */
#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */
#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */
#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
/* Bit fields for BURTC LOCK */
#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */
#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */
#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */
#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */
/* Bit fields for BURTC COMP */
#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */
#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */
#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */
#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */
#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */
#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */
/** @} End of group EFR32ZG23_BURTC_BitFields */
/** @} End of group EFR32ZG23_BURTC */
/** @} End of group Parts */
#endif /* EFR32ZG23_BURTC_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 DCDC register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_DCDC_H
#define EFR32ZG23_DCDC_H
#define DCDC_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_DCDC DCDC
* @{
* @brief EFR32ZG23 DCDC Register Declaration.
*****************************************************************************/
/** DCDC Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IPVERSION */
__IOM uint32_t CTRL; /**< Control */
__IOM uint32_t EM01CTRL0; /**< EM01 Control */
uint32_t RESERVED0[1U]; /**< Reserved for future use */
__IOM uint32_t EM23CTRL0; /**< EM23 Control */
uint32_t RESERVED1[3U]; /**< Reserved for future use */
__IOM uint32_t PFMXCTRL; /**< PFMX Control Register */
uint32_t RESERVED2[1U]; /**< Reserved for future use */
__IOM uint32_t IF; /**< Interrupt Flags */
__IOM uint32_t IEN; /**< Interrupt Enable */
__IM uint32_t STATUS; /**< Status Register */
__IM uint32_t SYNCBUSY; /**< Syncbusy Status Register */
uint32_t RESERVED3[2U]; /**< Reserved for future use */
__IOM uint32_t LOCK; /**< Lock Register */
__IM uint32_t LOCKSTATUS; /**< Lock Status Register */
uint32_t RESERVED4[2U]; /**< Reserved for future use */
uint32_t RESERVED5[1U]; /**< Reserved for future use */
uint32_t RESERVED6[7U]; /**< Reserved for future use */
uint32_t RESERVED7[1U]; /**< Reserved for future use */
uint32_t RESERVED8[7U]; /**< Reserved for future use */
uint32_t RESERVED9[1U]; /**< Reserved for future use */
uint32_t RESERVED10[987U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IPVERSION */
__IOM uint32_t CTRL_SET; /**< Control */
__IOM uint32_t EM01CTRL0_SET; /**< EM01 Control */
uint32_t RESERVED11[1U]; /**< Reserved for future use */
__IOM uint32_t EM23CTRL0_SET; /**< EM23 Control */
uint32_t RESERVED12[3U]; /**< Reserved for future use */
__IOM uint32_t PFMXCTRL_SET; /**< PFMX Control Register */
uint32_t RESERVED13[1U]; /**< Reserved for future use */
__IOM uint32_t IF_SET; /**< Interrupt Flags */
__IOM uint32_t IEN_SET; /**< Interrupt Enable */
__IM uint32_t STATUS_SET; /**< Status Register */
__IM uint32_t SYNCBUSY_SET; /**< Syncbusy Status Register */
uint32_t RESERVED14[2U]; /**< Reserved for future use */
__IOM uint32_t LOCK_SET; /**< Lock Register */
__IM uint32_t LOCKSTATUS_SET; /**< Lock Status Register */
uint32_t RESERVED15[2U]; /**< Reserved for future use */
uint32_t RESERVED16[1U]; /**< Reserved for future use */
uint32_t RESERVED17[7U]; /**< Reserved for future use */
uint32_t RESERVED18[1U]; /**< Reserved for future use */
uint32_t RESERVED19[7U]; /**< Reserved for future use */
uint32_t RESERVED20[1U]; /**< Reserved for future use */
uint32_t RESERVED21[987U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IPVERSION */
__IOM uint32_t CTRL_CLR; /**< Control */
__IOM uint32_t EM01CTRL0_CLR; /**< EM01 Control */
uint32_t RESERVED22[1U]; /**< Reserved for future use */
__IOM uint32_t EM23CTRL0_CLR; /**< EM23 Control */
uint32_t RESERVED23[3U]; /**< Reserved for future use */
__IOM uint32_t PFMXCTRL_CLR; /**< PFMX Control Register */
uint32_t RESERVED24[1U]; /**< Reserved for future use */
__IOM uint32_t IF_CLR; /**< Interrupt Flags */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable */
__IM uint32_t STATUS_CLR; /**< Status Register */
__IM uint32_t SYNCBUSY_CLR; /**< Syncbusy Status Register */
uint32_t RESERVED25[2U]; /**< Reserved for future use */
__IOM uint32_t LOCK_CLR; /**< Lock Register */
__IM uint32_t LOCKSTATUS_CLR; /**< Lock Status Register */
uint32_t RESERVED26[2U]; /**< Reserved for future use */
uint32_t RESERVED27[1U]; /**< Reserved for future use */
uint32_t RESERVED28[7U]; /**< Reserved for future use */
uint32_t RESERVED29[1U]; /**< Reserved for future use */
uint32_t RESERVED30[7U]; /**< Reserved for future use */
uint32_t RESERVED31[1U]; /**< Reserved for future use */
uint32_t RESERVED32[987U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IPVERSION */
__IOM uint32_t CTRL_TGL; /**< Control */
__IOM uint32_t EM01CTRL0_TGL; /**< EM01 Control */
uint32_t RESERVED33[1U]; /**< Reserved for future use */
__IOM uint32_t EM23CTRL0_TGL; /**< EM23 Control */
uint32_t RESERVED34[3U]; /**< Reserved for future use */
__IOM uint32_t PFMXCTRL_TGL; /**< PFMX Control Register */
uint32_t RESERVED35[1U]; /**< Reserved for future use */
__IOM uint32_t IF_TGL; /**< Interrupt Flags */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable */
__IM uint32_t STATUS_TGL; /**< Status Register */
__IM uint32_t SYNCBUSY_TGL; /**< Syncbusy Status Register */
uint32_t RESERVED36[2U]; /**< Reserved for future use */
__IOM uint32_t LOCK_TGL; /**< Lock Register */
__IM uint32_t LOCKSTATUS_TGL; /**< Lock Status Register */
uint32_t RESERVED37[2U]; /**< Reserved for future use */
uint32_t RESERVED38[1U]; /**< Reserved for future use */
uint32_t RESERVED39[7U]; /**< Reserved for future use */
uint32_t RESERVED40[1U]; /**< Reserved for future use */
uint32_t RESERVED41[7U]; /**< Reserved for future use */
uint32_t RESERVED42[1U]; /**< Reserved for future use */
} DCDC_TypeDef;
/** @} End of group EFR32ZG23_DCDC */
/**************************************************************************//**
* @addtogroup EFR32ZG23_DCDC
* @{
* @defgroup EFR32ZG23_DCDC_BitFields DCDC Bit Fields
* @{
*****************************************************************************/
/* Bit fields for DCDC IPVERSION */
#define _DCDC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DCDC_IPVERSION */
#define _DCDC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DCDC_IPVERSION */
#define _DCDC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DCDC_IPVERSION */
#define _DCDC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_IPVERSION */
#define _DCDC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_IPVERSION */
#define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */
/* Bit fields for DCDC CTRL */
#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */
#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */
#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */
#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */
#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */
#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */
#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */
#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */
#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */
#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */
#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */
#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */
#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */
#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */
#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */
/* Bit fields for DCDC EM01CTRL0 */
#define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */
#define _DCDC_EM01CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM01CTRL0 */
#define _DCDC_EM01CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */
#define _DCDC_EM01CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */
#define _DCDC_EM01CTRL0_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */
#define _DCDC_EM01CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM01CTRL0 */
#define _DCDC_EM01CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM01CTRL0 */
#define _DCDC_EM01CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM01CTRL0 */
#define _DCDC_EM01CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM01CTRL0 */
#define _DCDC_EM01CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM01CTRL0 */
#define _DCDC_EM01CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM01CTRL0 */
#define _DCDC_EM01CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM01CTRL0 */
#define DCDC_EM01CTRL0_IPKVAL_DEFAULT (_DCDC_EM01CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */
#define DCDC_EM01CTRL0_IPKVAL_Load36mA (_DCDC_EM01CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM01CTRL0 */
#define DCDC_EM01CTRL0_IPKVAL_Load40mA (_DCDC_EM01CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM01CTRL0 */
#define DCDC_EM01CTRL0_IPKVAL_Load44mA (_DCDC_EM01CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM01CTRL0 */
#define DCDC_EM01CTRL0_IPKVAL_Load48mA (_DCDC_EM01CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM01CTRL0 */
#define DCDC_EM01CTRL0_IPKVAL_Load52mA (_DCDC_EM01CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM01CTRL0 */
#define DCDC_EM01CTRL0_IPKVAL_Load56mA (_DCDC_EM01CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM01CTRL0 */
#define DCDC_EM01CTRL0_IPKVAL_Load60mA (_DCDC_EM01CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM01CTRL0 */
#define _DCDC_EM01CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */
#define _DCDC_EM01CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */
#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */
#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM01CTRL0 */
#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM01CTRL0 */
#define _DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM01CTRL0 */
#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM01CTRL0 */
#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */
#define DCDC_EM01CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM01CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM01CTRL0 */
#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM01CTRL0*/
#define DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM01CTRL0*/
#define DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM01CTRL0*/
/* Bit fields for DCDC EM23CTRL0 */
#define _DCDC_EM23CTRL0_RESETVALUE 0x00000103UL /**< Default value for DCDC_EM23CTRL0 */
#define _DCDC_EM23CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM23CTRL0 */
#define _DCDC_EM23CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */
#define _DCDC_EM23CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */
#define _DCDC_EM23CTRL0_IPKVAL_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */
#define _DCDC_EM23CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM23CTRL0 */
#define _DCDC_EM23CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM23CTRL0 */
#define _DCDC_EM23CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM23CTRL0 */
#define _DCDC_EM23CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM23CTRL0 */
#define _DCDC_EM23CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM23CTRL0 */
#define _DCDC_EM23CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM23CTRL0 */
#define _DCDC_EM23CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM23CTRL0 */
#define DCDC_EM23CTRL0_IPKVAL_DEFAULT (_DCDC_EM23CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */
#define DCDC_EM23CTRL0_IPKVAL_Load36mA (_DCDC_EM23CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM23CTRL0 */
#define DCDC_EM23CTRL0_IPKVAL_Load40mA (_DCDC_EM23CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM23CTRL0 */
#define DCDC_EM23CTRL0_IPKVAL_Load44mA (_DCDC_EM23CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM23CTRL0 */
#define DCDC_EM23CTRL0_IPKVAL_Load48mA (_DCDC_EM23CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM23CTRL0 */
#define DCDC_EM23CTRL0_IPKVAL_Load52mA (_DCDC_EM23CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM23CTRL0 */
#define DCDC_EM23CTRL0_IPKVAL_Load56mA (_DCDC_EM23CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM23CTRL0 */
#define DCDC_EM23CTRL0_IPKVAL_Load60mA (_DCDC_EM23CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM23CTRL0 */
#define _DCDC_EM23CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */
#define _DCDC_EM23CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */
#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */
#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM23CTRL0 */
#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM23CTRL0 */
#define _DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM23CTRL0 */
#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM23CTRL0 */
#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */
#define DCDC_EM23CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM23CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM23CTRL0 */
#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM23CTRL0*/
#define DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM23CTRL0*/
#define DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM23CTRL0*/
/* Bit fields for DCDC PFMXCTRL */
#define _DCDC_PFMXCTRL_RESETVALUE 0x00000B0CUL /**< Default value for DCDC_PFMXCTRL */
#define _DCDC_PFMXCTRL_MASK 0x00001F0FUL /**< Mask for DCDC_PFMXCTRL */
#define _DCDC_PFMXCTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */
#define _DCDC_PFMXCTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */
#define _DCDC_PFMXCTRL_IPKVAL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_PFMXCTRL */
#define DCDC_PFMXCTRL_IPKVAL_DEFAULT (_DCDC_PFMXCTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */
#define _DCDC_PFMXCTRL_IPKTMAXCTRL_SHIFT 8 /**< Shift value for DCDC_IPKTMAXCTRL */
#define _DCDC_PFMXCTRL_IPKTMAXCTRL_MASK 0x1F00UL /**< Bit mask for DCDC_IPKTMAXCTRL */
#define _DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DCDC_PFMXCTRL */
#define DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT (_DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */
/* Bit fields for DCDC IF */
#define _DCDC_IF_RESETVALUE 0x00000000UL /**< Default value for DCDC_IF */
#define _DCDC_IF_MASK 0x000003FFUL /**< Mask for DCDC_IF */
#define DCDC_IF_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled */
#define _DCDC_IF_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */
#define _DCDC_IF_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */
#define _DCDC_IF_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
#define DCDC_IF_BYPSW_DEFAULT (_DCDC_IF_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IF */
#define DCDC_IF_WARM (0x1UL << 1) /**< DCDC Warmup Time Done */
#define _DCDC_IF_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */
#define _DCDC_IF_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */
#define _DCDC_IF_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
#define DCDC_IF_WARM_DEFAULT (_DCDC_IF_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IF */
#define DCDC_IF_RUNNING (0x1UL << 2) /**< DCDC Running */
#define _DCDC_IF_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */
#define _DCDC_IF_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */
#define _DCDC_IF_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
#define DCDC_IF_RUNNING_DEFAULT (_DCDC_IF_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IF */
#define DCDC_IF_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold */
#define _DCDC_IF_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */
#define _DCDC_IF_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */
#define _DCDC_IF_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
#define DCDC_IF_VREGINLOW_DEFAULT (_DCDC_IF_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IF */
#define DCDC_IF_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold */
#define _DCDC_IF_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */
#define _DCDC_IF_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */
#define _DCDC_IF_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
#define DCDC_IF_VREGINHIGH_DEFAULT (_DCDC_IF_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IF */
#define DCDC_IF_REGULATION (0x1UL << 5) /**< DCDC in regulation */
#define _DCDC_IF_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */
#define _DCDC_IF_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */
#define _DCDC_IF_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
#define DCDC_IF_REGULATION_DEFAULT (_DCDC_IF_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IF */
#define DCDC_IF_TMAX (0x1UL << 6) /**< Ton_max Timeout Reached */
#define _DCDC_IF_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */
#define _DCDC_IF_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */
#define _DCDC_IF_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
#define DCDC_IF_TMAX_DEFAULT (_DCDC_IF_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IF */
#define DCDC_IF_EM4ERR (0x1UL << 7) /**< EM4 Entry Request Error */
#define _DCDC_IF_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */
#define _DCDC_IF_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */
#define _DCDC_IF_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
#define DCDC_IF_EM4ERR_DEFAULT (_DCDC_IF_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IF */
#define DCDC_IF_PPMODE (0x1UL << 8) /**< Entered Pulse Pairing mode */
#define _DCDC_IF_PPMODE_SHIFT 8 /**< Shift value for DCDC_PPMODE */
#define _DCDC_IF_PPMODE_MASK 0x100UL /**< Bit mask for DCDC_PPMODE */
#define _DCDC_IF_PPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
#define DCDC_IF_PPMODE_DEFAULT (_DCDC_IF_PPMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_IF */
#define DCDC_IF_PFMXMODE (0x1UL << 9) /**< Entered PFMX mode */
#define _DCDC_IF_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */
#define _DCDC_IF_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */
#define _DCDC_IF_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
#define DCDC_IF_PFMXMODE_DEFAULT (_DCDC_IF_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IF */
/* Bit fields for DCDC IEN */
#define _DCDC_IEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_IEN */
#define _DCDC_IEN_MASK 0x000003FFUL /**< Mask for DCDC_IEN */
#define DCDC_IEN_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled Interrupt Enable */
#define _DCDC_IEN_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */
#define _DCDC_IEN_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */
#define _DCDC_IEN_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_BYPSW_DEFAULT (_DCDC_IEN_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_WARM (0x1UL << 1) /**< DCDC Warmup Time Done Interrupt Enable */
#define _DCDC_IEN_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */
#define _DCDC_IEN_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */
#define _DCDC_IEN_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_WARM_DEFAULT (_DCDC_IEN_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_RUNNING (0x1UL << 2) /**< DCDC Running Interrupt Enable */
#define _DCDC_IEN_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */
#define _DCDC_IEN_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */
#define _DCDC_IEN_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_RUNNING_DEFAULT (_DCDC_IEN_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold Interrupt Enable */
#define _DCDC_IEN_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */
#define _DCDC_IEN_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */
#define _DCDC_IEN_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_VREGINLOW_DEFAULT (_DCDC_IEN_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold Interrupt Enable */
#define _DCDC_IEN_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */
#define _DCDC_IEN_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */
#define _DCDC_IEN_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_VREGINHIGH_DEFAULT (_DCDC_IEN_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_REGULATION (0x1UL << 5) /**< DCDC in Regulation Interrupt Enable */
#define _DCDC_IEN_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */
#define _DCDC_IEN_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */
#define _DCDC_IEN_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_REGULATION_DEFAULT (_DCDC_IEN_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_TMAX (0x1UL << 6) /**< Ton_max Timeout Interrupt Enable */
#define _DCDC_IEN_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */
#define _DCDC_IEN_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */
#define _DCDC_IEN_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_TMAX_DEFAULT (_DCDC_IEN_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_EM4ERR (0x1UL << 7) /**< EM4 Entry Req Interrupt Enable */
#define _DCDC_IEN_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */
#define _DCDC_IEN_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */
#define _DCDC_IEN_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_EM4ERR_DEFAULT (_DCDC_IEN_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_PPMODE (0x1UL << 8) /**< Pulse Pairing Mode Interrupt Enable */
#define _DCDC_IEN_PPMODE_SHIFT 8 /**< Shift value for DCDC_PPMODE */
#define _DCDC_IEN_PPMODE_MASK 0x100UL /**< Bit mask for DCDC_PPMODE */
#define _DCDC_IEN_PPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_PPMODE_DEFAULT (_DCDC_IEN_PPMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_PFMXMODE (0x1UL << 9) /**< PFMX Mode Interrupt Enable */
#define _DCDC_IEN_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */
#define _DCDC_IEN_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */
#define _DCDC_IEN_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
#define DCDC_IEN_PFMXMODE_DEFAULT (_DCDC_IEN_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IEN */
/* Bit fields for DCDC STATUS */
#define _DCDC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_STATUS */
#define _DCDC_STATUS_MASK 0x0000071FUL /**< Mask for DCDC_STATUS */
#define DCDC_STATUS_BYPSW (0x1UL << 0) /**< Bypass Switch is currently enabled */
#define _DCDC_STATUS_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */
#define _DCDC_STATUS_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */
#define _DCDC_STATUS_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */
#define DCDC_STATUS_BYPSW_DEFAULT (_DCDC_STATUS_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_STATUS */
#define DCDC_STATUS_WARM (0x1UL << 1) /**< DCDC Warmup Done */
#define _DCDC_STATUS_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */
#define _DCDC_STATUS_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */
#define _DCDC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */
#define DCDC_STATUS_WARM_DEFAULT (_DCDC_STATUS_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_STATUS */
#define DCDC_STATUS_RUNNING (0x1UL << 2) /**< DCDC is running */
#define _DCDC_STATUS_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */
#define _DCDC_STATUS_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */
#define _DCDC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */
#define DCDC_STATUS_RUNNING_DEFAULT (_DCDC_STATUS_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_STATUS */
#define DCDC_STATUS_VREGIN (0x1UL << 3) /**< VREGIN comparator status */
#define _DCDC_STATUS_VREGIN_SHIFT 3 /**< Shift value for DCDC_VREGIN */
#define _DCDC_STATUS_VREGIN_MASK 0x8UL /**< Bit mask for DCDC_VREGIN */
#define _DCDC_STATUS_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */
#define DCDC_STATUS_VREGIN_DEFAULT (_DCDC_STATUS_VREGIN_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_STATUS */
#define DCDC_STATUS_BYPCMPOUT (0x1UL << 4) /**< Bypass Comparator Output */
#define _DCDC_STATUS_BYPCMPOUT_SHIFT 4 /**< Shift value for DCDC_BYPCMPOUT */
#define _DCDC_STATUS_BYPCMPOUT_MASK 0x10UL /**< Bit mask for DCDC_BYPCMPOUT */
#define _DCDC_STATUS_BYPCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */
#define DCDC_STATUS_BYPCMPOUT_DEFAULT (_DCDC_STATUS_BYPCMPOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_STATUS */
#define DCDC_STATUS_PPMODE (0x1UL << 8) /**< DCDC in pulse-pairing mode */
#define _DCDC_STATUS_PPMODE_SHIFT 8 /**< Shift value for DCDC_PPMODE */
#define _DCDC_STATUS_PPMODE_MASK 0x100UL /**< Bit mask for DCDC_PPMODE */
#define _DCDC_STATUS_PPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */
#define DCDC_STATUS_PPMODE_DEFAULT (_DCDC_STATUS_PPMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_STATUS */
#define DCDC_STATUS_PFMXMODE (0x1UL << 9) /**< DCDC in PFMX mode */
#define _DCDC_STATUS_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */
#define _DCDC_STATUS_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */
#define _DCDC_STATUS_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */
#define DCDC_STATUS_PFMXMODE_DEFAULT (_DCDC_STATUS_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_STATUS */
/* Bit fields for DCDC SYNCBUSY */
#define _DCDC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for DCDC_SYNCBUSY */
#define _DCDC_SYNCBUSY_MASK 0x000000FFUL /**< Mask for DCDC_SYNCBUSY */
#define DCDC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Sync Busy Status */
#define _DCDC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for DCDC_CTRL */
#define _DCDC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for DCDC_CTRL */
#define _DCDC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */
#define DCDC_SYNCBUSY_CTRL_DEFAULT (_DCDC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */
#define DCDC_SYNCBUSY_EM01CTRL0 (0x1UL << 1) /**< EM01CTRL0 Sync Busy Status */
#define _DCDC_SYNCBUSY_EM01CTRL0_SHIFT 1 /**< Shift value for DCDC_EM01CTRL0 */
#define _DCDC_SYNCBUSY_EM01CTRL0_MASK 0x2UL /**< Bit mask for DCDC_EM01CTRL0 */
#define _DCDC_SYNCBUSY_EM01CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */
#define DCDC_SYNCBUSY_EM01CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL0_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */
#define DCDC_SYNCBUSY_EM01CTRL1 (0x1UL << 2) /**< EM01CTRL1 Sync Bust Status */
#define _DCDC_SYNCBUSY_EM01CTRL1_SHIFT 2 /**< Shift value for DCDC_EM01CTRL1 */
#define _DCDC_SYNCBUSY_EM01CTRL1_MASK 0x4UL /**< Bit mask for DCDC_EM01CTRL1 */
#define _DCDC_SYNCBUSY_EM01CTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */
#define DCDC_SYNCBUSY_EM01CTRL1_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL1_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */
#define DCDC_SYNCBUSY_EM23CTRL0 (0x1UL << 3) /**< EM23CTRL0 Sync Busy Status */
#define _DCDC_SYNCBUSY_EM23CTRL0_SHIFT 3 /**< Shift value for DCDC_EM23CTRL0 */
#define _DCDC_SYNCBUSY_EM23CTRL0_MASK 0x8UL /**< Bit mask for DCDC_EM23CTRL0 */
#define _DCDC_SYNCBUSY_EM23CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */
#define DCDC_SYNCBUSY_EM23CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM23CTRL0_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */
#define DCDC_SYNCBUSY_PFMXCTRL (0x1UL << 7) /**< PFMXCTRL Sync Busy Status */
#define _DCDC_SYNCBUSY_PFMXCTRL_SHIFT 7 /**< Shift value for DCDC_PFMXCTRL */
#define _DCDC_SYNCBUSY_PFMXCTRL_MASK 0x80UL /**< Bit mask for DCDC_PFMXCTRL */
#define _DCDC_SYNCBUSY_PFMXCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */
#define DCDC_SYNCBUSY_PFMXCTRL_DEFAULT (_DCDC_SYNCBUSY_PFMXCTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */
/* Bit fields for DCDC LOCK */
#define _DCDC_LOCK_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCK */
#define _DCDC_LOCK_MASK 0x0000FFFFUL /**< Mask for DCDC_LOCK */
#define _DCDC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DCDC_LOCKKEY */
#define _DCDC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DCDC_LOCKKEY */
#define _DCDC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCK */
#define _DCDC_LOCK_LOCKKEY_UNLOCKKEY 0x0000ABCDUL /**< Mode UNLOCKKEY for DCDC_LOCK */
#define DCDC_LOCK_LOCKKEY_DEFAULT (_DCDC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCK */
#define DCDC_LOCK_LOCKKEY_UNLOCKKEY (_DCDC_LOCK_LOCKKEY_UNLOCKKEY << 0) /**< Shifted mode UNLOCKKEY for DCDC_LOCK */
/* Bit fields for DCDC LOCKSTATUS */
#define _DCDC_LOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCKSTATUS */
#define _DCDC_LOCKSTATUS_MASK 0x00000001UL /**< Mask for DCDC_LOCKSTATUS */
#define DCDC_LOCKSTATUS_LOCK (0x1UL << 0) /**< Lock Status */
#define _DCDC_LOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for DCDC_LOCK */
#define _DCDC_LOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for DCDC_LOCK */
#define _DCDC_LOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCKSTATUS */
#define _DCDC_LOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DCDC_LOCKSTATUS */
#define _DCDC_LOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DCDC_LOCKSTATUS */
#define DCDC_LOCKSTATUS_LOCK_DEFAULT (_DCDC_LOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCKSTATUS */
#define DCDC_LOCKSTATUS_LOCK_UNLOCKED (_DCDC_LOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for DCDC_LOCKSTATUS */
#define DCDC_LOCKSTATUS_LOCK_LOCKED (_DCDC_LOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for DCDC_LOCKSTATUS */
/** @} End of group EFR32ZG23_DCDC_BitFields */
/** @} End of group EFR32ZG23_DCDC */
/** @} End of group Parts */
#endif /* EFR32ZG23_DCDC_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 DMA descriptor bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_DMA_DESCRIPTOR_H
#define EFR32ZG23_DMA_DESCRIPTOR_H
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* Treat file as system include file. */
#endif
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup DMA_DESCRIPTOR DMA Descriptor
* @{
*****************************************************************************/
/** DMA_DESCRIPTOR Register Declaration */
typedef struct {
/* Note! Use of double __IOM (volatile) qualifier to ensure that both */
/* pointer and referenced memory are declared volatile. */
__IOM uint32_t CTRL; /**< DMA control register */
__IOM void * __IOM SRC; /**< DMA source address */
__IOM void * __IOM DST; /**< DMA destination address */
__IOM void * __IOM LINK; /**< DMA link address */
} DMA_DESCRIPTOR_TypeDef; /**< @} */
/** @} End of group Parts */
#endif /* EFR32ZG23_DMA_DESCRIPTOR_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 DPLL register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_DPLL_H
#define EFR32ZG23_DPLL_H
#define DPLL_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_DPLL DPLL
* @{
* @brief EFR32ZG23 DPLL Register Declaration.
*****************************************************************************/
/** DPLL Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP Version */
__IOM uint32_t EN; /**< Enable */
__IOM uint32_t CFG; /**< Config */
__IOM uint32_t CFG1; /**< Config1 */
__IOM uint32_t IF; /**< Interrupt Flag */
__IOM uint32_t IEN; /**< Interrupt Enable */
__IM uint32_t STATUS; /**< Status */
uint32_t RESERVED0[2U]; /**< Reserved for future use */
__IOM uint32_t LOCK; /**< Lock */
uint32_t RESERVED1[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP Version */
__IOM uint32_t EN_SET; /**< Enable */
__IOM uint32_t CFG_SET; /**< Config */
__IOM uint32_t CFG1_SET; /**< Config1 */
__IOM uint32_t IF_SET; /**< Interrupt Flag */
__IOM uint32_t IEN_SET; /**< Interrupt Enable */
__IM uint32_t STATUS_SET; /**< Status */
uint32_t RESERVED2[2U]; /**< Reserved for future use */
__IOM uint32_t LOCK_SET; /**< Lock */
uint32_t RESERVED3[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP Version */
__IOM uint32_t EN_CLR; /**< Enable */
__IOM uint32_t CFG_CLR; /**< Config */
__IOM uint32_t CFG1_CLR; /**< Config1 */
__IOM uint32_t IF_CLR; /**< Interrupt Flag */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable */
__IM uint32_t STATUS_CLR; /**< Status */
uint32_t RESERVED4[2U]; /**< Reserved for future use */
__IOM uint32_t LOCK_CLR; /**< Lock */
uint32_t RESERVED5[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP Version */
__IOM uint32_t EN_TGL; /**< Enable */
__IOM uint32_t CFG_TGL; /**< Config */
__IOM uint32_t CFG1_TGL; /**< Config1 */
__IOM uint32_t IF_TGL; /**< Interrupt Flag */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable */
__IM uint32_t STATUS_TGL; /**< Status */
uint32_t RESERVED6[2U]; /**< Reserved for future use */
__IOM uint32_t LOCK_TGL; /**< Lock */
} DPLL_TypeDef;
/** @} End of group EFR32ZG23_DPLL */
/**************************************************************************//**
* @addtogroup EFR32ZG23_DPLL
* @{
* @defgroup EFR32ZG23_DPLL_BitFields DPLL Bit Fields
* @{
*****************************************************************************/
/* Bit fields for DPLL IPVERSION */
#define _DPLL_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DPLL_IPVERSION */
#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */
#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */
#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */
#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DPLL_IPVERSION */
#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */
/* Bit fields for DPLL EN */
#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */
#define _DPLL_EN_MASK 0x00000003UL /**< Mask for DPLL_EN */
#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */
#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */
#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */
#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */
#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */
#define DPLL_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */
#define _DPLL_EN_DISABLING_SHIFT 1 /**< Shift value for DPLL_DISABLING */
#define _DPLL_EN_DISABLING_MASK 0x2UL /**< Bit mask for DPLL_DISABLING */
#define _DPLL_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */
#define DPLL_EN_DISABLING_DEFAULT (_DPLL_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_EN */
/* Bit fields for DPLL CFG */
#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */
#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */
#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */
#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */
#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */
#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */
#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */
#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */
#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */
#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */
#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */
#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */
#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */
#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */
#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */
#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */
#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */
#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */
#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */
#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */
#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */
#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */
#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */
#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */
#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */
#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */
/* Bit fields for DPLL CFG1 */
#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */
#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */
#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */
#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */
#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */
#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */
#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */
#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */
#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */
#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */
/* Bit fields for DPLL IF */
#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */
#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */
#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */
#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */
#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */
#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */
#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */
#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */
#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */
#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */
#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */
#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */
#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */
#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */
#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */
#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */
#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */
/* Bit fields for DPLL IEN */
#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */
#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */
#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */
#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */
#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */
#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */
#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */
#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */
#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */
#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */
#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */
#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */
#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */
#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */
#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */
#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */
#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */
/* Bit fields for DPLL STATUS */
#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */
#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */
#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */
#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */
#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */
#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */
#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */
#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */
#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */
#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */
#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */
#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */
#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */
#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */
#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */
#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */
#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */
#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */
#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */
#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */
#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */
/* Bit fields for DPLL LOCK */
#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */
#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */
#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */
#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */
#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */
#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */
#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */
#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */
/** @} End of group EFR32ZG23_DPLL_BitFields */
/** @} End of group EFR32ZG23_DPLL */
/** @} End of group Parts */
#endif /* EFR32ZG23_DPLL_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 EMU register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_EMU_H
#define EFR32ZG23_EMU_H
#define EMU_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_EMU EMU
* @{
* @brief EFR32ZG23 EMU Register Declaration.
*****************************************************************************/
/** EMU Register Declaration. */
typedef struct {
uint32_t RESERVED0[4U]; /**< Reserved for future use */
__IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */
uint32_t RESERVED1[3U]; /**< Reserved for future use */
__IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */
uint32_t RESERVED2[6U]; /**< Reserved for future use */
__IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */
__IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */
uint32_t RESERVED3[6U]; /**< Reserved for future use */
__IM uint32_t IPVERSION; /**< IP Version */
__IOM uint32_t LOCK; /**< EMU Configuration lock register */
__IOM uint32_t IF; /**< Interrupt Flags */
__IOM uint32_t IEN; /**< Interrupt Enables */
__IOM uint32_t EM4CTRL; /**< EM4 Control */
__IOM uint32_t CMD; /**< EMU Command register */
__IOM uint32_t CTRL; /**< EMU Control register */
__IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */
uint32_t RESERVED4[2U]; /**< Reserved for future use */
__IM uint32_t STATUS; /**< EMU Status register */
__IM uint32_t TEMP; /**< Temperature */
uint32_t RESERVED5[1U]; /**< Reserved for future use */
__IOM uint32_t RSTCTRL; /**< Reset Management Control register */
__IM uint32_t RSTCAUSE; /**< Reset cause */
uint32_t RESERVED6[2U]; /**< Reserved for future use */
__IOM uint32_t DGIF; /**< Interrupt Flags Debug */
__IOM uint32_t DGIEN; /**< Interrupt Enables Debug */
uint32_t RESERVED7[6U]; /**< Reserved for future use */
uint32_t RESERVED8[1U]; /**< Reserved for future use */
uint32_t RESERVED9[15U]; /**< Reserved for future use */
__IOM uint32_t EFPIF; /**< EFP Interrupt Register */
__IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */
uint32_t RESERVED10[14U]; /**< Reserved for future use */
uint32_t RESERVED11[1U]; /**< Reserved for future use */
uint32_t RESERVED12[18U]; /**< Reserved for future use */
uint32_t RESERVED13[1U]; /**< Reserved for future use */
uint32_t RESERVED14[924U]; /**< Reserved for future use */
uint32_t RESERVED15[4U]; /**< Reserved for future use */
__IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */
uint32_t RESERVED16[3U]; /**< Reserved for future use */
__IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */
uint32_t RESERVED17[6U]; /**< Reserved for future use */
__IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */
__IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */
uint32_t RESERVED18[6U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP Version */
__IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */
__IOM uint32_t IF_SET; /**< Interrupt Flags */
__IOM uint32_t IEN_SET; /**< Interrupt Enables */
__IOM uint32_t EM4CTRL_SET; /**< EM4 Control */
__IOM uint32_t CMD_SET; /**< EMU Command register */
__IOM uint32_t CTRL_SET; /**< EMU Control register */
__IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */
uint32_t RESERVED19[2U]; /**< Reserved for future use */
__IM uint32_t STATUS_SET; /**< EMU Status register */
__IM uint32_t TEMP_SET; /**< Temperature */
uint32_t RESERVED20[1U]; /**< Reserved for future use */
__IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */
__IM uint32_t RSTCAUSE_SET; /**< Reset cause */
uint32_t RESERVED21[2U]; /**< Reserved for future use */
__IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */
__IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */
uint32_t RESERVED22[6U]; /**< Reserved for future use */
uint32_t RESERVED23[1U]; /**< Reserved for future use */
uint32_t RESERVED24[15U]; /**< Reserved for future use */
__IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */
__IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */
uint32_t RESERVED25[14U]; /**< Reserved for future use */
uint32_t RESERVED26[1U]; /**< Reserved for future use */
uint32_t RESERVED27[18U]; /**< Reserved for future use */
uint32_t RESERVED28[1U]; /**< Reserved for future use */
uint32_t RESERVED29[924U]; /**< Reserved for future use */
uint32_t RESERVED30[4U]; /**< Reserved for future use */
__IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */
uint32_t RESERVED31[3U]; /**< Reserved for future use */
__IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */
uint32_t RESERVED32[6U]; /**< Reserved for future use */
__IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */
__IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */
uint32_t RESERVED33[6U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP Version */
__IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */
__IOM uint32_t IF_CLR; /**< Interrupt Flags */
__IOM uint32_t IEN_CLR; /**< Interrupt Enables */
__IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */
__IOM uint32_t CMD_CLR; /**< EMU Command register */
__IOM uint32_t CTRL_CLR; /**< EMU Control register */
__IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */
uint32_t RESERVED34[2U]; /**< Reserved for future use */
__IM uint32_t STATUS_CLR; /**< EMU Status register */
__IM uint32_t TEMP_CLR; /**< Temperature */
uint32_t RESERVED35[1U]; /**< Reserved for future use */
__IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */
__IM uint32_t RSTCAUSE_CLR; /**< Reset cause */
uint32_t RESERVED36[2U]; /**< Reserved for future use */
__IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */
__IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */
uint32_t RESERVED37[6U]; /**< Reserved for future use */
uint32_t RESERVED38[1U]; /**< Reserved for future use */
uint32_t RESERVED39[15U]; /**< Reserved for future use */
__IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */
__IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */
uint32_t RESERVED40[14U]; /**< Reserved for future use */
uint32_t RESERVED41[1U]; /**< Reserved for future use */
uint32_t RESERVED42[18U]; /**< Reserved for future use */
uint32_t RESERVED43[1U]; /**< Reserved for future use */
uint32_t RESERVED44[924U]; /**< Reserved for future use */
uint32_t RESERVED45[4U]; /**< Reserved for future use */
__IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */
uint32_t RESERVED46[3U]; /**< Reserved for future use */
__IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */
uint32_t RESERVED47[6U]; /**< Reserved for future use */
__IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */
__IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */
uint32_t RESERVED48[6U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP Version */
__IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */
__IOM uint32_t IF_TGL; /**< Interrupt Flags */
__IOM uint32_t IEN_TGL; /**< Interrupt Enables */
__IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */
__IOM uint32_t CMD_TGL; /**< EMU Command register */
__IOM uint32_t CTRL_TGL; /**< EMU Control register */
__IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */
uint32_t RESERVED49[2U]; /**< Reserved for future use */
__IM uint32_t STATUS_TGL; /**< EMU Status register */
__IM uint32_t TEMP_TGL; /**< Temperature */
uint32_t RESERVED50[1U]; /**< Reserved for future use */
__IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */
__IM uint32_t RSTCAUSE_TGL; /**< Reset cause */
uint32_t RESERVED51[2U]; /**< Reserved for future use */
__IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */
__IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */
uint32_t RESERVED52[6U]; /**< Reserved for future use */
uint32_t RESERVED53[1U]; /**< Reserved for future use */
uint32_t RESERVED54[15U]; /**< Reserved for future use */
__IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */
__IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */
uint32_t RESERVED55[14U]; /**< Reserved for future use */
uint32_t RESERVED56[1U]; /**< Reserved for future use */
uint32_t RESERVED57[18U]; /**< Reserved for future use */
uint32_t RESERVED58[1U]; /**< Reserved for future use */
} EMU_TypeDef;
/** @} End of group EFR32ZG23_EMU */
/**************************************************************************//**
* @addtogroup EFR32ZG23_EMU
* @{
* @defgroup EFR32ZG23_EMU_BitFields EMU Bit Fields
* @{
*****************************************************************************/
/* Bit fields for EMU DECBOD */
#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */
#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */
#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */
#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */
#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */
#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */
#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */
#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */
#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */
#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */
#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */
#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */
#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */
#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */
#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */
#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */
#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */
#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */
#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */
#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */
#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */
#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */
/* Bit fields for EMU BOD3SENSE */
#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */
#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */
#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */
#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */
#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */
#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */
#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */
#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */
#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */
#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */
#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */
#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */
#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */
#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */
#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */
#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */
#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */
/* Bit fields for EMU VREGVDDCMPCTRL */
#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */
#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */
#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */
#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */
#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */
#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */
#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */
#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */
#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */
#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */
#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */
/* Bit fields for EMU PD1PARETCTRL */
#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */
#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */
#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */
#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */
#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */
#define _EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN 0x00000001UL /**< Mode PERIPHNORETAIN for EMU_PD1PARETCTRL */
#define _EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN 0x00000002UL /**< Mode RADIONORETAIN for EMU_PD1PARETCTRL */
#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */
#define EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN << 0) /**< Shifted mode PERIPHNORETAIN for EMU_PD1PARETCTRL*/
#define EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN << 0) /**< Shifted mode RADIONORETAIN for EMU_PD1PARETCTRL*/
/* Bit fields for EMU IPVERSION */
#define _EMU_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for EMU_IPVERSION */
#define _EMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EMU_IPVERSION */
#define _EMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EMU_IPVERSION */
#define _EMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_IPVERSION */
#define _EMU_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_IPVERSION */
#define EMU_IPVERSION_IPVERSION_DEFAULT (_EMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IPVERSION */
/* Bit fields for EMU LOCK */
#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */
#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
/* Bit fields for EMU IF */
#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */
#define _EMU_IF_MASK 0xEB070000UL /**< Mask for EMU_IF */
#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */
#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */
#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */
#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */
#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */
#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */
#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */
#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */
#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */
#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */
#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */
#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */
#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */
#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */
#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */
#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */
#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */
#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */
#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */
#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */
#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */
#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */
#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */
#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */
/* Bit fields for EMU IEN */
#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */
#define _EMU_IEN_MASK 0xEB070000UL /**< Mask for EMU_IEN */
#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */
#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */
#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */
#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */
#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */
#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */
#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */
#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */
#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */
#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */
#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */
#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */
#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */
#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */
#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */
#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */
#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */
#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */
#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */
#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */
#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */
#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */
#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */
#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */
/* Bit fields for EMU EM4CTRL */
#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */
#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */
#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */
#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */
#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */
#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */
#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */
#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */
#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */
#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */
#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */
#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */
#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */
#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */
#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */
#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
/* Bit fields for EMU CMD */
#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */
#define _EMU_CMD_MASK 0x00060E12UL /**< Mask for EMU_CMD */
#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */
#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */
#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */
#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */
#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */
#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */
#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */
#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */
#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */
#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */
#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */
#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */
#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */
#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */
#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */
#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */
#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */
#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */
#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */
#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */
/* Bit fields for EMU CTRL */
#define _EMU_CTRL_RESETVALUE 0x00000200UL /**< Default value for EMU_CTRL */
#define _EMU_CTRL_MASK 0xE0010309UL /**< Mask for EMU_CTRL */
#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */
#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */
#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */
#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */
#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */
#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */
#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */
#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */
#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */
#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */
#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */
#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */
#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */
#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */
#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */
#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */
#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */
#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */
#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */
#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */
#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */
#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */
#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */
#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */
#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */
#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */
#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */
#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */
#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */
#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */
#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */
#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */
/* Bit fields for EMU TEMPLIMITS */
#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */
#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */
#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */
#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */
#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */
#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */
#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */
#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
/* Bit fields for EMU STATUS */
#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */
#define _EMU_STATUS_MASK 0xFFFFD4FFUL /**< Mask for EMU_STATUS */
#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */
#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */
#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */
#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */
#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */
#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */
#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */
#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */
#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */
#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */
#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */
#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */
#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */
#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */
#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */
#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */
#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */
#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */
#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */
#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */
#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */
#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */
#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */
#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */
#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */
#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */
#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */
#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */
#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */
#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */
#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */
#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */
#define EMU_STATUS_RACACTIVE (0x1UL << 10) /**< RAC active */
#define _EMU_STATUS_RACACTIVE_SHIFT 10 /**< Shift value for EMU_RACACTIVE */
#define _EMU_STATUS_RACACTIVE_MASK 0x400UL /**< Bit mask for EMU_RACACTIVE */
#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_EM4IORET (0x1UL << 12) /**< EM4 IO retention status */
#define _EMU_STATUS_EM4IORET_SHIFT 12 /**< Shift value for EMU_EM4IORET */
#define _EMU_STATUS_EM4IORET_MASK 0x1000UL /**< Bit mask for EMU_EM4IORET */
#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_EM2ENTERED (0x1UL << 14) /**< EM2 entered */
#define _EMU_STATUS_EM2ENTERED_SHIFT 14 /**< Shift value for EMU_EM2ENTERED */
#define _EMU_STATUS_EM2ENTERED_MASK 0x4000UL /**< Bit mask for EMU_EM2ENTERED */
#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_STATUS */
/* Bit fields for EMU TEMP */
#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */
#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */
#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */
#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */
#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */
#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */
#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */
#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */
#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */
#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */
#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */
#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */
#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */
#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */
/* Bit fields for EMU RSTCTRL */
#define _EMU_RSTCTRL_RESETVALUE 0x00060407UL /**< Default value for EMU_RSTCTRL */
#define _EMU_RSTCTRL_MASK 0xC006C5CFUL /**< Mask for EMU_RSTCTRL */
#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */
#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */
#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */
#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */
#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */
#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */
#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */
#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */
#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */
#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */
#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */
#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */
#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */
#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */
#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */
#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */
#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */
#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */
#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */
#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */
#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */
#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */
#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */
#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */
#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */
#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */
#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */
#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */
#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */
#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */
#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */
#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */
#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */
#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */
#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */
#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */
#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */
#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */
/* Bit fields for EMU RSTCAUSE */
#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */
#define _EMU_RSTCAUSE_MASK 0x8006FFFFUL /**< Mask for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */
#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */
#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */
#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */
#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */
#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */
#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */
#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */
#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */
#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */
#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */
#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */
#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_WDOG1 (0x1UL << 4) /**< Watchdog 1 Reset */
#define _EMU_RSTCAUSE_WDOG1_SHIFT 4 /**< Shift value for EMU_WDOG1 */
#define _EMU_RSTCAUSE_WDOG1_MASK 0x10UL /**< Bit mask for EMU_WDOG1 */
#define _EMU_RSTCAUSE_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_WDOG1_DEFAULT (_EMU_RSTCAUSE_WDOG1_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */
#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */
#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */
#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */
#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */
#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */
#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */
#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */
#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */
#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */
#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */
#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */
#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */
#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */
#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */
#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */
#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */
#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */
#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */
#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */
#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */
#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */
#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */
#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */
#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
/* Bit fields for EMU DGIF */
#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */
#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */
#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */
#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */
#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */
#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */
#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */
#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */
#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */
#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */
#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */
#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */
#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */
#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */
#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */
#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */
#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */
#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */
#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */
#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */
#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */
#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */
/* Bit fields for EMU DGIEN */
#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */
#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */
#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */
#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */
#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */
#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */
#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */
#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */
#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */
#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */
#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */
#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */
#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */
#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */
#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */
#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */
#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */
#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */
#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */
#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */
#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */
#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */
/* Bit fields for EMU EFPIF */
#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */
#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */
#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */
#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */
#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */
#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */
#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */
/* Bit fields for EMU EFPIEN */
#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */
#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */
#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */
#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */
#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */
#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */
#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */
/** @} End of group EFR32ZG23_EMU_BitFields */
/** @} End of group EFR32ZG23_EMU */
/** @} End of group Parts */
#endif /* EFR32ZG23_EMU_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 FSRCO register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_FSRCO_H
#define EFR32ZG23_FSRCO_H
#define FSRCO_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_FSRCO FSRCO
* @{
* @brief EFR32ZG23 FSRCO Register Declaration.
*****************************************************************************/
/** FSRCO Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP Version */
uint32_t RESERVED0[1023U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP Version */
uint32_t RESERVED1[1023U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP Version */
uint32_t RESERVED2[1023U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP Version */
} FSRCO_TypeDef;
/** @} End of group EFR32ZG23_FSRCO */
/**************************************************************************//**
* @addtogroup EFR32ZG23_FSRCO
* @{
* @defgroup EFR32ZG23_FSRCO_BitFields FSRCO Bit Fields
* @{
*****************************************************************************/
/* Bit fields for FSRCO IPVERSION */
#define _FSRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for FSRCO_IPVERSION */
#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */
#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */
#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */
#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for FSRCO_IPVERSION */
#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */
/** @} End of group EFR32ZG23_FSRCO_BitFields */
/** @} End of group EFR32ZG23_FSRCO */
/** @} End of group Parts */
#endif /* EFR32ZG23_FSRCO_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 GPCRC register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_GPCRC_H
#define EFR32ZG23_GPCRC_H
#define GPCRC_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_GPCRC GPCRC
* @{
* @brief EFR32ZG23 GPCRC Register Declaration.
*****************************************************************************/
/** GPCRC Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP Version ID */
__IOM uint32_t EN; /**< CRC Enable */
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
__IOM uint32_t INIT; /**< CRC Init Value */
__IOM uint32_t POLY; /**< CRC Polynomial Value */
__IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */
__IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */
__IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */
__IM uint32_t DATA; /**< CRC Data Register */
__IM uint32_t DATAREV; /**< CRC Data Reverse Register */
__IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */
uint32_t RESERVED0[1012U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP Version ID */
__IOM uint32_t EN_SET; /**< CRC Enable */
__IOM uint32_t CTRL_SET; /**< Control Register */
__IOM uint32_t CMD_SET; /**< Command Register */
__IOM uint32_t INIT_SET; /**< CRC Init Value */
__IOM uint32_t POLY_SET; /**< CRC Polynomial Value */
__IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */
__IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */
__IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */
__IM uint32_t DATA_SET; /**< CRC Data Register */
__IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */
__IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */
uint32_t RESERVED1[1012U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP Version ID */
__IOM uint32_t EN_CLR; /**< CRC Enable */
__IOM uint32_t CTRL_CLR; /**< Control Register */
__IOM uint32_t CMD_CLR; /**< Command Register */
__IOM uint32_t INIT_CLR; /**< CRC Init Value */
__IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */
__IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */
__IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */
__IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */
__IM uint32_t DATA_CLR; /**< CRC Data Register */
__IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */
__IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */
uint32_t RESERVED2[1012U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP Version ID */
__IOM uint32_t EN_TGL; /**< CRC Enable */
__IOM uint32_t CTRL_TGL; /**< Control Register */
__IOM uint32_t CMD_TGL; /**< Command Register */
__IOM uint32_t INIT_TGL; /**< CRC Init Value */
__IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */
__IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */
__IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */
__IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */
__IM uint32_t DATA_TGL; /**< CRC Data Register */
__IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */
__IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */
} GPCRC_TypeDef;
/** @} End of group EFR32ZG23_GPCRC */
/**************************************************************************//**
* @addtogroup EFR32ZG23_GPCRC
* @{
* @defgroup EFR32ZG23_GPCRC_BitFields GPCRC Bit Fields
* @{
*****************************************************************************/
/* Bit fields for GPCRC IPVERSION */
#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */
#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */
#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */
#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */
#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */
#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */
/* Bit fields for GPCRC EN */
#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */
#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */
#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */
#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */
#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */
#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */
#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */
#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */
#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */
#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */
#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */
/* Bit fields for GPCRC CTRL */
#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */
#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */
#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */
#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */
#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */
#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */
#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */
#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */
#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */
#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */
#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */
#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */
#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */
#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */
#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */
#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */
#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */
#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */
#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */
#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */
#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */
#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */
#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */
#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */
#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */
#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */
#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */
#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */
#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */
#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */
/* Bit fields for GPCRC CMD */
#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */
#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */
#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */
#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */
#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */
#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */
/* Bit fields for GPCRC INIT */
#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */
#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */
#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */
#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */
#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */
/* Bit fields for GPCRC POLY */
#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */
#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */
#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */
#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */
#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */
#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */
/* Bit fields for GPCRC INPUTDATA */
#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */
#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */
#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */
#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */
#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */
#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */
/* Bit fields for GPCRC INPUTDATAHWORD */
#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */
#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */
#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */
#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */
#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */
#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/
/* Bit fields for GPCRC INPUTDATABYTE */
#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */
#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */
#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */
#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */
#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */
#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/
/* Bit fields for GPCRC DATA */
#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */
#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */
#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */
#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */
#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */
#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */
/* Bit fields for GPCRC DATAREV */
#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */
#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */
#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */
#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */
#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */
#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */
/* Bit fields for GPCRC DATABYTEREV */
#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */
#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */
#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */
#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */
#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */
#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */
/** @} End of group EFR32ZG23_GPCRC_BitFields */
/** @} End of group EFR32ZG23_GPCRC */
/** @} End of group Parts */
#endif /* EFR32ZG23_GPCRC_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 GPIO Port register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef GPIO_PORT_H
#define GPIO_PORT_H
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief EFR32ZG23 GPIO PORT
*****************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< Port control */
__IOM uint32_t MODEL; /**< mode low */
uint32_t RESERVED0[1]; /**< Reserved for future use */
__IOM uint32_t MODEH; /**< mode high */
__IOM uint32_t DOUT; /**< data out */
__IM uint32_t DIN; /**< data in */
uint32_t RESERVED1[6]; /**< Reserved for future use */
} GPIO_PORT_TypeDef;
/* Bit fields for GPIO_P CTRL */
#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */
#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */
#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */
#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */
#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */
#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */
#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */
#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */
#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */
#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */
#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */
#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */
#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */
#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */
#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
/* Bit fields for GPIO_P MODEL */
#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */
#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */
#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */
#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */
#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */
#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */
#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */
#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */
#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */
#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */
#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */
#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */
#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */
#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */
#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */
#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */
#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
/* Bit fields for GPIO_P MODEH */
#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MASK 0x00000FFFUL /**< Mask for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */
#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */
#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/
#define _GPIO_P_MODEH_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */
#define _GPIO_P_MODEH_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */
#define _GPIO_P_MODEH_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE1_DEFAULT (_GPIO_P_MODEH_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE1_DISABLED (_GPIO_P_MODEH_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE1_INPUT (_GPIO_P_MODEH_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE1_INPUTPULL (_GPIO_P_MODEH_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE1_INPUTPULLFILTER (_GPIO_P_MODEH_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE1_PUSHPULL (_GPIO_P_MODEH_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE1_PUSHPULLALT (_GPIO_P_MODEH_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE1_WIREDOR (_GPIO_P_MODEH_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE1_WIREDAND (_GPIO_P_MODEH_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE1_WIREDANDFILTER (_GPIO_P_MODEH_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE1_WIREDANDPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE1_WIREDANDALT (_GPIO_P_MODEH_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/
#define _GPIO_P_MODEH_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */
#define _GPIO_P_MODEH_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */
#define _GPIO_P_MODEH_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
#define _GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE2_DEFAULT (_GPIO_P_MODEH_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE2_DISABLED (_GPIO_P_MODEH_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE2_INPUT (_GPIO_P_MODEH_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE2_INPUTPULL (_GPIO_P_MODEH_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE2_INPUTPULLFILTER (_GPIO_P_MODEH_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE2_PUSHPULL (_GPIO_P_MODEH_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE2_PUSHPULLALT (_GPIO_P_MODEH_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE2_WIREDOR (_GPIO_P_MODEH_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE2_WIREDAND (_GPIO_P_MODEH_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE2_WIREDANDFILTER (_GPIO_P_MODEH_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE2_WIREDANDPULLUP (_GPIO_P_MODEH_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE2_WIREDANDALT (_GPIO_P_MODEH_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
#define GPIO_P_MODEH_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/
#define GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/
/* Bit fields for GPIO_P DOUT */
#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */
#define _GPIO_P_DOUT_MASK 0x000007FFUL /**< Mask for GPIO_P_DOUT */
#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */
#define _GPIO_P_DOUT_DOUT_MASK 0x7FFUL /**< Bit mask for GPIO_DOUT */
#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */
#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */
/* Bit fields for GPIO_P DIN */
#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */
#define _GPIO_P_DIN_MASK 0x000007FFUL /**< Mask for GPIO_P_DIN */
#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */
#define _GPIO_P_DIN_DIN_MASK 0x7FFUL /**< Bit mask for GPIO_DIN */
#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */
#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */
/** @} End of group Parts */
#endif /* GPIO_PORT_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 HFRCO register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_HFRCO_H
#define EFR32ZG23_HFRCO_H
#define HFRCO_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_HFRCO HFRCO
* @{
* @brief EFR32ZG23 HFRCO Register Declaration.
*****************************************************************************/
/** HFRCO Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP Version ID */
__IOM uint32_t CTRL; /**< Ctrl Register */
__IOM uint32_t CAL; /**< Calibration Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
uint32_t RESERVED0[1U]; /**< Reserved for future use */
__IOM uint32_t LOCK; /**< Lock Register */
uint32_t RESERVED1[1016U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP Version ID */
__IOM uint32_t CTRL_SET; /**< Ctrl Register */
__IOM uint32_t CAL_SET; /**< Calibration Register */
__IM uint32_t STATUS_SET; /**< Status Register */
__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
uint32_t RESERVED2[1U]; /**< Reserved for future use */
__IOM uint32_t LOCK_SET; /**< Lock Register */
uint32_t RESERVED3[1016U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP Version ID */
__IOM uint32_t CTRL_CLR; /**< Ctrl Register */
__IOM uint32_t CAL_CLR; /**< Calibration Register */
__IM uint32_t STATUS_CLR; /**< Status Register */
__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
uint32_t RESERVED4[1U]; /**< Reserved for future use */
__IOM uint32_t LOCK_CLR; /**< Lock Register */
uint32_t RESERVED5[1016U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP Version ID */
__IOM uint32_t CTRL_TGL; /**< Ctrl Register */
__IOM uint32_t CAL_TGL; /**< Calibration Register */
__IM uint32_t STATUS_TGL; /**< Status Register */
__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
uint32_t RESERVED6[1U]; /**< Reserved for future use */
__IOM uint32_t LOCK_TGL; /**< Lock Register */
} HFRCO_TypeDef;
/** @} End of group EFR32ZG23_HFRCO */
/**************************************************************************//**
* @addtogroup EFR32ZG23_HFRCO
* @{
* @defgroup EFR32ZG23_HFRCO_BitFields HFRCO Bit Fields
* @{
*****************************************************************************/
/* Bit fields for HFRCO IPVERSION */
#define _HFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFRCO_IPVERSION */
#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */
#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */
#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */
#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_IPVERSION */
#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */
/* Bit fields for HFRCO CTRL */
#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */
#define _HFRCO_CTRL_MASK 0x00000007UL /**< Mask for HFRCO_CTRL */
#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */
#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */
#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */
#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */
#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */
#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */
#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */
#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */
#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */
#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */
#define HFRCO_CTRL_EM23ONDEMAND (0x1UL << 2) /**< EM23 On-demand */
#define _HFRCO_CTRL_EM23ONDEMAND_SHIFT 2 /**< Shift value for HFRCO_EM23ONDEMAND */
#define _HFRCO_CTRL_EM23ONDEMAND_MASK 0x4UL /**< Bit mask for HFRCO_EM23ONDEMAND */
#define _HFRCO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */
#define HFRCO_CTRL_EM23ONDEMAND_DEFAULT (_HFRCO_CTRL_EM23ONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_CTRL */
/* Bit fields for HFRCO CAL */
#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */
#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */
#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */
#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */
#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */
#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */
#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */
#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */
#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */
#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */
#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */
#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */
#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */
#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */
#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */
#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */
#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */
#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */
#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */
#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */
#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */
#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */
#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */
#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */
#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */
#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */
#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */
#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */
#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */
#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */
#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */
#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */
#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */
#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */
#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */
#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */
#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */
#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */
#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */
#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */
#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */
/* Bit fields for HFRCO STATUS */
#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */
#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */
#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */
#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */
#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */
#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */
#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */
#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */
#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */
#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */
#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */
#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */
#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */
#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */
#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */
#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */
#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */
#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */
#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */
#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */
#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */
#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */
#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */
#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */
#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */
#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */
#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */
#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */
#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */
#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */
#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */
/* Bit fields for HFRCO IF */
#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */
#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */
#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */
#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */
#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */
#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */
#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */
/* Bit fields for HFRCO IEN */
#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */
#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */
#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */
#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */
#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */
#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */
#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */
/* Bit fields for HFRCO LOCK */
#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */
#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */
#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */
#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */
#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */
#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */
#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */
#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */
/** @} End of group EFR32ZG23_HFRCO_BitFields */
/** @} End of group EFR32ZG23_HFRCO */
/** @} End of group Parts */
#endif /* EFR32ZG23_HFRCO_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 HFXO register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_HFXO_H
#define EFR32ZG23_HFXO_H
#define HFXO_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_HFXO HFXO
* @{
* @brief EFR32ZG23 HFXO Register Declaration.
*****************************************************************************/
/** HFXO Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP version ID */
uint32_t RESERVED0[3U]; /**< Reserved for future use */
__IOM uint32_t XTALCFG; /**< Crystal Configuration Register */
uint32_t RESERVED1[1U]; /**< Reserved for future use */
__IOM uint32_t XTALCTRL; /**< Crystal Control Register */
__IOM uint32_t XTALCTRL1; /**< BUFOUT Crystal Control Register */
__IOM uint32_t CFG; /**< Configuration Register */
uint32_t RESERVED2[1U]; /**< Reserved for future use */
__IOM uint32_t CTRL; /**< Control Register */
uint32_t RESERVED3[5U]; /**< Reserved for future use */
__IOM uint32_t BUFOUTTRIM; /**< BUFOUT Trim Configuration Register */
__IOM uint32_t BUFOUTCTRL; /**< BUFOUT Control Register */
uint32_t RESERVED4[2U]; /**< Reserved for future use */
__IOM uint32_t CMD; /**< Command Register */
uint32_t RESERVED5[1U]; /**< Reserved for future use */
__IM uint32_t STATUS; /**< Status Register */
uint32_t RESERVED6[5U]; /**< Reserved for future use */
__IOM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
uint32_t RESERVED7[2U]; /**< Reserved for future use */
__IOM uint32_t LOCK; /**< Configuration Lock Register */
uint32_t RESERVED8[991U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP version ID */
uint32_t RESERVED9[3U]; /**< Reserved for future use */
__IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */
uint32_t RESERVED10[1U]; /**< Reserved for future use */
__IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */
__IOM uint32_t XTALCTRL1_SET; /**< BUFOUT Crystal Control Register */
__IOM uint32_t CFG_SET; /**< Configuration Register */
uint32_t RESERVED11[1U]; /**< Reserved for future use */
__IOM uint32_t CTRL_SET; /**< Control Register */
uint32_t RESERVED12[5U]; /**< Reserved for future use */
__IOM uint32_t BUFOUTTRIM_SET; /**< BUFOUT Trim Configuration Register */
__IOM uint32_t BUFOUTCTRL_SET; /**< BUFOUT Control Register */
uint32_t RESERVED13[2U]; /**< Reserved for future use */
__IOM uint32_t CMD_SET; /**< Command Register */
uint32_t RESERVED14[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_SET; /**< Status Register */
uint32_t RESERVED15[5U]; /**< Reserved for future use */
__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
uint32_t RESERVED16[2U]; /**< Reserved for future use */
__IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
uint32_t RESERVED17[991U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP version ID */
uint32_t RESERVED18[3U]; /**< Reserved for future use */
__IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */
uint32_t RESERVED19[1U]; /**< Reserved for future use */
__IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */
__IOM uint32_t XTALCTRL1_CLR; /**< BUFOUT Crystal Control Register */
__IOM uint32_t CFG_CLR; /**< Configuration Register */
uint32_t RESERVED20[1U]; /**< Reserved for future use */
__IOM uint32_t CTRL_CLR; /**< Control Register */
uint32_t RESERVED21[5U]; /**< Reserved for future use */
__IOM uint32_t BUFOUTTRIM_CLR; /**< BUFOUT Trim Configuration Register */
__IOM uint32_t BUFOUTCTRL_CLR; /**< BUFOUT Control Register */
uint32_t RESERVED22[2U]; /**< Reserved for future use */
__IOM uint32_t CMD_CLR; /**< Command Register */
uint32_t RESERVED23[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_CLR; /**< Status Register */
uint32_t RESERVED24[5U]; /**< Reserved for future use */
__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
uint32_t RESERVED25[2U]; /**< Reserved for future use */
__IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
uint32_t RESERVED26[991U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP version ID */
uint32_t RESERVED27[3U]; /**< Reserved for future use */
__IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */
uint32_t RESERVED28[1U]; /**< Reserved for future use */
__IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */
__IOM uint32_t XTALCTRL1_TGL; /**< BUFOUT Crystal Control Register */
__IOM uint32_t CFG_TGL; /**< Configuration Register */
uint32_t RESERVED29[1U]; /**< Reserved for future use */
__IOM uint32_t CTRL_TGL; /**< Control Register */
uint32_t RESERVED30[5U]; /**< Reserved for future use */
__IOM uint32_t BUFOUTTRIM_TGL; /**< BUFOUT Trim Configuration Register */
__IOM uint32_t BUFOUTCTRL_TGL; /**< BUFOUT Control Register */
uint32_t RESERVED31[2U]; /**< Reserved for future use */
__IOM uint32_t CMD_TGL; /**< Command Register */
uint32_t RESERVED32[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_TGL; /**< Status Register */
uint32_t RESERVED33[5U]; /**< Reserved for future use */
__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
uint32_t RESERVED34[2U]; /**< Reserved for future use */
__IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
} HFXO_TypeDef;
/** @} End of group EFR32ZG23_HFXO */
/**************************************************************************//**
* @addtogroup EFR32ZG23_HFXO
* @{
* @defgroup EFR32ZG23_HFXO_BitFields HFXO Bit Fields
* @{
*****************************************************************************/
/* Bit fields for HFXO IPVERSION */
#define _HFXO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for HFXO_IPVERSION */
#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */
#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */
#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */
#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_IPVERSION */
#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */
/* Bit fields for HFXO XTALCFG */
#define _HFXO_XTALCFG_RESETVALUE 0x0BB00820UL /**< Default value for HFXO_XTALCFG */
#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */
#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */
#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */
#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */
#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */
#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */
#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */
#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */
#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */
#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */
#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */
#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */
#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */
#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */
#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */
#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */
#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4US 0x00000000UL /**< Mode T4US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000001UL /**< Mode T16US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000003UL /**< Mode T83US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000004UL /**< Mode T125US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000005UL /**< Mode T166US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000006UL /**< Mode T208US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000007UL /**< Mode T250US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000008UL /**< Mode T333US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000009UL /**< Mode T416US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x0000000AUL /**< Mode T500US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000BUL /**< Mode T666US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000DUL /**< Mode T1666US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000EUL /**< Mode T2500US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000FUL /**< Mode T4166US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T4US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4US << 20) /**< Shifted mode T4US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */
#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */
#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */
/* Bit fields for HFXO XTALCTRL */
#define _HFXO_XTALCTRL_RESETVALUE 0x033C3C3CUL /**< Default value for HFXO_XTALCTRL */
#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */
#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */
#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */
#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */
#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */
#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */
#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */
#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */
#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */
#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */
#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */
#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */
#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */
#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */
#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */
#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */
#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */
#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */
#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */
#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */
#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */
#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */
#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */
#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */
#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */
#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */
#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */
#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */
/* Bit fields for HFXO XTALCTRL1 */
#define _HFXO_XTALCTRL1_RESETVALUE 0x0000003CUL /**< Default value for HFXO_XTALCTRL1 */
#define _HFXO_XTALCTRL1_MASK 0x000000FFUL /**< Mask for HFXO_XTALCTRL1 */
#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_SHIFT 0 /**< Shift value for HFXO_CTUNEXIBUFOUTANA */
#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_MASK 0xFFUL /**< Bit mask for HFXO_CTUNEXIBUFOUTANA */
#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL1 */
#define HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT (_HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL1 */
/* Bit fields for HFXO CFG */
#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */
#define _HFXO_CFG_MASK 0xB000000FUL /**< Mask for HFXO_CFG */
#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */
#define _HFXO_CFG_MODE_MASK 0x3UL /**< Bit mask for HFXO_MODE */
#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */
#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */
#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */
#define _HFXO_CFG_MODE_EXTCLKPKDET 0x00000002UL /**< Mode EXTCLKPKDET for HFXO_CFG */
#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */
#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */
#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */
#define HFXO_CFG_MODE_EXTCLKPKDET (_HFXO_CFG_MODE_EXTCLKPKDET << 0) /**< Shifted mode EXTCLKPKDET for HFXO_CFG */
#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */
#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */
#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */
#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */
#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */
#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */
#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */
#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */
#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */
#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */
#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */
#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */
#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */
#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */
#define HFXO_CFG_FORCELFTIMEOUT (0x1UL << 28) /**< Force Low Frequency Timeout */
#define _HFXO_CFG_FORCELFTIMEOUT_SHIFT 28 /**< Shift value for HFXO_FORCELFTIMEOUT */
#define _HFXO_CFG_FORCELFTIMEOUT_MASK 0x10000000UL /**< Bit mask for HFXO_FORCELFTIMEOUT */
#define _HFXO_CFG_FORCELFTIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CFG */
#define HFXO_CFG_FORCELFTIMEOUT_DEFAULT (_HFXO_CFG_FORCELFTIMEOUT_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_CFG */
/* Bit fields for HFXO CTRL */
#define _HFXO_CTRL_RESETVALUE 0x07000040UL /**< Default value for HFXO_CTRL */
#define _HFXO_CTRL_MASK 0x8707FF7DUL /**< Mask for HFXO_CTRL */
#define HFXO_CTRL_BUFOUTFREEZE (0x1UL << 0) /**< Freeze BUFOUT Controls */
#define _HFXO_CTRL_BUFOUTFREEZE_SHIFT 0 /**< Shift value for HFXO_BUFOUTFREEZE */
#define _HFXO_CTRL_BUFOUTFREEZE_MASK 0x1UL /**< Bit mask for HFXO_BUFOUTFREEZE */
#define _HFXO_CTRL_BUFOUTFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_BUFOUTFREEZE_DEFAULT (_HFXO_CTRL_BUFOUTFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */
#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */
#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */
#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_EM23ONDEMAND (0x1UL << 3) /**< On-demand During EM23 */
#define _HFXO_CTRL_EM23ONDEMAND_SHIFT 3 /**< Shift value for HFXO_EM23ONDEMAND */
#define _HFXO_CTRL_EM23ONDEMAND_MASK 0x8UL /**< Bit mask for HFXO_EM23ONDEMAND */
#define _HFXO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_EM23ONDEMAND_DEFAULT (_HFXO_CTRL_EM23ONDEMAND_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */
#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */
#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */
#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */
#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */
#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */
#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */
#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */
#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */
#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */
#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */
#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */
#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */
#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */
#define HFXO_CTRL_FORCECTUNEMAX (0x1UL << 6) /**< Force Tuning Cap to Max Value */
#define _HFXO_CTRL_FORCECTUNEMAX_SHIFT 6 /**< Shift value for HFXO_FORCECTUNEMAX */
#define _HFXO_CTRL_FORCECTUNEMAX_MASK 0x40UL /**< Bit mask for HFXO_FORCECTUNEMAX */
#define _HFXO_CTRL_FORCECTUNEMAX_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_FORCECTUNEMAX_DEFAULT (_HFXO_CTRL_FORCECTUNEMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL0_SHIFT 8 /**< Shift value for HFXO_PRSSTATUSSEL0 */
#define _HFXO_CTRL_PRSSTATUSSEL0_MASK 0xF00UL /**< Bit mask for HFXO_PRSSTATUSSEL0 */
#define _HFXO_CTRL_PRSSTATUSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL0_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL0_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL0_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL0_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL0_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL0_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL0_DISABLED (_HFXO_CTRL_PRSSTATUSSEL0_DISABLED << 8) /**< Shifted mode DISABLED for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL0_ENS (_HFXO_CTRL_PRSSTATUSSEL0_ENS << 8) /**< Shifted mode ENS for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY << 8) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL0_RDY (_HFXO_CTRL_PRSSTATUSSEL0_RDY << 8) /**< Shifted mode RDY for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL0_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL0_PRSRDY << 8) /**< Shifted mode PRSRDY for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY << 8) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL0_HWREQ (_HFXO_CTRL_PRSSTATUSSEL0_HWREQ << 8) /**< Shifted mode HWREQ for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ << 8) /**< Shifted mode PRSHWREQ for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ << 8) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL1_SHIFT 12 /**< Shift value for HFXO_PRSSTATUSSEL1 */
#define _HFXO_CTRL_PRSSTATUSSEL1_MASK 0xF000UL /**< Bit mask for HFXO_PRSSTATUSSEL1 */
#define _HFXO_CTRL_PRSSTATUSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL1_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL1_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL1_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL1_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */
#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL1_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL1_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL1_DISABLED (_HFXO_CTRL_PRSSTATUSSEL1_DISABLED << 12) /**< Shifted mode DISABLED for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL1_ENS (_HFXO_CTRL_PRSSTATUSSEL1_ENS << 12) /**< Shifted mode ENS for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY << 12) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL1_RDY (_HFXO_CTRL_PRSSTATUSSEL1_RDY << 12) /**< Shifted mode RDY for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL1_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL1_PRSRDY << 12) /**< Shifted mode PRSRDY for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY << 12) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL1_HWREQ (_HFXO_CTRL_PRSSTATUSSEL1_HWREQ << 12) /**< Shifted mode HWREQ for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ << 12) /**< Shifted mode PRSHWREQ for HFXO_CTRL */
#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ << 12) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */
#define HFXO_CTRL_FORCEEN (0x1UL << 16) /**< Force Digital Clock Request */
#define _HFXO_CTRL_FORCEEN_SHIFT 16 /**< Shift value for HFXO_FORCEEN */
#define _HFXO_CTRL_FORCEEN_MASK 0x10000UL /**< Bit mask for HFXO_FORCEEN */
#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_FORCEENPRS (0x1UL << 17) /**< Force PRS Oscillator Request */
#define _HFXO_CTRL_FORCEENPRS_SHIFT 17 /**< Shift value for HFXO_FORCEENPRS */
#define _HFXO_CTRL_FORCEENPRS_MASK 0x20000UL /**< Bit mask for HFXO_FORCEENPRS */
#define _HFXO_CTRL_FORCEENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_FORCEENPRS_DEFAULT (_HFXO_CTRL_FORCEENPRS_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_FORCEENBUFOUT (0x1UL << 18) /**< Force BUFOUT Request */
#define _HFXO_CTRL_FORCEENBUFOUT_SHIFT 18 /**< Shift value for HFXO_FORCEENBUFOUT */
#define _HFXO_CTRL_FORCEENBUFOUT_MASK 0x40000UL /**< Bit mask for HFXO_FORCEENBUFOUT */
#define _HFXO_CTRL_FORCEENBUFOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_FORCEENBUFOUT_DEFAULT (_HFXO_CTRL_FORCEENBUFOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_DISONDEMAND (0x1UL << 24) /**< Disable On-demand For Digital Clock */
#define _HFXO_CTRL_DISONDEMAND_SHIFT 24 /**< Shift value for HFXO_DISONDEMAND */
#define _HFXO_CTRL_DISONDEMAND_MASK 0x1000000UL /**< Bit mask for HFXO_DISONDEMAND */
#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_DISONDEMANDPRS (0x1UL << 25) /**< Disable On-demand For PRS */
#define _HFXO_CTRL_DISONDEMANDPRS_SHIFT 25 /**< Shift value for HFXO_DISONDEMANDPRS */
#define _HFXO_CTRL_DISONDEMANDPRS_MASK 0x2000000UL /**< Bit mask for HFXO_DISONDEMANDPRS */
#define _HFXO_CTRL_DISONDEMANDPRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_DISONDEMANDPRS_DEFAULT (_HFXO_CTRL_DISONDEMANDPRS_DEFAULT << 25) /**< Shifted mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_DISONDEMANDBUFOUT (0x1UL << 26) /**< Disable On-demand For BUFOUT */
#define _HFXO_CTRL_DISONDEMANDBUFOUT_SHIFT 26 /**< Shift value for HFXO_DISONDEMANDBUFOUT */
#define _HFXO_CTRL_DISONDEMANDBUFOUT_MASK 0x4000000UL /**< Bit mask for HFXO_DISONDEMANDBUFOUT */
#define _HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */
#define HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT (_HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_CTRL */
/* Bit fields for HFXO BUFOUTTRIM */
#define _HFXO_BUFOUTTRIM_RESETVALUE 0x00000008UL /**< Default value for HFXO_BUFOUTTRIM */
#define _HFXO_BUFOUTTRIM_MASK 0x0000000FUL /**< Mask for HFXO_BUFOUTTRIM */
#define _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT 0 /**< Shift value for HFXO_VTRTRIMANA */
#define _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK 0xFUL /**< Bit mask for HFXO_VTRTRIMANA */
#define _HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFXO_BUFOUTTRIM */
#define HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT (_HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTTRIM */
/* Bit fields for HFXO BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_RESETVALUE 0x00643C15UL /**< Default value for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_MASK 0xC0FFFFFFUL /**< Mask for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_XOUTBIASANA_SHIFT 0 /**< Shift value for HFXO_XOUTBIASANA */
#define _HFXO_BUFOUTCTRL_XOUTBIASANA_MASK 0xFUL /**< Bit mask for HFXO_XOUTBIASANA */
#define _HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT 0x00000005UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_XOUTCFANA_SHIFT 4 /**< Shift value for HFXO_XOUTCFANA */
#define _HFXO_BUFOUTCTRL_XOUTCFANA_MASK 0xF0UL /**< Bit mask for HFXO_XOUTCFANA */
#define _HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_XOUTGMANA_SHIFT 8 /**< Shift value for HFXO_XOUTGMANA */
#define _HFXO_BUFOUTCTRL_XOUTGMANA_MASK 0xF00UL /**< Bit mask for HFXO_XOUTGMANA */
#define _HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT 0x0000000CUL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_SHIFT 12 /**< Shift value for HFXO_PEAKDETTHRESANA */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_MASK 0xF000UL /**< Bit mask for HFXO_PEAKDETTHRESANA */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV 0x00000000UL /**< Mode V105MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV 0x00000001UL /**< Mode V132MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV 0x00000002UL /**< Mode V157MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV 0x00000003UL /**< Mode V184MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV 0x00000004UL /**< Mode V210MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV 0x00000005UL /**< Mode V236MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV 0x00000006UL /**< Mode V262MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV 0x00000007UL /**< Mode V289MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV 0x00000008UL /**< Mode V315MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV 0x00000009UL /**< Mode V341MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV 0x0000000AUL /**< Mode V367MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV 0x0000000BUL /**< Mode V394MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV 0x0000000CUL /**< Mode V420MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV 0x0000000DUL /**< Mode V446MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV 0x0000000EUL /**< Mode V472MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV 0x0000000FUL /**< Mode V499MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV << 12) /**< Shifted mode V105MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV << 12) /**< Shifted mode V132MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV << 12) /**< Shifted mode V157MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV << 12) /**< Shifted mode V184MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV << 12) /**< Shifted mode V210MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV << 12) /**< Shifted mode V236MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV << 12) /**< Shifted mode V262MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV << 12) /**< Shifted mode V289MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV << 12) /**< Shifted mode V315MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV << 12) /**< Shifted mode V341MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV << 12) /**< Shifted mode V367MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV << 12) /**< Shifted mode V394MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV << 12) /**< Shifted mode V420MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV << 12) /**< Shifted mode V446MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV << 12) /**< Shifted mode V472MV for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV << 12) /**< Shifted mode V499MV for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_SHIFT 16 /**< Shift value for HFXO_TIMEOUTCTUNE */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_MASK 0xF0000UL /**< Bit mask for HFXO_TIMEOUTCTUNE */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US 0x00000000UL /**< Mode T2US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US 0x00000001UL /**< Mode T5US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US 0x00000002UL /**< Mode T10US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US 0x00000003UL /**< Mode T16US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US 0x00000004UL /**< Mode T21US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US 0x00000005UL /**< Mode T26US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US 0x00000006UL /**< Mode T31US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US 0x00000007UL /**< Mode T42US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US 0x00000008UL /**< Mode T52US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US 0x00000009UL /**< Mode T63US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US 0x0000000AUL /**< Mode T83US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US 0x0000000BUL /**< Mode T104US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US 0x0000000CUL /**< Mode T208US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US 0x0000000DUL /**< Mode T313US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US 0x0000000EUL /**< Mode T521US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US 0x0000000FUL /**< Mode T938US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US << 16) /**< Shifted mode T2US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US << 16) /**< Shifted mode T5US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US << 16) /**< Shifted mode T10US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US << 16) /**< Shifted mode T16US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US << 16) /**< Shifted mode T21US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US << 16) /**< Shifted mode T26US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US << 16) /**< Shifted mode T31US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US << 16) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US << 16) /**< Shifted mode T52US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US << 16) /**< Shifted mode T63US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US << 16) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US << 16) /**< Shifted mode T104US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US << 16) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US << 16) /**< Shifted mode T313US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US << 16) /**< Shifted mode T521US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US << 16) /**< Shifted mode T938US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTARTUP */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTARTUP */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT 0x00000006UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US 0x00000000UL /**< Mode T42US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US 0x00000001UL /**< Mode T83US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US 0x00000002UL /**< Mode T108US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US 0x00000003UL /**< Mode T133US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US 0x00000004UL /**< Mode T158US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US 0x00000005UL /**< Mode T183US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US 0x00000006UL /**< Mode T208US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US 0x00000007UL /**< Mode T233US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US 0x00000008UL /**< Mode T258US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US 0x00000009UL /**< Mode T283US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US 0x0000000AUL /**< Mode T333US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US 0x0000000BUL /**< Mode T375US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US 0x0000000CUL /**< Mode T417US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US 0x0000000DUL /**< Mode T458US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US 0x0000000EUL /**< Mode T500US for HFXO_BUFOUTCTRL */
#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US 0x0000000FUL /**< Mode T667US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US << 20) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US << 20) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US << 20) /**< Shifted mode T108US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US << 20) /**< Shifted mode T133US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US << 20) /**< Shifted mode T158US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US << 20) /**< Shifted mode T183US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US << 20) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US << 20) /**< Shifted mode T233US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US << 20) /**< Shifted mode T258US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US << 20) /**< Shifted mode T283US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US << 20) /**< Shifted mode T333US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US << 20) /**< Shifted mode T375US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US << 20) /**< Shifted mode T417US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US << 20) /**< Shifted mode T458US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US << 20) /**< Shifted mode T500US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US << 20) /**< Shifted mode T667US for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY (0x1UL << 31) /**< Minimum Startup Delay */
#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT 31 /**< Shift value for HFXO_MINIMUMSTARTUPDELAY */
#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK 0x80000000UL /**< Bit mask for HFXO_MINIMUMSTARTUPDELAY */
#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */
#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT (_HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */
/* Bit fields for HFXO CMD */
#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */
#define _HFXO_CMD_MASK 0x00000001UL /**< Mask for HFXO_CMD */
#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */
#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */
#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */
#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */
#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */
/* Bit fields for HFXO STATUS */
#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */
#define _HFXO_STATUS_MASK 0xC03F800FUL /**< Mask for HFXO_STATUS */
#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */
#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */
#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */
#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */
#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */
#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */
#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_PRSRDY (0x1UL << 2) /**< PRS Ready Status */
#define _HFXO_STATUS_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */
#define _HFXO_STATUS_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */
#define _HFXO_STATUS_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_PRSRDY_DEFAULT (_HFXO_STATUS_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Status */
#define _HFXO_STATUS_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */
#define _HFXO_STATUS_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */
#define _HFXO_STATUS_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_BUFOUTRDY_DEFAULT (_HFXO_STATUS_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT Frozen */
#define _HFXO_STATUS_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */
#define _HFXO_STATUS_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */
#define _HFXO_STATUS_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_BUFOUTFROZEN_DEFAULT (_HFXO_STATUS_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */
#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */
#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */
#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Digital Clock */
#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */
#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */
#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */
#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */
#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */
#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_PRSHWREQ (0x1UL << 20) /**< Oscillator Requested by PRS Request */
#define _HFXO_STATUS_PRSHWREQ_SHIFT 20 /**< Shift value for HFXO_PRSHWREQ */
#define _HFXO_STATUS_PRSHWREQ_MASK 0x100000UL /**< Bit mask for HFXO_PRSHWREQ */
#define _HFXO_STATUS_PRSHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_PRSHWREQ_DEFAULT (_HFXO_STATUS_PRSHWREQ_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_BUFOUTHWREQ (0x1UL << 21) /**< Oscillator Requested by BUFOUT Request */
#define _HFXO_STATUS_BUFOUTHWREQ_SHIFT 21 /**< Shift value for HFXO_BUFOUTHWREQ */
#define _HFXO_STATUS_BUFOUTHWREQ_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTHWREQ */
#define _HFXO_STATUS_BUFOUTHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_BUFOUTHWREQ_DEFAULT (_HFXO_STATUS_BUFOUTHWREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_SYNCBUSY (0x1UL << 30) /**< Sync Busy */
#define _HFXO_STATUS_SYNCBUSY_SHIFT 30 /**< Shift value for HFXO_SYNCBUSY */
#define _HFXO_STATUS_SYNCBUSY_MASK 0x40000000UL /**< Bit mask for HFXO_SYNCBUSY */
#define _HFXO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_SYNCBUSY_DEFAULT (_HFXO_STATUS_SYNCBUSY_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */
#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */
#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */
#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */
#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */
#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */
#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */
#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */
/* Bit fields for HFXO IF */
#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */
#define _HFXO_IF_MASK 0xF830800FUL /**< Mask for HFXO_IF */
#define HFXO_IF_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */
#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */
#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */
#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */
#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */
#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */
#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */
#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */
#define HFXO_IF_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */
#define _HFXO_IF_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */
#define _HFXO_IF_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */
#define _HFXO_IF_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
#define HFXO_IF_PRSRDY_DEFAULT (_HFXO_IF_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IF */
#define HFXO_IF_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */
#define _HFXO_IF_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */
#define _HFXO_IF_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */
#define _HFXO_IF_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
#define HFXO_IF_BUFOUTRDY_DEFAULT (_HFXO_IF_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IF */
#define HFXO_IF_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */
#define _HFXO_IF_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */
#define _HFXO_IF_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */
#define _HFXO_IF_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
#define HFXO_IF_BUFOUTFROZEN_DEFAULT (_HFXO_IF_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IF */
#define HFXO_IF_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */
#define _HFXO_IF_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */
#define _HFXO_IF_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */
#define _HFXO_IF_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
#define HFXO_IF_PRSERR_DEFAULT (_HFXO_IF_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IF */
#define HFXO_IF_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */
#define _HFXO_IF_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */
#define _HFXO_IF_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */
#define _HFXO_IF_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
#define HFXO_IF_BUFOUTERR_DEFAULT (_HFXO_IF_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IF */
#define HFXO_IF_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */
#define _HFXO_IF_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */
#define _HFXO_IF_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */
#define _HFXO_IF_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
#define HFXO_IF_BUFOUTFREEZEERR_DEFAULT (_HFXO_IF_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IF */
#define HFXO_IF_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */
#define _HFXO_IF_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */
#define _HFXO_IF_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */
#define _HFXO_IF_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
#define HFXO_IF_BUFOUTDNSERR_DEFAULT (_HFXO_IF_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IF */
#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */
#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */
#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */
#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */
#define HFXO_IF_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */
#define _HFXO_IF_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */
#define _HFXO_IF_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */
#define _HFXO_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
#define HFXO_IF_LFTIMEOUTERR_DEFAULT (_HFXO_IF_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IF */
#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */
#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */
#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */
#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */
/* Bit fields for HFXO IEN */
#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */
#define _HFXO_IEN_MASK 0xF830800FUL /**< Mask for HFXO_IEN */
#define HFXO_IEN_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */
#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */
#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */
#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */
#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */
#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */
#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */
#define _HFXO_IEN_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */
#define _HFXO_IEN_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */
#define _HFXO_IEN_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_PRSRDY_DEFAULT (_HFXO_IEN_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */
#define _HFXO_IEN_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */
#define _HFXO_IEN_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */
#define _HFXO_IEN_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_BUFOUTRDY_DEFAULT (_HFXO_IEN_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */
#define _HFXO_IEN_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */
#define _HFXO_IEN_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */
#define _HFXO_IEN_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_BUFOUTFROZEN_DEFAULT (_HFXO_IEN_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */
#define _HFXO_IEN_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */
#define _HFXO_IEN_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */
#define _HFXO_IEN_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_PRSERR_DEFAULT (_HFXO_IEN_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */
#define _HFXO_IEN_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */
#define _HFXO_IEN_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */
#define _HFXO_IEN_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_BUFOUTERR_DEFAULT (_HFXO_IEN_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */
#define _HFXO_IEN_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */
#define _HFXO_IEN_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */
#define _HFXO_IEN_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_BUFOUTFREEZEERR_DEFAULT (_HFXO_IEN_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */
#define _HFXO_IEN_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */
#define _HFXO_IEN_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */
#define _HFXO_IEN_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_BUFOUTDNSERR_DEFAULT (_HFXO_IEN_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */
#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */
#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */
#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */
#define _HFXO_IEN_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */
#define _HFXO_IEN_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */
#define _HFXO_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_LFTIMEOUTERR_DEFAULT (_HFXO_IEN_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */
#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */
#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */
#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */
/* Bit fields for HFXO LOCK */
#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */
#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */
#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */
#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */
#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */
#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */
#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */
#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */
/** @} End of group EFR32ZG23_HFXO_BitFields */
/** @} End of group EFR32ZG23_HFXO */
/** @} End of group Parts */
#endif /* EFR32ZG23_HFXO_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 I2C register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_I2C_H
#define EFR32ZG23_I2C_H
#define I2C_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_I2C I2C
* @{
* @brief EFR32ZG23 I2C Register Declaration.
*****************************************************************************/
/** I2C Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP VERSION Register */
__IOM uint32_t EN; /**< Enable Register */
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
__IM uint32_t STATE; /**< State Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t CLKDIV; /**< Clock Division Register */
__IOM uint32_t SADDR; /**< Follower Address Register */
__IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */
__IM uint32_t RXDATA; /**< Receive Buffer Data Register */
__IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */
__IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
__IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */
__IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
__IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */
__IOM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
uint32_t RESERVED0[1007U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP VERSION Register */
__IOM uint32_t EN_SET; /**< Enable Register */
__IOM uint32_t CTRL_SET; /**< Control Register */
__IOM uint32_t CMD_SET; /**< Command Register */
__IM uint32_t STATE_SET; /**< State Register */
__IM uint32_t STATUS_SET; /**< Status Register */
__IOM uint32_t CLKDIV_SET; /**< Clock Division Register */
__IOM uint32_t SADDR_SET; /**< Follower Address Register */
__IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */
__IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */
__IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */
__IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */
__IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */
__IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */
__IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */
__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
uint32_t RESERVED1[1007U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */
__IOM uint32_t EN_CLR; /**< Enable Register */
__IOM uint32_t CTRL_CLR; /**< Control Register */
__IOM uint32_t CMD_CLR; /**< Command Register */
__IM uint32_t STATE_CLR; /**< State Register */
__IM uint32_t STATUS_CLR; /**< Status Register */
__IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */
__IOM uint32_t SADDR_CLR; /**< Follower Address Register */
__IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */
__IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */
__IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */
__IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */
__IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */
__IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */
__IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */
__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
uint32_t RESERVED2[1007U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */
__IOM uint32_t EN_TGL; /**< Enable Register */
__IOM uint32_t CTRL_TGL; /**< Control Register */
__IOM uint32_t CMD_TGL; /**< Command Register */
__IM uint32_t STATE_TGL; /**< State Register */
__IM uint32_t STATUS_TGL; /**< Status Register */
__IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */
__IOM uint32_t SADDR_TGL; /**< Follower Address Register */
__IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */
__IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */
__IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */
__IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */
__IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */
__IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */
__IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */
__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
} I2C_TypeDef;
/** @} End of group EFR32ZG23_I2C */
/**************************************************************************//**
* @addtogroup EFR32ZG23_I2C
* @{
* @defgroup EFR32ZG23_I2C_BitFields I2C Bit Fields
* @{
*****************************************************************************/
/* Bit fields for I2C IPVERSION */
#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */
#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */
#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */
#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */
#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */
#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */
/* Bit fields for I2C EN */
#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */
#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */
#define I2C_EN_EN (0x1UL << 0) /**< module enable */
#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */
#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */
#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */
#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */
#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */
#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */
#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */
/* Bit fields for I2C CTRL */
#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */
#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */
#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */
#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */
#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */
#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */
#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */
#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */
#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */
#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */
#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */
#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */
#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */
#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */
#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */
#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */
#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */
#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */
#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */
#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */
#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */
#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */
#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */
#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */
#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */
#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */
#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */
#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */
#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */
#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */
#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */
#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */
#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */
#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */
#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */
#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */
#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */
#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */
#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */
#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */
#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */
#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */
#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */
#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */
#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */
#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */
#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */
#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */
#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */
#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */
#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */
#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */
#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */
#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */
#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */
/* Bit fields for I2C CMD */
#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */
#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */
#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */
#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */
#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
/* Bit fields for I2C STATE */
#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */
#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
/* Bit fields for I2C STATUS */
#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */
#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */
#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */
#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */
#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */
#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */
#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */
#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */
#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */
#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */
/* Bit fields for I2C CLKDIV */
#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
/* Bit fields for I2C SADDR */
#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
/* Bit fields for I2C SADDRMASK */
#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */
#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */
#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
/* Bit fields for I2C RXDATA */
#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
/* Bit fields for I2C RXDOUBLE */
#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */
#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */
#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */
#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */
#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */
#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */
#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
/* Bit fields for I2C RXDATAP */
#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
/* Bit fields for I2C RXDOUBLEP */
#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */
#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */
#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */
#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */
#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */
#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */
#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
/* Bit fields for I2C TXDATA */
#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
/* Bit fields for I2C TXDOUBLE */
#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */
#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */
#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */
#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */
#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */
#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */
#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
/* Bit fields for I2C IF */
#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */
#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */
#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */
#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */
#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */
#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */
#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */
#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */
#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */
#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */
#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */
#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */
#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */
#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */
/* Bit fields for I2C IEN */
#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */
#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */
#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */
#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */
#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */
#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */
#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */
#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */
#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */
#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */
#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */
#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */
#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */
/** @} End of group EFR32ZG23_I2C_BitFields */
/** @} End of group EFR32ZG23_I2C */
/** @} End of group Parts */
#endif /* EFR32ZG23_I2C_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 ICACHE register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_ICACHE_H
#define EFR32ZG23_ICACHE_H
#define ICACHE_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_ICACHE ICACHE
* @{
* @brief EFR32ZG23 ICACHE Register Declaration.
*****************************************************************************/
/** ICACHE Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP Version */
__IOM uint32_t CTRL; /**< Control Register */
__IM uint32_t PCHITS; /**< Performance Counter Hits */
__IM uint32_t PCMISSES; /**< Performance Counter Misses */
__IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t CMD; /**< Command Register */
__IOM uint32_t LPMODE; /**< Low Power Mode */
__IOM uint32_t IF; /**< Interrupt Flag */
__IOM uint32_t IEN; /**< Interrupt Enable */
uint32_t RESERVED0[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP Version */
__IOM uint32_t CTRL_SET; /**< Control Register */
__IM uint32_t PCHITS_SET; /**< Performance Counter Hits */
__IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */
__IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */
__IM uint32_t STATUS_SET; /**< Status Register */
__IOM uint32_t CMD_SET; /**< Command Register */
__IOM uint32_t LPMODE_SET; /**< Low Power Mode */
__IOM uint32_t IF_SET; /**< Interrupt Flag */
__IOM uint32_t IEN_SET; /**< Interrupt Enable */
uint32_t RESERVED1[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP Version */
__IOM uint32_t CTRL_CLR; /**< Control Register */
__IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */
__IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */
__IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */
__IM uint32_t STATUS_CLR; /**< Status Register */
__IOM uint32_t CMD_CLR; /**< Command Register */
__IOM uint32_t LPMODE_CLR; /**< Low Power Mode */
__IOM uint32_t IF_CLR; /**< Interrupt Flag */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable */
uint32_t RESERVED2[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP Version */
__IOM uint32_t CTRL_TGL; /**< Control Register */
__IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */
__IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */
__IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */
__IM uint32_t STATUS_TGL; /**< Status Register */
__IOM uint32_t CMD_TGL; /**< Command Register */
__IOM uint32_t LPMODE_TGL; /**< Low Power Mode */
__IOM uint32_t IF_TGL; /**< Interrupt Flag */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable */
} ICACHE_TypeDef;
/** @} End of group EFR32ZG23_ICACHE */
/**************************************************************************//**
* @addtogroup EFR32ZG23_ICACHE
* @{
* @defgroup EFR32ZG23_ICACHE_BitFields ICACHE Bit Fields
* @{
*****************************************************************************/
/* Bit fields for ICACHE IPVERSION */
#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */
#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */
#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */
#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */
#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */
#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */
/* Bit fields for ICACHE CTRL */
#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */
#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */
#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */
#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */
#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */
#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */
#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */
#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */
#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */
#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */
#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */
#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */
#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */
#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */
#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */
#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */
#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */
/* Bit fields for ICACHE PCHITS */
#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */
#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */
#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */
#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */
#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */
#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */
/* Bit fields for ICACHE PCMISSES */
#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */
#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */
#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */
#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */
#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */
#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */
/* Bit fields for ICACHE PCAHITS */
#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */
#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */
#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */
#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */
#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */
#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */
/* Bit fields for ICACHE STATUS */
#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */
#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */
#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */
#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */
#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */
#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */
#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */
/* Bit fields for ICACHE CMD */
#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */
#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */
#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */
#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */
#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */
#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */
#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */
#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */
#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */
#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */
#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */
#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */
#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */
#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */
#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */
#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */
#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */
/* Bit fields for ICACHE LPMODE */
#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */
#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */
#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */
#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */
#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */
#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */
#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */
#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */
#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */
#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */
#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */
#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */
#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */
#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */
#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */
#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */
/* Bit fields for ICACHE IF */
#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */
#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */
#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */
#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */
#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */
#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */
#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */
#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */
#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */
#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */
#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */
#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */
#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */
#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */
#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */
#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */
#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */
#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */
#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */
#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */
#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */
#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */
/* Bit fields for ICACHE IEN */
#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */
#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */
#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */
#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */
#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */
#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */
#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */
#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */
#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */
#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */
#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */
#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */
#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */
#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */
#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */
#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */
#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */
#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */
#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */
#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */
#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */
#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */
/** @} End of group EFR32ZG23_ICACHE_BitFields */
/** @} End of group EFR32ZG23_ICACHE */
/** @} End of group Parts */
#endif /* EFR32ZG23_ICACHE_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 KEYSCAN register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_KEYSCAN_H
#define EFR32ZG23_KEYSCAN_H
#define KEYSCAN_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_KEYSCAN KEYSCAN
* @{
* @brief EFR32ZG23 KEYSCAN Register Declaration.
*****************************************************************************/
/** KEYSCAN Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IPVERSION */
__IOM uint32_t EN; /**< Enable */
__IOM uint32_t SWRST; /**< Software Reset */
__IOM uint32_t CFG; /**< Config */
__IOM uint32_t CMD; /**< Command */
__IOM uint32_t DELAY; /**< Delay */
__IM uint32_t STATUS; /**< Status */
__IOM uint32_t IF; /**< Interrupt Flags */
__IOM uint32_t IEN; /**< Interrupt Enables */
uint32_t RESERVED0[1015U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IPVERSION */
__IOM uint32_t EN_SET; /**< Enable */
__IOM uint32_t SWRST_SET; /**< Software Reset */
__IOM uint32_t CFG_SET; /**< Config */
__IOM uint32_t CMD_SET; /**< Command */
__IOM uint32_t DELAY_SET; /**< Delay */
__IM uint32_t STATUS_SET; /**< Status */
__IOM uint32_t IF_SET; /**< Interrupt Flags */
__IOM uint32_t IEN_SET; /**< Interrupt Enables */
uint32_t RESERVED1[1015U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IPVERSION */
__IOM uint32_t EN_CLR; /**< Enable */
__IOM uint32_t SWRST_CLR; /**< Software Reset */
__IOM uint32_t CFG_CLR; /**< Config */
__IOM uint32_t CMD_CLR; /**< Command */
__IOM uint32_t DELAY_CLR; /**< Delay */
__IM uint32_t STATUS_CLR; /**< Status */
__IOM uint32_t IF_CLR; /**< Interrupt Flags */
__IOM uint32_t IEN_CLR; /**< Interrupt Enables */
uint32_t RESERVED2[1015U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IPVERSION */
__IOM uint32_t EN_TGL; /**< Enable */
__IOM uint32_t SWRST_TGL; /**< Software Reset */
__IOM uint32_t CFG_TGL; /**< Config */
__IOM uint32_t CMD_TGL; /**< Command */
__IOM uint32_t DELAY_TGL; /**< Delay */
__IM uint32_t STATUS_TGL; /**< Status */
__IOM uint32_t IF_TGL; /**< Interrupt Flags */
__IOM uint32_t IEN_TGL; /**< Interrupt Enables */
} KEYSCAN_TypeDef;
/** @} End of group EFR32ZG23_KEYSCAN */
/**************************************************************************//**
* @addtogroup EFR32ZG23_KEYSCAN
* @{
* @defgroup EFR32ZG23_KEYSCAN_BitFields KEYSCAN Bit Fields
* @{
*****************************************************************************/
/* Bit fields for KEYSCAN IPVERSION */
#define _KEYSCAN_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for KEYSCAN_IPVERSION */
#define _KEYSCAN_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for KEYSCAN_IPVERSION */
#define _KEYSCAN_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for KEYSCAN_IPVERSION */
#define _KEYSCAN_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for KEYSCAN_IPVERSION */
#define _KEYSCAN_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_IPVERSION */
#define KEYSCAN_IPVERSION_IPVERSION_DEFAULT (_KEYSCAN_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IPVERSION */
/* Bit fields for KEYSCAN EN */
#define _KEYSCAN_EN_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_EN */
#define _KEYSCAN_EN_MASK 0x00000003UL /**< Mask for KEYSCAN_EN */
#define KEYSCAN_EN_EN (0x1UL << 0) /**< Enable */
#define _KEYSCAN_EN_EN_SHIFT 0 /**< Shift value for KEYSCAN_EN */
#define _KEYSCAN_EN_EN_MASK 0x1UL /**< Bit mask for KEYSCAN_EN */
#define _KEYSCAN_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_EN */
#define _KEYSCAN_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for KEYSCAN_EN */
#define _KEYSCAN_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for KEYSCAN_EN */
#define KEYSCAN_EN_EN_DEFAULT (_KEYSCAN_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_EN */
#define KEYSCAN_EN_EN_DISABLE (_KEYSCAN_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for KEYSCAN_EN */
#define KEYSCAN_EN_EN_ENABLE (_KEYSCAN_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for KEYSCAN_EN */
#define KEYSCAN_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
#define _KEYSCAN_EN_DISABLING_SHIFT 1 /**< Shift value for KEYSCAN_DISABLING */
#define _KEYSCAN_EN_DISABLING_MASK 0x2UL /**< Bit mask for KEYSCAN_DISABLING */
#define _KEYSCAN_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_EN */
#define KEYSCAN_EN_DISABLING_DEFAULT (_KEYSCAN_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_EN */
/* Bit fields for KEYSCAN SWRST */
#define _KEYSCAN_SWRST_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_SWRST */
#define _KEYSCAN_SWRST_MASK 0x00000003UL /**< Mask for KEYSCAN_SWRST */
#define KEYSCAN_SWRST_SWRST (0x1UL << 0) /**< Software reset command */
#define _KEYSCAN_SWRST_SWRST_SHIFT 0 /**< Shift value for KEYSCAN_SWRST */
#define _KEYSCAN_SWRST_SWRST_MASK 0x1UL /**< Bit mask for KEYSCAN_SWRST */
#define _KEYSCAN_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_SWRST */
#define KEYSCAN_SWRST_SWRST_DEFAULT (_KEYSCAN_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */
#define KEYSCAN_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */
#define _KEYSCAN_SWRST_RESETTING_SHIFT 1 /**< Shift value for KEYSCAN_RESETTING */
#define _KEYSCAN_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for KEYSCAN_RESETTING */
#define _KEYSCAN_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_SWRST */
#define KEYSCAN_SWRST_RESETTING_DEFAULT (_KEYSCAN_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */
/* Bit fields for KEYSCAN CFG */
#define _KEYSCAN_CFG_RESETVALUE 0x2501387FUL /**< Default value for KEYSCAN_CFG */
#define _KEYSCAN_CFG_MASK 0x7753FFFFUL /**< Mask for KEYSCAN_CFG */
#define _KEYSCAN_CFG_CLKDIV_SHIFT 0 /**< Shift value for KEYSCAN_CLKDIV */
#define _KEYSCAN_CFG_CLKDIV_MASK 0x3FFFFUL /**< Bit mask for KEYSCAN_CLKDIV */
#define _KEYSCAN_CFG_CLKDIV_DEFAULT 0x0001387FUL /**< Mode DEFAULT for KEYSCAN_CFG */
#define KEYSCAN_CFG_CLKDIV_DEFAULT (_KEYSCAN_CFG_CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CFG */
#define KEYSCAN_CFG_SINGLEPRESS (0x1UL << 20) /**< Single Press */
#define _KEYSCAN_CFG_SINGLEPRESS_SHIFT 20 /**< Shift value for KEYSCAN_SINGLEPRESS */
#define _KEYSCAN_CFG_SINGLEPRESS_MASK 0x100000UL /**< Bit mask for KEYSCAN_SINGLEPRESS */
#define _KEYSCAN_CFG_SINGLEPRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */
#define _KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS 0x00000000UL /**< Mode MULTIPRESS for KEYSCAN_CFG */
#define _KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS 0x00000001UL /**< Mode SINGLEPRESS for KEYSCAN_CFG */
#define KEYSCAN_CFG_SINGLEPRESS_DEFAULT (_KEYSCAN_CFG_SINGLEPRESS_DEFAULT << 20) /**< Shifted mode DEFAULT for KEYSCAN_CFG */
#define KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS (_KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS << 20) /**< Shifted mode MULTIPRESS for KEYSCAN_CFG */
#define KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS (_KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS << 20) /**< Shifted mode SINGLEPRESS for KEYSCAN_CFG */
#define KEYSCAN_CFG_AUTOSTART (0x1UL << 22) /**< Automatically Start */
#define _KEYSCAN_CFG_AUTOSTART_SHIFT 22 /**< Shift value for KEYSCAN_AUTOSTART */
#define _KEYSCAN_CFG_AUTOSTART_MASK 0x400000UL /**< Bit mask for KEYSCAN_AUTOSTART */
#define _KEYSCAN_CFG_AUTOSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */
#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS 0x00000000UL /**< Mode AUTOSTARTDIS for KEYSCAN_CFG */
#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN 0x00000001UL /**< Mode AUTOSTARTEN for KEYSCAN_CFG */
#define KEYSCAN_CFG_AUTOSTART_DEFAULT (_KEYSCAN_CFG_AUTOSTART_DEFAULT << 22) /**< Shifted mode DEFAULT for KEYSCAN_CFG */
#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS << 22) /**< Shifted mode AUTOSTARTDIS for KEYSCAN_CFG */
#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN << 22) /**< Shifted mode AUTOSTARTEN for KEYSCAN_CFG */
#define _KEYSCAN_CFG_NUMROWS_SHIFT 24 /**< Shift value for KEYSCAN_NUMROWS */
#define _KEYSCAN_CFG_NUMROWS_MASK 0x7000000UL /**< Bit mask for KEYSCAN_NUMROWS */
#define _KEYSCAN_CFG_NUMROWS_DEFAULT 0x00000005UL /**< Mode DEFAULT for KEYSCAN_CFG */
#define _KEYSCAN_CFG_NUMROWS_RSV1 0x00000000UL /**< Mode RSV1 for KEYSCAN_CFG */
#define _KEYSCAN_CFG_NUMROWS_RSV2 0x00000001UL /**< Mode RSV2 for KEYSCAN_CFG */
#define _KEYSCAN_CFG_NUMROWS_ROW3 0x00000002UL /**< Mode ROW3 for KEYSCAN_CFG */
#define _KEYSCAN_CFG_NUMROWS_ROW4 0x00000003UL /**< Mode ROW4 for KEYSCAN_CFG */
#define _KEYSCAN_CFG_NUMROWS_ROW5 0x00000004UL /**< Mode ROW5 for KEYSCAN_CFG */
#define _KEYSCAN_CFG_NUMROWS_ROW6 0x00000005UL /**< Mode ROW6 for KEYSCAN_CFG */
#define KEYSCAN_CFG_NUMROWS_DEFAULT (_KEYSCAN_CFG_NUMROWS_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_CFG */
#define KEYSCAN_CFG_NUMROWS_RSV1 (_KEYSCAN_CFG_NUMROWS_RSV1 << 24) /**< Shifted mode RSV1 for KEYSCAN_CFG */
#define KEYSCAN_CFG_NUMROWS_RSV2 (_KEYSCAN_CFG_NUMROWS_RSV2 << 24) /**< Shifted mode RSV2 for KEYSCAN_CFG */
#define KEYSCAN_CFG_NUMROWS_ROW3 (_KEYSCAN_CFG_NUMROWS_ROW3 << 24) /**< Shifted mode ROW3 for KEYSCAN_CFG */
#define KEYSCAN_CFG_NUMROWS_ROW4 (_KEYSCAN_CFG_NUMROWS_ROW4 << 24) /**< Shifted mode ROW4 for KEYSCAN_CFG */
#define KEYSCAN_CFG_NUMROWS_ROW5 (_KEYSCAN_CFG_NUMROWS_ROW5 << 24) /**< Shifted mode ROW5 for KEYSCAN_CFG */
#define KEYSCAN_CFG_NUMROWS_ROW6 (_KEYSCAN_CFG_NUMROWS_ROW6 << 24) /**< Shifted mode ROW6 for KEYSCAN_CFG */
#define _KEYSCAN_CFG_NUMCOLS_SHIFT 28 /**< Shift value for KEYSCAN_NUMCOLS */
#define _KEYSCAN_CFG_NUMCOLS_MASK 0x70000000UL /**< Bit mask for KEYSCAN_NUMCOLS */
#define _KEYSCAN_CFG_NUMCOLS_DEFAULT 0x00000002UL /**< Mode DEFAULT for KEYSCAN_CFG */
#define KEYSCAN_CFG_NUMCOLS_DEFAULT (_KEYSCAN_CFG_NUMCOLS_DEFAULT << 28) /**< Shifted mode DEFAULT for KEYSCAN_CFG */
/* Bit fields for KEYSCAN CMD */
#define _KEYSCAN_CMD_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_CMD */
#define _KEYSCAN_CMD_MASK 0x00000003UL /**< Mask for KEYSCAN_CMD */
#define KEYSCAN_CMD_KEYSCANSTART (0x1UL << 0) /**< Keyscan Start */
#define _KEYSCAN_CMD_KEYSCANSTART_SHIFT 0 /**< Shift value for KEYSCAN_KEYSCANSTART */
#define _KEYSCAN_CMD_KEYSCANSTART_MASK 0x1UL /**< Bit mask for KEYSCAN_KEYSCANSTART */
#define _KEYSCAN_CMD_KEYSCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */
#define KEYSCAN_CMD_KEYSCANSTART_DEFAULT (_KEYSCAN_CMD_KEYSCANSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CMD */
#define KEYSCAN_CMD_KEYSCANSTOP (0x1UL << 1) /**< Keyscan Stop */
#define _KEYSCAN_CMD_KEYSCANSTOP_SHIFT 1 /**< Shift value for KEYSCAN_KEYSCANSTOP */
#define _KEYSCAN_CMD_KEYSCANSTOP_MASK 0x2UL /**< Bit mask for KEYSCAN_KEYSCANSTOP */
#define _KEYSCAN_CMD_KEYSCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */
#define KEYSCAN_CMD_KEYSCANSTOP_DEFAULT (_KEYSCAN_CMD_KEYSCANSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_CMD */
/* Bit fields for KEYSCAN DELAY */
#define _KEYSCAN_DELAY_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_MASK 0x0F0F0F00UL /**< Mask for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SHIFT 8 /**< Shift value for KEYSCAN_SCANDLY */
#define _KEYSCAN_DELAY_SCANDLY_MASK 0xF00UL /**< Bit mask for KEYSCAN_SCANDLY */
#define _KEYSCAN_DELAY_SCANDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY2 0x00000000UL /**< Mode SCANDLY2 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY4 0x00000001UL /**< Mode SCANDLY4 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY6 0x00000002UL /**< Mode SCANDLY6 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY8 0x00000003UL /**< Mode SCANDLY8 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY10 0x00000004UL /**< Mode SCANDLY10 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY12 0x00000005UL /**< Mode SCANDLY12 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY14 0x00000006UL /**< Mode SCANDLY14 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY16 0x00000007UL /**< Mode SCANDLY16 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY18 0x00000008UL /**< Mode SCANDLY18 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY20 0x00000009UL /**< Mode SCANDLY20 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY22 0x0000000AUL /**< Mode SCANDLY22 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY24 0x0000000BUL /**< Mode SCANDLY24 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY26 0x0000000CUL /**< Mode SCANDLY26 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY28 0x0000000DUL /**< Mode SCANDLY28 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY30 0x0000000EUL /**< Mode SCANDLY30 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_SCANDLY_SCANDLY32 0x0000000FUL /**< Mode SCANDLY32 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_DEFAULT (_KEYSCAN_DELAY_SCANDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY2 (_KEYSCAN_DELAY_SCANDLY_SCANDLY2 << 8) /**< Shifted mode SCANDLY2 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY4 (_KEYSCAN_DELAY_SCANDLY_SCANDLY4 << 8) /**< Shifted mode SCANDLY4 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY6 (_KEYSCAN_DELAY_SCANDLY_SCANDLY6 << 8) /**< Shifted mode SCANDLY6 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY8 (_KEYSCAN_DELAY_SCANDLY_SCANDLY8 << 8) /**< Shifted mode SCANDLY8 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY10 (_KEYSCAN_DELAY_SCANDLY_SCANDLY10 << 8) /**< Shifted mode SCANDLY10 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY12 (_KEYSCAN_DELAY_SCANDLY_SCANDLY12 << 8) /**< Shifted mode SCANDLY12 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY14 (_KEYSCAN_DELAY_SCANDLY_SCANDLY14 << 8) /**< Shifted mode SCANDLY14 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY16 (_KEYSCAN_DELAY_SCANDLY_SCANDLY16 << 8) /**< Shifted mode SCANDLY16 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY18 (_KEYSCAN_DELAY_SCANDLY_SCANDLY18 << 8) /**< Shifted mode SCANDLY18 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY20 (_KEYSCAN_DELAY_SCANDLY_SCANDLY20 << 8) /**< Shifted mode SCANDLY20 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY22 (_KEYSCAN_DELAY_SCANDLY_SCANDLY22 << 8) /**< Shifted mode SCANDLY22 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY24 (_KEYSCAN_DELAY_SCANDLY_SCANDLY24 << 8) /**< Shifted mode SCANDLY24 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY26 (_KEYSCAN_DELAY_SCANDLY_SCANDLY26 << 8) /**< Shifted mode SCANDLY26 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY28 (_KEYSCAN_DELAY_SCANDLY_SCANDLY28 << 8) /**< Shifted mode SCANDLY28 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY30 (_KEYSCAN_DELAY_SCANDLY_SCANDLY30 << 8) /**< Shifted mode SCANDLY30 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_SCANDLY_SCANDLY32 (_KEYSCAN_DELAY_SCANDLY_SCANDLY32 << 8) /**< Shifted mode SCANDLY32 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_SHIFT 16 /**< Shift value for KEYSCAN_DEBDLY */
#define _KEYSCAN_DELAY_DEBDLY_MASK 0xF0000UL /**< Bit mask for KEYSCAN_DEBDLY */
#define _KEYSCAN_DELAY_DEBDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY2 0x00000000UL /**< Mode DEBDLY2 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY4 0x00000001UL /**< Mode DEBDLY4 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY6 0x00000002UL /**< Mode DEBDLY6 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY8 0x00000003UL /**< Mode DEBDLY8 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY10 0x00000004UL /**< Mode DEBDLY10 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY12 0x00000005UL /**< Mode DEBDLY12 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY14 0x00000006UL /**< Mode DEBDLY14 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY16 0x00000007UL /**< Mode DEBDLY16 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY18 0x00000008UL /**< Mode DEBDLY18 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY20 0x00000009UL /**< Mode DEBDLY20 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY22 0x0000000AUL /**< Mode DEBDLY22 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY24 0x0000000BUL /**< Mode DEBDLY24 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY26 0x0000000CUL /**< Mode DEBDLY26 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY28 0x0000000DUL /**< Mode DEBDLY28 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY30 0x0000000EUL /**< Mode DEBDLY30 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_DEBDLY_DEBDLY32 0x0000000FUL /**< Mode DEBDLY32 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEFAULT (_KEYSCAN_DELAY_DEBDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY2 (_KEYSCAN_DELAY_DEBDLY_DEBDLY2 << 16) /**< Shifted mode DEBDLY2 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY4 (_KEYSCAN_DELAY_DEBDLY_DEBDLY4 << 16) /**< Shifted mode DEBDLY4 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY6 (_KEYSCAN_DELAY_DEBDLY_DEBDLY6 << 16) /**< Shifted mode DEBDLY6 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY8 (_KEYSCAN_DELAY_DEBDLY_DEBDLY8 << 16) /**< Shifted mode DEBDLY8 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY10 (_KEYSCAN_DELAY_DEBDLY_DEBDLY10 << 16) /**< Shifted mode DEBDLY10 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY12 (_KEYSCAN_DELAY_DEBDLY_DEBDLY12 << 16) /**< Shifted mode DEBDLY12 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY14 (_KEYSCAN_DELAY_DEBDLY_DEBDLY14 << 16) /**< Shifted mode DEBDLY14 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY16 (_KEYSCAN_DELAY_DEBDLY_DEBDLY16 << 16) /**< Shifted mode DEBDLY16 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY18 (_KEYSCAN_DELAY_DEBDLY_DEBDLY18 << 16) /**< Shifted mode DEBDLY18 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY20 (_KEYSCAN_DELAY_DEBDLY_DEBDLY20 << 16) /**< Shifted mode DEBDLY20 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY22 (_KEYSCAN_DELAY_DEBDLY_DEBDLY22 << 16) /**< Shifted mode DEBDLY22 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY24 (_KEYSCAN_DELAY_DEBDLY_DEBDLY24 << 16) /**< Shifted mode DEBDLY24 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY26 (_KEYSCAN_DELAY_DEBDLY_DEBDLY26 << 16) /**< Shifted mode DEBDLY26 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY28 (_KEYSCAN_DELAY_DEBDLY_DEBDLY28 << 16) /**< Shifted mode DEBDLY28 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY30 (_KEYSCAN_DELAY_DEBDLY_DEBDLY30 << 16) /**< Shifted mode DEBDLY30 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_DEBDLY_DEBDLY32 (_KEYSCAN_DELAY_DEBDLY_DEBDLY32 << 16) /**< Shifted mode DEBDLY32 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_SHIFT 24 /**< Shift value for KEYSCAN_STABDLY */
#define _KEYSCAN_DELAY_STABDLY_MASK 0xF000000UL /**< Bit mask for KEYSCAN_STABDLY */
#define _KEYSCAN_DELAY_STABDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY2 0x00000000UL /**< Mode STABDLY2 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY4 0x00000001UL /**< Mode STABDLY4 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY6 0x00000002UL /**< Mode STABDLY6 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY8 0x00000003UL /**< Mode STABDLY8 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY10 0x00000004UL /**< Mode STABDLY10 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY12 0x00000005UL /**< Mode STABDLY12 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY14 0x00000006UL /**< Mode STABDLY14 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY16 0x00000007UL /**< Mode STABDLY16 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY18 0x00000008UL /**< Mode STABDLY18 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY20 0x00000009UL /**< Mode STABDLY20 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY22 0x0000000AUL /**< Mode STABDLY22 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY24 0x0000000BUL /**< Mode STABDLY24 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY26 0x0000000CUL /**< Mode STABDLY26 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY28 0x0000000DUL /**< Mode STABDLY28 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY30 0x0000000EUL /**< Mode STABDLY30 for KEYSCAN_DELAY */
#define _KEYSCAN_DELAY_STABDLY_STABDLY32 0x0000000FUL /**< Mode STABDLY32 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_DEFAULT (_KEYSCAN_DELAY_STABDLY_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY2 (_KEYSCAN_DELAY_STABDLY_STABDLY2 << 24) /**< Shifted mode STABDLY2 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY4 (_KEYSCAN_DELAY_STABDLY_STABDLY4 << 24) /**< Shifted mode STABDLY4 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY6 (_KEYSCAN_DELAY_STABDLY_STABDLY6 << 24) /**< Shifted mode STABDLY6 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY8 (_KEYSCAN_DELAY_STABDLY_STABDLY8 << 24) /**< Shifted mode STABDLY8 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY10 (_KEYSCAN_DELAY_STABDLY_STABDLY10 << 24) /**< Shifted mode STABDLY10 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY12 (_KEYSCAN_DELAY_STABDLY_STABDLY12 << 24) /**< Shifted mode STABDLY12 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY14 (_KEYSCAN_DELAY_STABDLY_STABDLY14 << 24) /**< Shifted mode STABDLY14 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY16 (_KEYSCAN_DELAY_STABDLY_STABDLY16 << 24) /**< Shifted mode STABDLY16 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY18 (_KEYSCAN_DELAY_STABDLY_STABDLY18 << 24) /**< Shifted mode STABDLY18 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY20 (_KEYSCAN_DELAY_STABDLY_STABDLY20 << 24) /**< Shifted mode STABDLY20 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY22 (_KEYSCAN_DELAY_STABDLY_STABDLY22 << 24) /**< Shifted mode STABDLY22 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY24 (_KEYSCAN_DELAY_STABDLY_STABDLY24 << 24) /**< Shifted mode STABDLY24 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY26 (_KEYSCAN_DELAY_STABDLY_STABDLY26 << 24) /**< Shifted mode STABDLY26 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY28 (_KEYSCAN_DELAY_STABDLY_STABDLY28 << 24) /**< Shifted mode STABDLY28 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY30 (_KEYSCAN_DELAY_STABDLY_STABDLY30 << 24) /**< Shifted mode STABDLY30 for KEYSCAN_DELAY */
#define KEYSCAN_DELAY_STABDLY_STABDLY32 (_KEYSCAN_DELAY_STABDLY_STABDLY32 << 24) /**< Shifted mode STABDLY32 for KEYSCAN_DELAY */
/* Bit fields for KEYSCAN STATUS */
#define _KEYSCAN_STATUS_RESETVALUE 0x40000000UL /**< Default value for KEYSCAN_STATUS */
#define _KEYSCAN_STATUS_MASK 0xC701003FUL /**< Mask for KEYSCAN_STATUS */
#define _KEYSCAN_STATUS_ROW_SHIFT 0 /**< Shift value for KEYSCAN_ROW */
#define _KEYSCAN_STATUS_ROW_MASK 0x3FUL /**< Bit mask for KEYSCAN_ROW */
#define _KEYSCAN_STATUS_ROW_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */
#define KEYSCAN_STATUS_ROW_DEFAULT (_KEYSCAN_STATUS_ROW_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */
#define KEYSCAN_STATUS_RUNNING (0x1UL << 16) /**< Running */
#define _KEYSCAN_STATUS_RUNNING_SHIFT 16 /**< Shift value for KEYSCAN_RUNNING */
#define _KEYSCAN_STATUS_RUNNING_MASK 0x10000UL /**< Bit mask for KEYSCAN_RUNNING */
#define _KEYSCAN_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */
#define KEYSCAN_STATUS_RUNNING_DEFAULT (_KEYSCAN_STATUS_RUNNING_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */
#define _KEYSCAN_STATUS_COL_SHIFT 24 /**< Shift value for KEYSCAN_COL */
#define _KEYSCAN_STATUS_COL_MASK 0x7000000UL /**< Bit mask for KEYSCAN_COL */
#define _KEYSCAN_STATUS_COL_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */
#define KEYSCAN_STATUS_COL_DEFAULT (_KEYSCAN_STATUS_COL_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */
#define KEYSCAN_STATUS_NOKEY (0x1UL << 30) /**< No Key pressed status */
#define _KEYSCAN_STATUS_NOKEY_SHIFT 30 /**< Shift value for KEYSCAN_NOKEY */
#define _KEYSCAN_STATUS_NOKEY_MASK 0x40000000UL /**< Bit mask for KEYSCAN_NOKEY */
#define _KEYSCAN_STATUS_NOKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_STATUS */
#define KEYSCAN_STATUS_NOKEY_DEFAULT (_KEYSCAN_STATUS_NOKEY_DEFAULT << 30) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */
#define KEYSCAN_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy */
#define _KEYSCAN_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for KEYSCAN_SYNCBUSY */
#define _KEYSCAN_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for KEYSCAN_SYNCBUSY */
#define _KEYSCAN_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */
#define KEYSCAN_STATUS_SYNCBUSY_DEFAULT (_KEYSCAN_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */
/* Bit fields for KEYSCAN IF */
#define _KEYSCAN_IF_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_IF */
#define _KEYSCAN_IF_MASK 0x0000000FUL /**< Mask for KEYSCAN_IF */
#define KEYSCAN_IF_NOKEY (0x1UL << 0) /**< No key was pressed */
#define _KEYSCAN_IF_NOKEY_SHIFT 0 /**< Shift value for KEYSCAN_NOKEY */
#define _KEYSCAN_IF_NOKEY_MASK 0x1UL /**< Bit mask for KEYSCAN_NOKEY */
#define _KEYSCAN_IF_NOKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */
#define KEYSCAN_IF_NOKEY_DEFAULT (_KEYSCAN_IF_NOKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IF */
#define KEYSCAN_IF_KEY (0x1UL << 1) /**< A key was pressed */
#define _KEYSCAN_IF_KEY_SHIFT 1 /**< Shift value for KEYSCAN_KEY */
#define _KEYSCAN_IF_KEY_MASK 0x2UL /**< Bit mask for KEYSCAN_KEY */
#define _KEYSCAN_IF_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */
#define KEYSCAN_IF_KEY_DEFAULT (_KEYSCAN_IF_KEY_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_IF */
#define KEYSCAN_IF_SCANNED (0x1UL << 2) /**< Completed scan */
#define _KEYSCAN_IF_SCANNED_SHIFT 2 /**< Shift value for KEYSCAN_SCANNED */
#define _KEYSCAN_IF_SCANNED_MASK 0x4UL /**< Bit mask for KEYSCAN_SCANNED */
#define _KEYSCAN_IF_SCANNED_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */
#define KEYSCAN_IF_SCANNED_DEFAULT (_KEYSCAN_IF_SCANNED_DEFAULT << 2) /**< Shifted mode DEFAULT for KEYSCAN_IF */
#define KEYSCAN_IF_WAKEUP (0x1UL << 3) /**< Wake up */
#define _KEYSCAN_IF_WAKEUP_SHIFT 3 /**< Shift value for KEYSCAN_WAKEUP */
#define _KEYSCAN_IF_WAKEUP_MASK 0x8UL /**< Bit mask for KEYSCAN_WAKEUP */
#define _KEYSCAN_IF_WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */
#define KEYSCAN_IF_WAKEUP_DEFAULT (_KEYSCAN_IF_WAKEUP_DEFAULT << 3) /**< Shifted mode DEFAULT for KEYSCAN_IF */
/* Bit fields for KEYSCAN IEN */
#define _KEYSCAN_IEN_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_IEN */
#define _KEYSCAN_IEN_MASK 0x0000000FUL /**< Mask for KEYSCAN_IEN */
#define KEYSCAN_IEN_NOKEY (0x1UL << 0) /**< No Key was pressed */
#define _KEYSCAN_IEN_NOKEY_SHIFT 0 /**< Shift value for KEYSCAN_NOKEY */
#define _KEYSCAN_IEN_NOKEY_MASK 0x1UL /**< Bit mask for KEYSCAN_NOKEY */
#define _KEYSCAN_IEN_NOKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */
#define KEYSCAN_IEN_NOKEY_DEFAULT (_KEYSCAN_IEN_NOKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IEN */
#define KEYSCAN_IEN_KEY (0x1UL << 1) /**< A Key was pressed */
#define _KEYSCAN_IEN_KEY_SHIFT 1 /**< Shift value for KEYSCAN_KEY */
#define _KEYSCAN_IEN_KEY_MASK 0x2UL /**< Bit mask for KEYSCAN_KEY */
#define _KEYSCAN_IEN_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */
#define KEYSCAN_IEN_KEY_DEFAULT (_KEYSCAN_IEN_KEY_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_IEN */
#define KEYSCAN_IEN_SCANNED (0x1UL << 2) /**< Completed Scanning */
#define _KEYSCAN_IEN_SCANNED_SHIFT 2 /**< Shift value for KEYSCAN_SCANNED */
#define _KEYSCAN_IEN_SCANNED_MASK 0x4UL /**< Bit mask for KEYSCAN_SCANNED */
#define _KEYSCAN_IEN_SCANNED_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */
#define KEYSCAN_IEN_SCANNED_DEFAULT (_KEYSCAN_IEN_SCANNED_DEFAULT << 2) /**< Shifted mode DEFAULT for KEYSCAN_IEN */
#define KEYSCAN_IEN_WAKEUP (0x1UL << 3) /**< Wake up */
#define _KEYSCAN_IEN_WAKEUP_SHIFT 3 /**< Shift value for KEYSCAN_WAKEUP */
#define _KEYSCAN_IEN_WAKEUP_MASK 0x8UL /**< Bit mask for KEYSCAN_WAKEUP */
#define _KEYSCAN_IEN_WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */
#define KEYSCAN_IEN_WAKEUP_DEFAULT (_KEYSCAN_IEN_WAKEUP_DEFAULT << 3) /**< Shifted mode DEFAULT for KEYSCAN_IEN */
/** @} End of group EFR32ZG23_KEYSCAN_BitFields */
/** @} End of group EFR32ZG23_KEYSCAN */
/** @} End of group Parts */
#endif /* EFR32ZG23_KEYSCAN_H */
#ifdef __cplusplus
}
#endif

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cpu/efm32/families/efr32zg23/include/vendor/efr32zg23_lcd.h vendored Normal file
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@ -0,0 +1,641 @@
/**************************************************************************//**
* @file
* @brief EFR32ZG23 LCD register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_LCD_H
#define EFR32ZG23_LCD_H
#define LCD_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_LCD LCD
* @{
* @brief EFR32ZG23 LCD Register Declaration.
*****************************************************************************/
/** LCD Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IPVERSION */
__IOM uint32_t EN; /**< Enable */
__IOM uint32_t SWRST; /**< Software Reset */
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command register */
__IOM uint32_t DISPCTRL; /**< Display Control Register */
__IOM uint32_t BACFG; /**< Blink and Animation Config Register */
__IOM uint32_t BACTRL; /**< Blink and Animation Control Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t AREGA; /**< Animation Register A */
__IOM uint32_t AREGB; /**< Animation Register B */
__IOM uint32_t IF; /**< Interrupt Enable Register */
__IOM uint32_t IEN; /**< Interrupt Enable */
__IOM uint32_t BIASCTRL; /**< Analog BIAS Control */
__IOM uint32_t DISPCTRLX; /**< Display Control Extended */
uint32_t RESERVED0[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD0; /**< Segment Data Register 0 */
uint32_t RESERVED1[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD1; /**< Segment Data Register 1 */
uint32_t RESERVED2[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD2; /**< Segment Data Register 2 */
uint32_t RESERVED3[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD3; /**< Segment Data Register 3 */
uint32_t RESERVED4[25U]; /**< Reserved for future use */
__IOM uint32_t UPDATECTRL; /**< Update Control */
uint32_t RESERVED5[11U]; /**< Reserved for future use */
__IOM uint32_t FRAMERATE; /**< Frame Rate */
uint32_t RESERVED6[963U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IPVERSION */
__IOM uint32_t EN_SET; /**< Enable */
__IOM uint32_t SWRST_SET; /**< Software Reset */
__IOM uint32_t CTRL_SET; /**< Control Register */
__IOM uint32_t CMD_SET; /**< Command register */
__IOM uint32_t DISPCTRL_SET; /**< Display Control Register */
__IOM uint32_t BACFG_SET; /**< Blink and Animation Config Register */
__IOM uint32_t BACTRL_SET; /**< Blink and Animation Control Register */
__IM uint32_t STATUS_SET; /**< Status Register */
__IOM uint32_t AREGA_SET; /**< Animation Register A */
__IOM uint32_t AREGB_SET; /**< Animation Register B */
__IOM uint32_t IF_SET; /**< Interrupt Enable Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable */
__IOM uint32_t BIASCTRL_SET; /**< Analog BIAS Control */
__IOM uint32_t DISPCTRLX_SET; /**< Display Control Extended */
uint32_t RESERVED7[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD0_SET; /**< Segment Data Register 0 */
uint32_t RESERVED8[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD1_SET; /**< Segment Data Register 1 */
uint32_t RESERVED9[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD2_SET; /**< Segment Data Register 2 */
uint32_t RESERVED10[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD3_SET; /**< Segment Data Register 3 */
uint32_t RESERVED11[25U]; /**< Reserved for future use */
__IOM uint32_t UPDATECTRL_SET; /**< Update Control */
uint32_t RESERVED12[11U]; /**< Reserved for future use */
__IOM uint32_t FRAMERATE_SET; /**< Frame Rate */
uint32_t RESERVED13[963U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IPVERSION */
__IOM uint32_t EN_CLR; /**< Enable */
__IOM uint32_t SWRST_CLR; /**< Software Reset */
__IOM uint32_t CTRL_CLR; /**< Control Register */
__IOM uint32_t CMD_CLR; /**< Command register */
__IOM uint32_t DISPCTRL_CLR; /**< Display Control Register */
__IOM uint32_t BACFG_CLR; /**< Blink and Animation Config Register */
__IOM uint32_t BACTRL_CLR; /**< Blink and Animation Control Register */
__IM uint32_t STATUS_CLR; /**< Status Register */
__IOM uint32_t AREGA_CLR; /**< Animation Register A */
__IOM uint32_t AREGB_CLR; /**< Animation Register B */
__IOM uint32_t IF_CLR; /**< Interrupt Enable Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable */
__IOM uint32_t BIASCTRL_CLR; /**< Analog BIAS Control */
__IOM uint32_t DISPCTRLX_CLR; /**< Display Control Extended */
uint32_t RESERVED14[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD0_CLR; /**< Segment Data Register 0 */
uint32_t RESERVED15[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD1_CLR; /**< Segment Data Register 1 */
uint32_t RESERVED16[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD2_CLR; /**< Segment Data Register 2 */
uint32_t RESERVED17[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD3_CLR; /**< Segment Data Register 3 */
uint32_t RESERVED18[25U]; /**< Reserved for future use */
__IOM uint32_t UPDATECTRL_CLR; /**< Update Control */
uint32_t RESERVED19[11U]; /**< Reserved for future use */
__IOM uint32_t FRAMERATE_CLR; /**< Frame Rate */
uint32_t RESERVED20[963U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IPVERSION */
__IOM uint32_t EN_TGL; /**< Enable */
__IOM uint32_t SWRST_TGL; /**< Software Reset */
__IOM uint32_t CTRL_TGL; /**< Control Register */
__IOM uint32_t CMD_TGL; /**< Command register */
__IOM uint32_t DISPCTRL_TGL; /**< Display Control Register */
__IOM uint32_t BACFG_TGL; /**< Blink and Animation Config Register */
__IOM uint32_t BACTRL_TGL; /**< Blink and Animation Control Register */
__IM uint32_t STATUS_TGL; /**< Status Register */
__IOM uint32_t AREGA_TGL; /**< Animation Register A */
__IOM uint32_t AREGB_TGL; /**< Animation Register B */
__IOM uint32_t IF_TGL; /**< Interrupt Enable Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable */
__IOM uint32_t BIASCTRL_TGL; /**< Analog BIAS Control */
__IOM uint32_t DISPCTRLX_TGL; /**< Display Control Extended */
uint32_t RESERVED21[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD0_TGL; /**< Segment Data Register 0 */
uint32_t RESERVED22[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD1_TGL; /**< Segment Data Register 1 */
uint32_t RESERVED23[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD2_TGL; /**< Segment Data Register 2 */
uint32_t RESERVED24[1U]; /**< Reserved for future use */
__IOM uint32_t SEGD3_TGL; /**< Segment Data Register 3 */
uint32_t RESERVED25[25U]; /**< Reserved for future use */
__IOM uint32_t UPDATECTRL_TGL; /**< Update Control */
uint32_t RESERVED26[11U]; /**< Reserved for future use */
__IOM uint32_t FRAMERATE_TGL; /**< Frame Rate */
} LCD_TypeDef;
/** @} End of group EFR32ZG23_LCD */
/**************************************************************************//**
* @addtogroup EFR32ZG23_LCD
* @{
* @defgroup EFR32ZG23_LCD_BitFields LCD Bit Fields
* @{
*****************************************************************************/
/* Bit fields for LCD IPVERSION */
#define _LCD_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LCD_IPVERSION */
#define _LCD_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LCD_IPVERSION */
#define _LCD_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LCD_IPVERSION */
#define _LCD_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_IPVERSION */
#define _LCD_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LCD_IPVERSION */
#define LCD_IPVERSION_IPVERSION_DEFAULT (_LCD_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IPVERSION */
/* Bit fields for LCD EN */
#define _LCD_EN_RESETVALUE 0x00000000UL /**< Default value for LCD_EN */
#define _LCD_EN_MASK 0x00000003UL /**< Mask for LCD_EN */
#define LCD_EN_EN (0x1UL << 0) /**< Enable */
#define _LCD_EN_EN_SHIFT 0 /**< Shift value for LCD_EN */
#define _LCD_EN_EN_MASK 0x1UL /**< Bit mask for LCD_EN */
#define _LCD_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_EN */
#define _LCD_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_EN */
#define _LCD_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_EN */
#define LCD_EN_EN_DEFAULT (_LCD_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_EN */
#define LCD_EN_EN_DISABLE (_LCD_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for LCD_EN */
#define LCD_EN_EN_ENABLE (_LCD_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for LCD_EN */
#define LCD_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
#define _LCD_EN_DISABLING_SHIFT 1 /**< Shift value for LCD_DISABLING */
#define _LCD_EN_DISABLING_MASK 0x2UL /**< Bit mask for LCD_DISABLING */
#define _LCD_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_EN */
#define LCD_EN_DISABLING_DEFAULT (_LCD_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_EN */
/* Bit fields for LCD SWRST */
#define _LCD_SWRST_RESETVALUE 0x00000000UL /**< Default value for LCD_SWRST */
#define _LCD_SWRST_MASK 0x00000003UL /**< Mask for LCD_SWRST */
#define LCD_SWRST_SWRST (0x1UL << 0) /**< Software reset command */
#define _LCD_SWRST_SWRST_SHIFT 0 /**< Shift value for LCD_SWRST */
#define _LCD_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LCD_SWRST */
#define _LCD_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SWRST */
#define LCD_SWRST_SWRST_DEFAULT (_LCD_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SWRST */
#define LCD_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */
#define _LCD_SWRST_RESETTING_SHIFT 1 /**< Shift value for LCD_RESETTING */
#define _LCD_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LCD_RESETTING */
#define _LCD_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SWRST */
#define LCD_SWRST_RESETTING_DEFAULT (_LCD_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SWRST */
/* Bit fields for LCD CTRL */
#define _LCD_CTRL_RESETVALUE 0x00100000UL /**< Default value for LCD_CTRL */
#define _LCD_CTRL_MASK 0x7F1D0006UL /**< Mask for LCD_CTRL */
#define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */
#define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */
#define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
#define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */
#define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000001UL /**< Mode FRAMESTART for LCD_CTRL */
#define _LCD_CTRL_UDCTRL_FCEVENT 0x00000002UL /**< Mode FCEVENT for LCD_CTRL */
#define _LCD_CTRL_UDCTRL_DISPLAYEVENT 0x00000003UL /**< Mode DISPLAYEVENT for LCD_CTRL */
#define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */
#define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */
#define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */
#define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */
#define LCD_CTRL_UDCTRL_DISPLAYEVENT (_LCD_CTRL_UDCTRL_DISPLAYEVENT << 1) /**< Shifted mode DISPLAYEVENT for LCD_CTRL */
#define LCD_CTRL_DSC (0x1UL << 16) /**< Direct Segment Control */
#define _LCD_CTRL_DSC_SHIFT 16 /**< Shift value for LCD_DSC */
#define _LCD_CTRL_DSC_MASK 0x10000UL /**< Bit mask for LCD_DSC */
#define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
#define _LCD_CTRL_DSC_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_CTRL */
#define _LCD_CTRL_DSC_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_CTRL */
#define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_CTRL */
#define LCD_CTRL_DSC_DISABLE (_LCD_CTRL_DSC_DISABLE << 16) /**< Shifted mode DISABLE for LCD_CTRL */
#define LCD_CTRL_DSC_ENABLE (_LCD_CTRL_DSC_ENABLE << 16) /**< Shifted mode ENABLE for LCD_CTRL */
#define _LCD_CTRL_WARMUPDLY_SHIFT 18 /**< Shift value for LCD_WARMUPDLY */
#define _LCD_CTRL_WARMUPDLY_MASK 0x1C0000UL /**< Bit mask for LCD_WARMUPDLY */
#define _LCD_CTRL_WARMUPDLY_DEFAULT 0x00000004UL /**< Mode DEFAULT for LCD_CTRL */
#define _LCD_CTRL_WARMUPDLY_WARMUP1 0x00000000UL /**< Mode WARMUP1 for LCD_CTRL */
#define _LCD_CTRL_WARMUPDLY_WARMUP31 0x00000001UL /**< Mode WARMUP31 for LCD_CTRL */
#define _LCD_CTRL_WARMUPDLY_WARMUP63 0x00000002UL /**< Mode WARMUP63 for LCD_CTRL */
#define _LCD_CTRL_WARMUPDLY_WARMUP125 0x00000003UL /**< Mode WARMUP125 for LCD_CTRL */
#define _LCD_CTRL_WARMUPDLY_WARMUP250 0x00000004UL /**< Mode WARMUP250 for LCD_CTRL */
#define _LCD_CTRL_WARMUPDLY_WARMUP500 0x00000005UL /**< Mode WARMUP500 for LCD_CTRL */
#define _LCD_CTRL_WARMUPDLY_WARMUP1000 0x00000006UL /**< Mode WARMUP1000 for LCD_CTRL */
#define _LCD_CTRL_WARMUPDLY_WARMUP2000 0x00000007UL /**< Mode WARMUP2000 for LCD_CTRL */
#define LCD_CTRL_WARMUPDLY_DEFAULT (_LCD_CTRL_WARMUPDLY_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_CTRL */
#define LCD_CTRL_WARMUPDLY_WARMUP1 (_LCD_CTRL_WARMUPDLY_WARMUP1 << 18) /**< Shifted mode WARMUP1 for LCD_CTRL */
#define LCD_CTRL_WARMUPDLY_WARMUP31 (_LCD_CTRL_WARMUPDLY_WARMUP31 << 18) /**< Shifted mode WARMUP31 for LCD_CTRL */
#define LCD_CTRL_WARMUPDLY_WARMUP63 (_LCD_CTRL_WARMUPDLY_WARMUP63 << 18) /**< Shifted mode WARMUP63 for LCD_CTRL */
#define LCD_CTRL_WARMUPDLY_WARMUP125 (_LCD_CTRL_WARMUPDLY_WARMUP125 << 18) /**< Shifted mode WARMUP125 for LCD_CTRL */
#define LCD_CTRL_WARMUPDLY_WARMUP250 (_LCD_CTRL_WARMUPDLY_WARMUP250 << 18) /**< Shifted mode WARMUP250 for LCD_CTRL */
#define LCD_CTRL_WARMUPDLY_WARMUP500 (_LCD_CTRL_WARMUPDLY_WARMUP500 << 18) /**< Shifted mode WARMUP500 for LCD_CTRL */
#define LCD_CTRL_WARMUPDLY_WARMUP1000 (_LCD_CTRL_WARMUPDLY_WARMUP1000 << 18) /**< Shifted mode WARMUP1000 for LCD_CTRL */
#define LCD_CTRL_WARMUPDLY_WARMUP2000 (_LCD_CTRL_WARMUPDLY_WARMUP2000 << 18) /**< Shifted mode WARMUP2000 for LCD_CTRL */
#define _LCD_CTRL_PRESCALE_SHIFT 24 /**< Shift value for LCD_PRESCALE */
#define _LCD_CTRL_PRESCALE_MASK 0x7F000000UL /**< Bit mask for LCD_PRESCALE */
#define _LCD_CTRL_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
#define LCD_CTRL_PRESCALE_DEFAULT (_LCD_CTRL_PRESCALE_DEFAULT << 24) /**< Shifted mode DEFAULT for LCD_CTRL */
/* Bit fields for LCD CMD */
#define _LCD_CMD_RESETVALUE 0x00000000UL /**< Default value for LCD_CMD */
#define _LCD_CMD_MASK 0x00000003UL /**< Mask for LCD_CMD */
#define LCD_CMD_LOAD (0x1UL << 0) /**< Load command */
#define _LCD_CMD_LOAD_SHIFT 0 /**< Shift value for LCD_LOAD */
#define _LCD_CMD_LOAD_MASK 0x1UL /**< Bit mask for LCD_LOAD */
#define _LCD_CMD_LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CMD */
#define LCD_CMD_LOAD_DEFAULT (_LCD_CMD_LOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CMD */
#define LCD_CMD_CLEAR (0x1UL << 1) /**< Clear command */
#define _LCD_CMD_CLEAR_SHIFT 1 /**< Shift value for LCD_CLEAR */
#define _LCD_CMD_CLEAR_MASK 0x2UL /**< Bit mask for LCD_CLEAR */
#define _LCD_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CMD */
#define LCD_CMD_CLEAR_DEFAULT (_LCD_CMD_CLEAR_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CMD */
/* Bit fields for LCD DISPCTRL */
#define _LCD_DISPCTRL_RESETVALUE 0x00100000UL /**< Default value for LCD_DISPCTRL */
#define _LCD_DISPCTRL_MASK 0x03700017UL /**< Mask for LCD_DISPCTRL */
#define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */
#define _LCD_DISPCTRL_MUX_MASK 0x7UL /**< Bit mask for LCD_MUX */
#define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
#define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
#define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */
#define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */
#define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */
#define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
#define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */
#define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */
#define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */
#define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */
#define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */
#define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */
#define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */
#define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
#define _LCD_DISPCTRL_WAVE_TYPEB 0x00000000UL /**< Mode TYPEB for LCD_DISPCTRL */
#define _LCD_DISPCTRL_WAVE_TYPEA 0x00000001UL /**< Mode TYPEA for LCD_DISPCTRL */
#define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
#define LCD_DISPCTRL_WAVE_TYPEB (_LCD_DISPCTRL_WAVE_TYPEB << 4) /**< Shifted mode TYPEB for LCD_DISPCTRL */
#define LCD_DISPCTRL_WAVE_TYPEA (_LCD_DISPCTRL_WAVE_TYPEA << 4) /**< Shifted mode TYPEA for LCD_DISPCTRL */
#define _LCD_DISPCTRL_CHGRDST_SHIFT 20 /**< Shift value for LCD_CHGRDST */
#define _LCD_DISPCTRL_CHGRDST_MASK 0x700000UL /**< Bit mask for LCD_CHGRDST */
#define _LCD_DISPCTRL_CHGRDST_DEFAULT 0x00000001UL /**< Mode DEFAULT for LCD_DISPCTRL */
#define _LCD_DISPCTRL_CHGRDST_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_DISPCTRL */
#define _LCD_DISPCTRL_CHGRDST_ONE 0x00000001UL /**< Mode ONE for LCD_DISPCTRL */
#define _LCD_DISPCTRL_CHGRDST_TWO 0x00000002UL /**< Mode TWO for LCD_DISPCTRL */
#define _LCD_DISPCTRL_CHGRDST_THREE 0x00000003UL /**< Mode THREE for LCD_DISPCTRL */
#define _LCD_DISPCTRL_CHGRDST_FOUR 0x00000004UL /**< Mode FOUR for LCD_DISPCTRL */
#define LCD_DISPCTRL_CHGRDST_DEFAULT (_LCD_DISPCTRL_CHGRDST_DEFAULT << 20) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
#define LCD_DISPCTRL_CHGRDST_DISABLE (_LCD_DISPCTRL_CHGRDST_DISABLE << 20) /**< Shifted mode DISABLE for LCD_DISPCTRL */
#define LCD_DISPCTRL_CHGRDST_ONE (_LCD_DISPCTRL_CHGRDST_ONE << 20) /**< Shifted mode ONE for LCD_DISPCTRL */
#define LCD_DISPCTRL_CHGRDST_TWO (_LCD_DISPCTRL_CHGRDST_TWO << 20) /**< Shifted mode TWO for LCD_DISPCTRL */
#define LCD_DISPCTRL_CHGRDST_THREE (_LCD_DISPCTRL_CHGRDST_THREE << 20) /**< Shifted mode THREE for LCD_DISPCTRL */
#define LCD_DISPCTRL_CHGRDST_FOUR (_LCD_DISPCTRL_CHGRDST_FOUR << 20) /**< Shifted mode FOUR for LCD_DISPCTRL */
#define _LCD_DISPCTRL_BIAS_SHIFT 24 /**< Shift value for LCD_BIAS */
#define _LCD_DISPCTRL_BIAS_MASK 0x3000000UL /**< Bit mask for LCD_BIAS */
#define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
#define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
#define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */
#define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */
#define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /**< Mode ONEFOURTH for LCD_DISPCTRL */
#define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 24) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
#define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 24) /**< Shifted mode STATIC for LCD_DISPCTRL */
#define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 24) /**< Shifted mode ONEHALF for LCD_DISPCTRL */
#define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 24) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */
#define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 24) /**< Shifted mode ONEFOURTH for LCD_DISPCTRL */
/* Bit fields for LCD BACFG */
#define _LCD_BACFG_RESETVALUE 0x00000007UL /**< Default value for LCD_BACFG */
#define _LCD_BACFG_MASK 0x00FF0007UL /**< Mask for LCD_BACFG */
#define _LCD_BACFG_ASTATETOP_SHIFT 0 /**< Shift value for LCD_ASTATETOP */
#define _LCD_BACFG_ASTATETOP_MASK 0x7UL /**< Bit mask for LCD_ASTATETOP */
#define _LCD_BACFG_ASTATETOP_DEFAULT 0x00000007UL /**< Mode DEFAULT for LCD_BACFG */
#define LCD_BACFG_ASTATETOP_DEFAULT (_LCD_BACFG_ASTATETOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACFG */
#define _LCD_BACFG_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */
#define _LCD_BACFG_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */
#define _LCD_BACFG_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACFG */
#define _LCD_BACFG_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACFG */
#define _LCD_BACFG_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACFG */
#define _LCD_BACFG_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACFG */
#define _LCD_BACFG_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACFG */
#define LCD_BACFG_FCPRESC_DEFAULT (_LCD_BACFG_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACFG */
#define LCD_BACFG_FCPRESC_DIV1 (_LCD_BACFG_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACFG */
#define LCD_BACFG_FCPRESC_DIV2 (_LCD_BACFG_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACFG */
#define LCD_BACFG_FCPRESC_DIV4 (_LCD_BACFG_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACFG */
#define LCD_BACFG_FCPRESC_DIV8 (_LCD_BACFG_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACFG */
#define _LCD_BACFG_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */
#define _LCD_BACFG_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */
#define _LCD_BACFG_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACFG */
#define LCD_BACFG_FCTOP_DEFAULT (_LCD_BACFG_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACFG */
/* Bit fields for LCD BACTRL */
#define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */
#define _LCD_BACTRL_MASK 0x100003FFUL /**< Mask for LCD_BACTRL */
#define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */
#define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */
#define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */
#define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */
#define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */
#define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */
#define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define _LCD_BACTRL_BLANK_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_BACTRL */
#define _LCD_BACTRL_BLANK_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_BACTRL */
#define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_BLANK_DISABLE (_LCD_BACTRL_BLANK_DISABLE << 1) /**< Shifted mode DISABLE for LCD_BACTRL */
#define LCD_BACTRL_BLANK_ENABLE (_LCD_BACTRL_BLANK_ENABLE << 1) /**< Shifted mode ENABLE for LCD_BACTRL */
#define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */
#define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */
#define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */
#define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */
#define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */
#define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
#define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
#define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
#define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */
#define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
#define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
#define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */
#define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */
#define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
#define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
#define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
#define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */
#define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
#define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */
#define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */
#define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */
#define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */
#define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */
#define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */
#define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */
#define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */
#define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */
#define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */
#define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_DISPLAYCNTEN (0x1UL << 9) /**< Display Counter Enable */
#define _LCD_BACTRL_DISPLAYCNTEN_SHIFT 9 /**< Shift value for LCD_DISPLAYCNTEN */
#define _LCD_BACTRL_DISPLAYCNTEN_MASK 0x200UL /**< Bit mask for LCD_DISPLAYCNTEN */
#define _LCD_BACTRL_DISPLAYCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define _LCD_BACTRL_DISPLAYCNTEN_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_BACTRL */
#define _LCD_BACTRL_DISPLAYCNTEN_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_BACTRL */
#define LCD_BACTRL_DISPLAYCNTEN_DEFAULT (_LCD_BACTRL_DISPLAYCNTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_DISPLAYCNTEN_DISABLE (_LCD_BACTRL_DISPLAYCNTEN_DISABLE << 9) /**< Shifted mode DISABLE for LCD_BACTRL */
#define LCD_BACTRL_DISPLAYCNTEN_ENABLE (_LCD_BACTRL_DISPLAYCNTEN_ENABLE << 9) /**< Shifted mode ENABLE for LCD_BACTRL */
#define LCD_BACTRL_ALOC (0x1UL << 28) /**< Animation Location */
#define _LCD_BACTRL_ALOC_SHIFT 28 /**< Shift value for LCD_ALOC */
#define _LCD_BACTRL_ALOC_MASK 0x10000000UL /**< Bit mask for LCD_ALOC */
#define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /**< Mode SEG0TO7 for LCD_BACTRL */
#define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /**< Mode SEG8TO15 for LCD_BACTRL */
#define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /**< Shifted mode SEG0TO7 for LCD_BACTRL */
#define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /**< Shifted mode SEG8TO15 for LCD_BACTRL */
/* Bit fields for LCD STATUS */
#define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */
#define _LCD_STATUS_MASK 0x0000090FUL /**< Mask for LCD_STATUS */
#define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */
#define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */
#define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
#define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */
#define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */
#define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */
#define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */
#define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
#define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */
#define LCD_STATUS_LOADBUSY (0x1UL << 11) /**< Load Synchronization is busy */
#define _LCD_STATUS_LOADBUSY_SHIFT 11 /**< Shift value for LCD_LOADBUSY */
#define _LCD_STATUS_LOADBUSY_MASK 0x800UL /**< Bit mask for LCD_LOADBUSY */
#define _LCD_STATUS_LOADBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
#define LCD_STATUS_LOADBUSY_DEFAULT (_LCD_STATUS_LOADBUSY_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_STATUS */
/* Bit fields for LCD AREGA */
#define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */
#define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */
#define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */
#define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */
#define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */
#define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */
/* Bit fields for LCD AREGB */
#define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */
#define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */
#define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */
#define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */
#define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */
#define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */
/* Bit fields for LCD IF */
#define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */
#define _LCD_IF_MASK 0x00000007UL /**< Mask for LCD_IF */
#define LCD_IF_FC (0x1UL << 0) /**< Frame Counter */
#define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */
#define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
#define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */
#define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */
#define LCD_IF_DISPLAY (0x1UL << 1) /**< Display Update Event */
#define _LCD_IF_DISPLAY_SHIFT 1 /**< Shift value for LCD_DISPLAY */
#define _LCD_IF_DISPLAY_MASK 0x2UL /**< Bit mask for LCD_DISPLAY */
#define _LCD_IF_DISPLAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */
#define LCD_IF_DISPLAY_DEFAULT (_LCD_IF_DISPLAY_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_IF */
#define LCD_IF_SYNCBUSYDONE (0x1UL << 2) /**< Synchronization is Done */
#define _LCD_IF_SYNCBUSYDONE_SHIFT 2 /**< Shift value for LCD_SYNCBUSYDONE */
#define _LCD_IF_SYNCBUSYDONE_MASK 0x4UL /**< Bit mask for LCD_SYNCBUSYDONE */
#define _LCD_IF_SYNCBUSYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */
#define LCD_IF_SYNCBUSYDONE_DEFAULT (_LCD_IF_SYNCBUSYDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_IF */
/* Bit fields for LCD IEN */
#define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */
#define _LCD_IEN_MASK 0x00000007UL /**< Mask for LCD_IEN */
#define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter */
#define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */
#define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
#define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */
#define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */
#define LCD_IEN_DISPLAY (0x1UL << 1) /**< Display Update Event */
#define _LCD_IEN_DISPLAY_SHIFT 1 /**< Shift value for LCD_DISPLAY */
#define _LCD_IEN_DISPLAY_MASK 0x2UL /**< Bit mask for LCD_DISPLAY */
#define _LCD_IEN_DISPLAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */
#define LCD_IEN_DISPLAY_DEFAULT (_LCD_IEN_DISPLAY_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_IEN */
#define LCD_IEN_SYNCBUSYDONE (0x1UL << 2) /**< Sync Busy Done */
#define _LCD_IEN_SYNCBUSYDONE_SHIFT 2 /**< Shift value for LCD_SYNCBUSYDONE */
#define _LCD_IEN_SYNCBUSYDONE_MASK 0x4UL /**< Bit mask for LCD_SYNCBUSYDONE */
#define _LCD_IEN_SYNCBUSYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */
#define LCD_IEN_SYNCBUSYDONE_DEFAULT (_LCD_IEN_SYNCBUSYDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_IEN */
/* Bit fields for LCD BIASCTRL */
#define _LCD_BIASCTRL_RESETVALUE 0x001F0000UL /**< Default value for LCD_BIASCTRL */
#define _LCD_BIASCTRL_MASK 0xC45F137FUL /**< Mask for LCD_BIASCTRL */
#define _LCD_BIASCTRL_RESISTOR_SHIFT 0 /**< Shift value for LCD_RESISTOR */
#define _LCD_BIASCTRL_RESISTOR_MASK 0xFUL /**< Bit mask for LCD_RESISTOR */
#define _LCD_BIASCTRL_RESISTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */
#define LCD_BIASCTRL_RESISTOR_DEFAULT (_LCD_BIASCTRL_RESISTOR_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BIASCTRL */
#define _LCD_BIASCTRL_BUFDRV_SHIFT 4 /**< Shift value for LCD_BUFDRV */
#define _LCD_BIASCTRL_BUFDRV_MASK 0x70UL /**< Bit mask for LCD_BUFDRV */
#define _LCD_BIASCTRL_BUFDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */
#define LCD_BIASCTRL_BUFDRV_DEFAULT (_LCD_BIASCTRL_BUFDRV_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_BIASCTRL */
#define _LCD_BIASCTRL_BUFBIAS_SHIFT 8 /**< Shift value for LCD_BUFBIAS */
#define _LCD_BIASCTRL_BUFBIAS_MASK 0x300UL /**< Bit mask for LCD_BUFBIAS */
#define _LCD_BIASCTRL_BUFBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */
#define LCD_BIASCTRL_BUFBIAS_DEFAULT (_LCD_BIASCTRL_BUFBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BIASCTRL */
#define LCD_BIASCTRL_MODE (0x1UL << 12) /**< Mode Setting */
#define _LCD_BIASCTRL_MODE_SHIFT 12 /**< Shift value for LCD_MODE */
#define _LCD_BIASCTRL_MODE_MASK 0x1000UL /**< Bit mask for LCD_MODE */
#define _LCD_BIASCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */
#define _LCD_BIASCTRL_MODE_STEPDOWN 0x00000000UL /**< Mode STEPDOWN for LCD_BIASCTRL */
#define _LCD_BIASCTRL_MODE_CHARGEPUMP 0x00000001UL /**< Mode CHARGEPUMP for LCD_BIASCTRL */
#define LCD_BIASCTRL_MODE_DEFAULT (_LCD_BIASCTRL_MODE_DEFAULT << 12) /**< Shifted mode DEFAULT for LCD_BIASCTRL */
#define LCD_BIASCTRL_MODE_STEPDOWN (_LCD_BIASCTRL_MODE_STEPDOWN << 12) /**< Shifted mode STEPDOWN for LCD_BIASCTRL */
#define LCD_BIASCTRL_MODE_CHARGEPUMP (_LCD_BIASCTRL_MODE_CHARGEPUMP << 12) /**< Shifted mode CHARGEPUMP for LCD_BIASCTRL */
#define _LCD_BIASCTRL_VLCD_SHIFT 16 /**< Shift value for LCD_VLCD */
#define _LCD_BIASCTRL_VLCD_MASK 0x1F0000UL /**< Bit mask for LCD_VLCD */
#define _LCD_BIASCTRL_VLCD_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_BIASCTRL */
#define LCD_BIASCTRL_VLCD_DEFAULT (_LCD_BIASCTRL_VLCD_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BIASCTRL */
#define LCD_BIASCTRL_VDDXSEL (0x1UL << 22) /**< VDDX select */
#define _LCD_BIASCTRL_VDDXSEL_SHIFT 22 /**< Shift value for LCD_VDDXSEL */
#define _LCD_BIASCTRL_VDDXSEL_MASK 0x400000UL /**< Bit mask for LCD_VDDXSEL */
#define _LCD_BIASCTRL_VDDXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */
#define _LCD_BIASCTRL_VDDXSEL_DVDD 0x00000000UL /**< Mode DVDD for LCD_BIASCTRL */
#define _LCD_BIASCTRL_VDDXSEL_AVDD 0x00000001UL /**< Mode AVDD for LCD_BIASCTRL */
#define LCD_BIASCTRL_VDDXSEL_DEFAULT (_LCD_BIASCTRL_VDDXSEL_DEFAULT << 22) /**< Shifted mode DEFAULT for LCD_BIASCTRL */
#define LCD_BIASCTRL_VDDXSEL_DVDD (_LCD_BIASCTRL_VDDXSEL_DVDD << 22) /**< Shifted mode DVDD for LCD_BIASCTRL */
#define LCD_BIASCTRL_VDDXSEL_AVDD (_LCD_BIASCTRL_VDDXSEL_AVDD << 22) /**< Shifted mode AVDD for LCD_BIASCTRL */
#define LCD_BIASCTRL_LCDGATE (0x1UL << 26) /**< LCD Gate */
#define _LCD_BIASCTRL_LCDGATE_SHIFT 26 /**< Shift value for LCD_LCDGATE */
#define _LCD_BIASCTRL_LCDGATE_MASK 0x4000000UL /**< Bit mask for LCD_LCDGATE */
#define _LCD_BIASCTRL_LCDGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */
#define _LCD_BIASCTRL_LCDGATE_UNGATE 0x00000000UL /**< Mode UNGATE for LCD_BIASCTRL */
#define _LCD_BIASCTRL_LCDGATE_GATE 0x00000001UL /**< Mode GATE for LCD_BIASCTRL */
#define LCD_BIASCTRL_LCDGATE_DEFAULT (_LCD_BIASCTRL_LCDGATE_DEFAULT << 26) /**< Shifted mode DEFAULT for LCD_BIASCTRL */
#define LCD_BIASCTRL_LCDGATE_UNGATE (_LCD_BIASCTRL_LCDGATE_UNGATE << 26) /**< Shifted mode UNGATE for LCD_BIASCTRL */
#define LCD_BIASCTRL_LCDGATE_GATE (_LCD_BIASCTRL_LCDGATE_GATE << 26) /**< Shifted mode GATE for LCD_BIASCTRL */
#define _LCD_BIASCTRL_DMAMODE_SHIFT 30 /**< Shift value for LCD_DMAMODE */
#define _LCD_BIASCTRL_DMAMODE_MASK 0xC0000000UL /**< Bit mask for LCD_DMAMODE */
#define _LCD_BIASCTRL_DMAMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */
#define _LCD_BIASCTRL_DMAMODE_DMADISABLE 0x00000000UL /**< Mode DMADISABLE for LCD_BIASCTRL */
#define _LCD_BIASCTRL_DMAMODE_DMAFC 0x00000001UL /**< Mode DMAFC for LCD_BIASCTRL */
#define _LCD_BIASCTRL_DMAMODE_DMADISPLAY 0x00000002UL /**< Mode DMADISPLAY for LCD_BIASCTRL */
#define LCD_BIASCTRL_DMAMODE_DEFAULT (_LCD_BIASCTRL_DMAMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LCD_BIASCTRL */
#define LCD_BIASCTRL_DMAMODE_DMADISABLE (_LCD_BIASCTRL_DMAMODE_DMADISABLE << 30) /**< Shifted mode DMADISABLE for LCD_BIASCTRL */
#define LCD_BIASCTRL_DMAMODE_DMAFC (_LCD_BIASCTRL_DMAMODE_DMAFC << 30) /**< Shifted mode DMAFC for LCD_BIASCTRL */
#define LCD_BIASCTRL_DMAMODE_DMADISPLAY (_LCD_BIASCTRL_DMAMODE_DMADISPLAY << 30) /**< Shifted mode DMADISPLAY for LCD_BIASCTRL */
/* Bit fields for LCD DISPCTRLX */
#define _LCD_DISPCTRLX_RESETVALUE 0x00000000UL /**< Default value for LCD_DISPCTRLX */
#define _LCD_DISPCTRLX_MASK 0x000003FFUL /**< Mask for LCD_DISPCTRLX */
#define _LCD_DISPCTRLX_DISPLAYDIV_SHIFT 0 /**< Shift value for LCD_DISPLAYDIV */
#define _LCD_DISPCTRLX_DISPLAYDIV_MASK 0x3FFUL /**< Bit mask for LCD_DISPLAYDIV */
#define _LCD_DISPCTRLX_DISPLAYDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRLX */
#define LCD_DISPCTRLX_DISPLAYDIV_DEFAULT (_LCD_DISPCTRLX_DISPLAYDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRLX */
/* Bit fields for LCD SEGD0 */
#define _LCD_SEGD0_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0 */
#define _LCD_SEGD0_MASK 0x000FFFFFUL /**< Mask for LCD_SEGD0 */
#define _LCD_SEGD0_SEGD0_SHIFT 0 /**< Shift value for LCD_SEGD0 */
#define _LCD_SEGD0_SEGD0_MASK 0xFFFFFUL /**< Bit mask for LCD_SEGD0 */
#define _LCD_SEGD0_SEGD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0 */
#define LCD_SEGD0_SEGD0_DEFAULT (_LCD_SEGD0_SEGD0_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0 */
/* Bit fields for LCD SEGD1 */
#define _LCD_SEGD1_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1 */
#define _LCD_SEGD1_MASK 0x000FFFFFUL /**< Mask for LCD_SEGD1 */
#define _LCD_SEGD1_SEGD1_SHIFT 0 /**< Shift value for LCD_SEGD1 */
#define _LCD_SEGD1_SEGD1_MASK 0xFFFFFUL /**< Bit mask for LCD_SEGD1 */
#define _LCD_SEGD1_SEGD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1 */
#define LCD_SEGD1_SEGD1_DEFAULT (_LCD_SEGD1_SEGD1_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1 */
/* Bit fields for LCD SEGD2 */
#define _LCD_SEGD2_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2 */
#define _LCD_SEGD2_MASK 0x000FFFFFUL /**< Mask for LCD_SEGD2 */
#define _LCD_SEGD2_SEGD2_SHIFT 0 /**< Shift value for LCD_SEGD2 */
#define _LCD_SEGD2_SEGD2_MASK 0xFFFFFUL /**< Bit mask for LCD_SEGD2 */
#define _LCD_SEGD2_SEGD2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2 */
#define LCD_SEGD2_SEGD2_DEFAULT (_LCD_SEGD2_SEGD2_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2 */
/* Bit fields for LCD SEGD3 */
#define _LCD_SEGD3_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3 */
#define _LCD_SEGD3_MASK 0x000FFFFFUL /**< Mask for LCD_SEGD3 */
#define _LCD_SEGD3_SEGD3_SHIFT 0 /**< Shift value for LCD_SEGD3 */
#define _LCD_SEGD3_SEGD3_MASK 0xFFFFFUL /**< Bit mask for LCD_SEGD3 */
#define _LCD_SEGD3_SEGD3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3 */
#define LCD_SEGD3_SEGD3_DEFAULT (_LCD_SEGD3_SEGD3_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3 */
/* Bit fields for LCD UPDATECTRL */
#define _LCD_UPDATECTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_UPDATECTRL */
#define _LCD_UPDATECTRL_MASK 0x0001E100UL /**< Mask for LCD_UPDATECTRL */
#define LCD_UPDATECTRL_AUTOLOAD (0x1UL << 8) /**< Auto Load */
#define _LCD_UPDATECTRL_AUTOLOAD_SHIFT 8 /**< Shift value for LCD_AUTOLOAD */
#define _LCD_UPDATECTRL_AUTOLOAD_MASK 0x100UL /**< Bit mask for LCD_AUTOLOAD */
#define _LCD_UPDATECTRL_AUTOLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_UPDATECTRL */
#define _LCD_UPDATECTRL_AUTOLOAD_MANUAL 0x00000000UL /**< Mode MANUAL for LCD_UPDATECTRL */
#define _LCD_UPDATECTRL_AUTOLOAD_AUTO 0x00000001UL /**< Mode AUTO for LCD_UPDATECTRL */
#define LCD_UPDATECTRL_AUTOLOAD_DEFAULT (_LCD_UPDATECTRL_AUTOLOAD_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_UPDATECTRL */
#define LCD_UPDATECTRL_AUTOLOAD_MANUAL (_LCD_UPDATECTRL_AUTOLOAD_MANUAL << 8) /**< Shifted mode MANUAL for LCD_UPDATECTRL */
#define LCD_UPDATECTRL_AUTOLOAD_AUTO (_LCD_UPDATECTRL_AUTOLOAD_AUTO << 8) /**< Shifted mode AUTO for LCD_UPDATECTRL */
#define _LCD_UPDATECTRL_LOADADDR_SHIFT 13 /**< Shift value for LCD_LOADADDR */
#define _LCD_UPDATECTRL_LOADADDR_MASK 0x1E000UL /**< Bit mask for LCD_LOADADDR */
#define _LCD_UPDATECTRL_LOADADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_UPDATECTRL */
#define _LCD_UPDATECTRL_LOADADDR_BACTRLWR 0x00000000UL /**< Mode BACTRLWR for LCD_UPDATECTRL */
#define _LCD_UPDATECTRL_LOADADDR_AREGAWR 0x00000001UL /**< Mode AREGAWR for LCD_UPDATECTRL */
#define _LCD_UPDATECTRL_LOADADDR_AREGBWR 0x00000002UL /**< Mode AREGBWR for LCD_UPDATECTRL */
#define _LCD_UPDATECTRL_LOADADDR_SEGD0WR 0x00000003UL /**< Mode SEGD0WR for LCD_UPDATECTRL */
#define _LCD_UPDATECTRL_LOADADDR_SEGD1WR 0x00000004UL /**< Mode SEGD1WR for LCD_UPDATECTRL */
#define _LCD_UPDATECTRL_LOADADDR_SEGD2WR 0x00000005UL /**< Mode SEGD2WR for LCD_UPDATECTRL */
#define _LCD_UPDATECTRL_LOADADDR_SEGD3WR 0x00000006UL /**< Mode SEGD3WR for LCD_UPDATECTRL */
#define LCD_UPDATECTRL_LOADADDR_DEFAULT (_LCD_UPDATECTRL_LOADADDR_DEFAULT << 13) /**< Shifted mode DEFAULT for LCD_UPDATECTRL */
#define LCD_UPDATECTRL_LOADADDR_BACTRLWR (_LCD_UPDATECTRL_LOADADDR_BACTRLWR << 13) /**< Shifted mode BACTRLWR for LCD_UPDATECTRL */
#define LCD_UPDATECTRL_LOADADDR_AREGAWR (_LCD_UPDATECTRL_LOADADDR_AREGAWR << 13) /**< Shifted mode AREGAWR for LCD_UPDATECTRL */
#define LCD_UPDATECTRL_LOADADDR_AREGBWR (_LCD_UPDATECTRL_LOADADDR_AREGBWR << 13) /**< Shifted mode AREGBWR for LCD_UPDATECTRL */
#define LCD_UPDATECTRL_LOADADDR_SEGD0WR (_LCD_UPDATECTRL_LOADADDR_SEGD0WR << 13) /**< Shifted mode SEGD0WR for LCD_UPDATECTRL */
#define LCD_UPDATECTRL_LOADADDR_SEGD1WR (_LCD_UPDATECTRL_LOADADDR_SEGD1WR << 13) /**< Shifted mode SEGD1WR for LCD_UPDATECTRL */
#define LCD_UPDATECTRL_LOADADDR_SEGD2WR (_LCD_UPDATECTRL_LOADADDR_SEGD2WR << 13) /**< Shifted mode SEGD2WR for LCD_UPDATECTRL */
#define LCD_UPDATECTRL_LOADADDR_SEGD3WR (_LCD_UPDATECTRL_LOADADDR_SEGD3WR << 13) /**< Shifted mode SEGD3WR for LCD_UPDATECTRL */
/* Bit fields for LCD FRAMERATE */
#define _LCD_FRAMERATE_RESETVALUE 0x00000000UL /**< Default value for LCD_FRAMERATE */
#define _LCD_FRAMERATE_MASK 0x000001FFUL /**< Mask for LCD_FRAMERATE */
#define _LCD_FRAMERATE_FRDIV_SHIFT 0 /**< Shift value for LCD_FRDIV */
#define _LCD_FRAMERATE_FRDIV_MASK 0x1FFUL /**< Bit mask for LCD_FRDIV */
#define _LCD_FRAMERATE_FRDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FRAMERATE */
#define LCD_FRAMERATE_FRDIV_DEFAULT (_LCD_FRAMERATE_FRDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FRAMERATE */
/** @} End of group EFR32ZG23_LCD_BitFields */
/** @} End of group EFR32ZG23_LCD */
/** @} End of group Parts */
#endif /* EFR32ZG23_LCD_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 LCDRF register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_LCDRF_H
#define EFR32ZG23_LCDRF_H
#define LCDRF_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_LCDRF LCDRF
* @{
* @brief EFR32ZG23 LCDRF Register Declaration.
*****************************************************************************/
/** LCDRF Register Declaration. */
typedef struct {
__IOM uint32_t RFIMLCDCTRL; /**< RF Interference Mitigation LCD Control */
uint32_t RESERVED0[1023U]; /**< Reserved for future use */
__IOM uint32_t RFIMLCDCTRL_SET; /**< RF Interference Mitigation LCD Control */
uint32_t RESERVED1[1023U]; /**< Reserved for future use */
__IOM uint32_t RFIMLCDCTRL_CLR; /**< RF Interference Mitigation LCD Control */
uint32_t RESERVED2[1023U]; /**< Reserved for future use */
__IOM uint32_t RFIMLCDCTRL_TGL; /**< RF Interference Mitigation LCD Control */
} LCDRF_TypeDef;
/** @} End of group EFR32ZG23_LCDRF */
/**************************************************************************//**
* @addtogroup EFR32ZG23_LCDRF
* @{
* @defgroup EFR32ZG23_LCDRF_BitFields LCDRF Bit Fields
* @{
*****************************************************************************/
/* Bit fields for LCDRF RFIMLCDCTRL */
#define _LCDRF_RFIMLCDCTRL_RESETVALUE 0x00000000UL /**< Default value for LCDRF_RFIMLCDCTRL */
#define _LCDRF_RFIMLCDCTRL_MASK 0x0000001FUL /**< Mask for LCDRF_RFIMLCDCTRL */
#define LCDRF_RFIMLCDCTRL_LCDCPXOEN (0x1UL << 0) /**< LCD Charge Pump XO Clock Enable */
#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_SHIFT 0 /**< Shift value for LCDRF_LCDCPXOEN */
#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_MASK 0x1UL /**< Bit mask for LCDRF_LCDCPXOEN */
#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */
#define LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */
#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL (0x1UL << 1) /**< LCD Charge Pump XO Select */
#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_SHIFT 1 /**< Shift value for LCDRF_LCDCPXOSEL */
#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_MASK 0x2UL /**< Bit mask for LCDRF_LCDCPXOSEL */
#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */
#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO 0x00000000UL /**< Mode INTRCO for LCDRF_RFIMLCDCTRL */
#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV 0x00000001UL /**< Mode HFXODIV for LCDRF_RFIMLCDCTRL */
#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */
#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO << 1) /**< Shifted mode INTRCO for LCDRF_RFIMLCDCTRL */
#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV << 1) /**< Shifted mode HFXODIV for LCDRF_RFIMLCDCTRL */
#define LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN (0x1UL << 2) /**< LCD Charge Pump XO Retime Enable */
#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_SHIFT 2 /**< Shift value for LCDRF_LCDCPXORETIMEEN */
#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_MASK 0x4UL /**< Bit mask for LCDRF_LCDCPXORETIMEEN */
#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */
#define LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */
#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE (0x1UL << 3) /**< LCD Low Noise */
#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SHIFT 3 /**< Shift value for LCDRF_LCDLOWNOISE */
#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_MASK 0x8UL /**< Bit mask for LCDRF_LCDLOWNOISE */
#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */
#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL 0x00000000UL /**< Mode NORMAL for LCDRF_RFIMLCDCTRL */
#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW 0x00000001UL /**< Mode SLOW for LCDRF_RFIMLCDCTRL */
#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT << 3) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */
#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL << 3) /**< Shifted mode NORMAL for LCDRF_RFIMLCDCTRL */
#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW << 3) /**< Shifted mode SLOW for LCDRF_RFIMLCDCTRL */
#define LCDRF_RFIMLCDCTRL_LCDCMPDOUT (0x1UL << 4) /**< LCD Comparator Dout */
#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_SHIFT 4 /**< Shift value for LCDRF_LCDCMPDOUT */
#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_MASK 0x10UL /**< Bit mask for LCDRF_LCDCMPDOUT */
#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */
#define LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */
/** @} End of group EFR32ZG23_LCDRF_BitFields */
/** @} End of group EFR32ZG23_LCDRF */
/** @} End of group Parts */
#endif /* EFR32ZG23_LCDRF_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 LDMA register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_LDMA_H
#define EFR32ZG23_LDMA_H
#define LDMA_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_LDMA LDMA
* @{
* @brief EFR32ZG23 LDMA Register Declaration.
*****************************************************************************/
/** LDMA CH Register Group Declaration. */
typedef struct {
uint32_t RESERVED0[1U]; /**< Reserved for future use */
__IOM uint32_t CFG; /**< Channel Configuration Register */
__IOM uint32_t LOOP; /**< Channel Loop Counter Register */
__IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */
__IOM uint32_t SRC; /**< Channel Descriptor Source Address */
__IOM uint32_t DST; /**< Channel Descriptor Destination Address */
__IOM uint32_t LINK; /**< Channel Descriptor Link Address */
uint32_t RESERVED1[5U]; /**< Reserved for future use */
} LDMA_CH_TypeDef;
/** LDMA Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< DMA Channel Request Clear Register */
__IOM uint32_t EN; /**< DMA module enable disable Register */
__IOM uint32_t CTRL; /**< DMA Control Register */
__IM uint32_t STATUS; /**< DMA Status Register */
__IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */
__IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */
__IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */
__IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */
__IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */
__IOM uint32_t CHEN; /**< DMA Channel Enable Register */
__IOM uint32_t CHDIS; /**< DMA Channel Disable Register */
__IM uint32_t CHSTATUS; /**< DMA Channel Status Register */
__IM uint32_t CHBUSY; /**< DMA Channel Busy Register */
__IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */
__IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */
__IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */
__IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */
__IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */
__IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */
__IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */
__IOM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */
uint32_t RESERVED0[906U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< DMA Channel Request Clear Register */
__IOM uint32_t EN_SET; /**< DMA module enable disable Register */
__IOM uint32_t CTRL_SET; /**< DMA Control Register */
__IM uint32_t STATUS_SET; /**< DMA Status Register */
__IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */
__IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */
__IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */
__IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */
__IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */
__IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */
__IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */
__IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */
__IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */
__IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */
__IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */
__IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */
__IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */
__IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */
__IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */
__IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */
__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */
uint32_t RESERVED1[906U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< DMA Channel Request Clear Register */
__IOM uint32_t EN_CLR; /**< DMA module enable disable Register */
__IOM uint32_t CTRL_CLR; /**< DMA Control Register */
__IM uint32_t STATUS_CLR; /**< DMA Status Register */
__IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */
__IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */
__IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */
__IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */
__IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */
__IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */
__IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */
__IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */
__IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */
__IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */
__IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */
__IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */
__IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */
__IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */
__IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */
__IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */
__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */
uint32_t RESERVED2[906U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< DMA Channel Request Clear Register */
__IOM uint32_t EN_TGL; /**< DMA module enable disable Register */
__IOM uint32_t CTRL_TGL; /**< DMA Control Register */
__IM uint32_t STATUS_TGL; /**< DMA Status Register */
__IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */
__IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */
__IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */
__IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */
__IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */
__IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */
__IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */
__IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */
__IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */
__IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */
__IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */
__IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */
__IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */
__IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */
__IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */
__IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */
__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */
} LDMA_TypeDef;
/** @} End of group EFR32ZG23_LDMA */
/**************************************************************************//**
* @addtogroup EFR32ZG23_LDMA
* @{
* @defgroup EFR32ZG23_LDMA_BitFields LDMA Bit Fields
* @{
*****************************************************************************/
/* Bit fields for LDMA IPVERSION */
#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */
#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */
#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */
#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */
#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */
#define LDMA_IPVERSION_IPVERSION_DEFAULT (_LDMA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IPVERSION */
/* Bit fields for LDMA EN */
#define _LDMA_EN_RESETVALUE 0x00000000UL /**< Default value for LDMA_EN */
#define _LDMA_EN_MASK 0x00000001UL /**< Mask for LDMA_EN */
#define LDMA_EN_EN (0x1UL << 0) /**< LDMA module enable and disable register */
#define _LDMA_EN_EN_SHIFT 0 /**< Shift value for LDMA_EN */
#define _LDMA_EN_EN_MASK 0x1UL /**< Bit mask for LDMA_EN */
#define _LDMA_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_EN */
#define LDMA_EN_EN_DEFAULT (_LDMA_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_EN */
/* Bit fields for LDMA CTRL */
#define _LDMA_CTRL_RESETVALUE 0x1E000000UL /**< Default value for LDMA_CTRL */
#define _LDMA_CTRL_MASK 0x9F000000UL /**< Mask for LDMA_CTRL */
#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */
#define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */
#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x0000001EUL /**< Mode DEFAULT for LDMA_CTRL */
#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */
#define LDMA_CTRL_CORERST (0x1UL << 31) /**< Reset DMA controller */
#define _LDMA_CTRL_CORERST_SHIFT 31 /**< Shift value for LDMA_CORERST */
#define _LDMA_CTRL_CORERST_MASK 0x80000000UL /**< Bit mask for LDMA_CORERST */
#define _LDMA_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
#define LDMA_CTRL_CORERST_DEFAULT (_LDMA_CTRL_CORERST_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CTRL */
/* Bit fields for LDMA STATUS */
#define _LDMA_STATUS_RESETVALUE 0x1F100000UL /**< Default value for LDMA_STATUS */
#define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */
#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */
#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */
#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */
#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */
#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */
#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */
#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */
#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */
#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */
#define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */
#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */
#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */
#define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */
#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */
#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */
#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */
#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */
#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */
#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */
#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */
#define _LDMA_STATUS_CHNUM_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LDMA_STATUS */
#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */
/* Bit fields for LDMA SYNCSWSET */
#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */
#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */
#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */
#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */
#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */
#define LDMA_SYNCSWSET_SYNCSWSET_DEFAULT (_LDMA_SYNCSWSET_SYNCSWSET_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWSET */
/* Bit fields for LDMA SYNCSWCLR */
#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */
#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */
#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */
#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */
#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */
#define LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT (_LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWCLR */
/* Bit fields for LDMA SYNCHWEN */
#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */
#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */
#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */
#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */
#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */
#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */
#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */
#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */
#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */
#define LDMA_SYNCHWEN_SYNCCLREN_DEFAULT (_LDMA_SYNCHWEN_SYNCCLREN_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */
/* Bit fields for LDMA SYNCHWSEL */
#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */
#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */
#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */
#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */
#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */
#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */
#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */
#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */
#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */
#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */
#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */
#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */
#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */
#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */
#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */
#define LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */
#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */
#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */
/* Bit fields for LDMA SYNCSTATUS */
#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */
#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */
#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */
#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */
#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */
#define LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT (_LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSTATUS */
/* Bit fields for LDMA CHEN */
#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */
#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */
#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */
#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */
#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */
#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */
/* Bit fields for LDMA CHDIS */
#define _LDMA_CHDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDIS */
#define _LDMA_CHDIS_MASK 0x000000FFUL /**< Mask for LDMA_CHDIS */
#define _LDMA_CHDIS_CHDIS_SHIFT 0 /**< Shift value for LDMA_CHDIS */
#define _LDMA_CHDIS_CHDIS_MASK 0xFFUL /**< Bit mask for LDMA_CHDIS */
#define _LDMA_CHDIS_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDIS */
#define LDMA_CHDIS_CHDIS_DEFAULT (_LDMA_CHDIS_CHDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDIS */
/* Bit fields for LDMA CHSTATUS */
#define _LDMA_CHSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHSTATUS */
#define _LDMA_CHSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_CHSTATUS */
#define _LDMA_CHSTATUS_CHSTATUS_SHIFT 0 /**< Shift value for LDMA_CHSTATUS */
#define _LDMA_CHSTATUS_CHSTATUS_MASK 0xFFUL /**< Bit mask for LDMA_CHSTATUS */
#define _LDMA_CHSTATUS_CHSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHSTATUS */
#define LDMA_CHSTATUS_CHSTATUS_DEFAULT (_LDMA_CHSTATUS_CHSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHSTATUS */
/* Bit fields for LDMA CHBUSY */
#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */
#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */
#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */
#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */
#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */
#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */
/* Bit fields for LDMA CHDONE */
#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */
#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE0 (0x1UL << 0) /**< DMA Channel Link done intr flag */
#define _LDMA_CHDONE_CHDONE0_SHIFT 0 /**< Shift value for LDMA_CHDONE0 */
#define _LDMA_CHDONE_CHDONE0_MASK 0x1UL /**< Bit mask for LDMA_CHDONE0 */
#define _LDMA_CHDONE_CHDONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE0_DEFAULT (_LDMA_CHDONE_CHDONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE1 (0x1UL << 1) /**< DMA Channel Link done intr flag */
#define _LDMA_CHDONE_CHDONE1_SHIFT 1 /**< Shift value for LDMA_CHDONE1 */
#define _LDMA_CHDONE_CHDONE1_MASK 0x2UL /**< Bit mask for LDMA_CHDONE1 */
#define _LDMA_CHDONE_CHDONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE1_DEFAULT (_LDMA_CHDONE_CHDONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE2 (0x1UL << 2) /**< DMA Channel Link done intr flag */
#define _LDMA_CHDONE_CHDONE2_SHIFT 2 /**< Shift value for LDMA_CHDONE2 */
#define _LDMA_CHDONE_CHDONE2_MASK 0x4UL /**< Bit mask for LDMA_CHDONE2 */
#define _LDMA_CHDONE_CHDONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE2_DEFAULT (_LDMA_CHDONE_CHDONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE3 (0x1UL << 3) /**< DMA Channel Link done intr flag */
#define _LDMA_CHDONE_CHDONE3_SHIFT 3 /**< Shift value for LDMA_CHDONE3 */
#define _LDMA_CHDONE_CHDONE3_MASK 0x8UL /**< Bit mask for LDMA_CHDONE3 */
#define _LDMA_CHDONE_CHDONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE3_DEFAULT (_LDMA_CHDONE_CHDONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE4 (0x1UL << 4) /**< DMA Channel Link done intr flag */
#define _LDMA_CHDONE_CHDONE4_SHIFT 4 /**< Shift value for LDMA_CHDONE4 */
#define _LDMA_CHDONE_CHDONE4_MASK 0x10UL /**< Bit mask for LDMA_CHDONE4 */
#define _LDMA_CHDONE_CHDONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE4_DEFAULT (_LDMA_CHDONE_CHDONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE5 (0x1UL << 5) /**< DMA Channel Link done intr flag */
#define _LDMA_CHDONE_CHDONE5_SHIFT 5 /**< Shift value for LDMA_CHDONE5 */
#define _LDMA_CHDONE_CHDONE5_MASK 0x20UL /**< Bit mask for LDMA_CHDONE5 */
#define _LDMA_CHDONE_CHDONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE5_DEFAULT (_LDMA_CHDONE_CHDONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE6 (0x1UL << 6) /**< DMA Channel Link done intr flag */
#define _LDMA_CHDONE_CHDONE6_SHIFT 6 /**< Shift value for LDMA_CHDONE6 */
#define _LDMA_CHDONE_CHDONE6_MASK 0x40UL /**< Bit mask for LDMA_CHDONE6 */
#define _LDMA_CHDONE_CHDONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE6_DEFAULT (_LDMA_CHDONE_CHDONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE7 (0x1UL << 7) /**< DMA Channel Link done intr flag */
#define _LDMA_CHDONE_CHDONE7_SHIFT 7 /**< Shift value for LDMA_CHDONE7 */
#define _LDMA_CHDONE_CHDONE7_MASK 0x80UL /**< Bit mask for LDMA_CHDONE7 */
#define _LDMA_CHDONE_CHDONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE7_DEFAULT (_LDMA_CHDONE_CHDONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_CHDONE */
/* Bit fields for LDMA DBGHALT */
#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */
#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */
#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */
#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */
#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */
#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */
/* Bit fields for LDMA SWREQ */
#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */
#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */
#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */
#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */
#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */
#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */
/* Bit fields for LDMA REQDIS */
#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */
#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */
#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */
#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */
#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */
#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */
/* Bit fields for LDMA REQPEND */
#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */
#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */
#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */
#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */
#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */
#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */
/* Bit fields for LDMA LINKLOAD */
#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */
#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */
#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */
#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */
#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */
#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */
/* Bit fields for LDMA REQCLEAR */
#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */
#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */
#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */
#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */
#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */
#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */
/* Bit fields for LDMA IF */
#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */
#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */
#define LDMA_IF_DONE0 (0x1UL << 0) /**< DMA Structure Operation Done */
#define _LDMA_IF_DONE0_SHIFT 0 /**< Shift value for LDMA_DONE0 */
#define _LDMA_IF_DONE0_MASK 0x1UL /**< Bit mask for LDMA_DONE0 */
#define _LDMA_IF_DONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE0_DEFAULT (_LDMA_IF_DONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE1 (0x1UL << 1) /**< DMA Structure Operation Done */
#define _LDMA_IF_DONE1_SHIFT 1 /**< Shift value for LDMA_DONE1 */
#define _LDMA_IF_DONE1_MASK 0x2UL /**< Bit mask for LDMA_DONE1 */
#define _LDMA_IF_DONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE1_DEFAULT (_LDMA_IF_DONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE2 (0x1UL << 2) /**< DMA Structure Operation Done */
#define _LDMA_IF_DONE2_SHIFT 2 /**< Shift value for LDMA_DONE2 */
#define _LDMA_IF_DONE2_MASK 0x4UL /**< Bit mask for LDMA_DONE2 */
#define _LDMA_IF_DONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE2_DEFAULT (_LDMA_IF_DONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE3 (0x1UL << 3) /**< DMA Structure Operation Done */
#define _LDMA_IF_DONE3_SHIFT 3 /**< Shift value for LDMA_DONE3 */
#define _LDMA_IF_DONE3_MASK 0x8UL /**< Bit mask for LDMA_DONE3 */
#define _LDMA_IF_DONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE3_DEFAULT (_LDMA_IF_DONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE4 (0x1UL << 4) /**< DMA Structure Operation Done */
#define _LDMA_IF_DONE4_SHIFT 4 /**< Shift value for LDMA_DONE4 */
#define _LDMA_IF_DONE4_MASK 0x10UL /**< Bit mask for LDMA_DONE4 */
#define _LDMA_IF_DONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE4_DEFAULT (_LDMA_IF_DONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE5 (0x1UL << 5) /**< DMA Structure Operation Done */
#define _LDMA_IF_DONE5_SHIFT 5 /**< Shift value for LDMA_DONE5 */
#define _LDMA_IF_DONE5_MASK 0x20UL /**< Bit mask for LDMA_DONE5 */
#define _LDMA_IF_DONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE5_DEFAULT (_LDMA_IF_DONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE6 (0x1UL << 6) /**< DMA Structure Operation Done */
#define _LDMA_IF_DONE6_SHIFT 6 /**< Shift value for LDMA_DONE6 */
#define _LDMA_IF_DONE6_MASK 0x40UL /**< Bit mask for LDMA_DONE6 */
#define _LDMA_IF_DONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE6_DEFAULT (_LDMA_IF_DONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE7 (0x1UL << 7) /**< DMA Structure Operation Done */
#define _LDMA_IF_DONE7_SHIFT 7 /**< Shift value for LDMA_DONE7 */
#define _LDMA_IF_DONE7_MASK 0x80UL /**< Bit mask for LDMA_DONE7 */
#define _LDMA_IF_DONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE7_DEFAULT (_LDMA_IF_DONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_IF */
#define LDMA_IF_ERROR (0x1UL << 31) /**< Error Flag */
#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */
/* Bit fields for LDMA IEN */
#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */
#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */
#define _LDMA_IEN_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */
#define _LDMA_IEN_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */
#define _LDMA_IEN_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
#define LDMA_IEN_CHDONE_DEFAULT (_LDMA_IEN_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */
#define LDMA_IEN_ERROR (0x1UL << 31) /**< Enable or disable the error interrupt */
#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */
/* Bit fields for LDMA CH_CFG */
#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */
#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */
#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */
#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */
#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */
#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */
#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */
#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */
#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */
#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */
#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */
#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */
#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */
#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */
#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */
#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */
#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */
#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */
#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
/* Bit fields for LDMA CH_LOOP */
#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */
#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */
#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */
#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */
#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */
#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */
/* Bit fields for LDMA CH_CTRL */
#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */
#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */
#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */
#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */
#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */
#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */
#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */
#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */
#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */
#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */
#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */
#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */
#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */
#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */
#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */
#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */
#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */
#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */
#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */
#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */
#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */
#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */
#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */
#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */
#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */
#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */
#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */
#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */
#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */
#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */
#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */
#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */
#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */
#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */
#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */
#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */
#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
/* Bit fields for LDMA CH_SRC */
#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */
#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */
#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */
#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */
#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */
#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */
/* Bit fields for LDMA CH_DST */
#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */
#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */
#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */
#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */
#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */
#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */
/* Bit fields for LDMA CH_LINK */
#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */
#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */
#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */
#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */
#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */
#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */
#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */
#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */
#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */
#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */
#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
/** @} End of group EFR32ZG23_LDMA_BitFields */
/** @} End of group EFR32ZG23_LDMA */
/** @} End of group Parts */
#endif /* EFR32ZG23_LDMA_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 LDMAXBAR register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_LDMAXBAR_H
#define EFR32ZG23_LDMAXBAR_H
#define LDMAXBAR_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_LDMAXBAR LDMAXBAR
* @{
* @brief EFR32ZG23 LDMAXBAR Register Declaration.
*****************************************************************************/
/** LDMAXBAR CH Register Group Declaration. */
typedef struct {
__IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */
} LDMAXBAR_CH_TypeDef;
/** LDMAXBAR Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP veersion ID */
LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */
uint32_t RESERVED0[1015U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP veersion ID */
LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */
uint32_t RESERVED1[1015U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP veersion ID */
LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */
uint32_t RESERVED2[1015U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP veersion ID */
LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */
} LDMAXBAR_TypeDef;
/** @} End of group EFR32ZG23_LDMAXBAR */
/**************************************************************************//**
* @addtogroup EFR32ZG23_LDMAXBAR
* @{
* @defgroup EFR32ZG23_LDMAXBAR_BitFields LDMAXBAR Bit Fields
* @{
*****************************************************************************/
/* Bit fields for LDMAXBAR IPVERSION */
#define _LDMAXBAR_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for LDMAXBAR_IPVERSION */
#define _LDMAXBAR_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LDMAXBAR_IPVERSION */
#define _LDMAXBAR_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMAXBAR_IPVERSION */
#define _LDMAXBAR_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LDMAXBAR_IPVERSION */
#define _LDMAXBAR_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for LDMAXBAR_IPVERSION */
#define LDMAXBAR_IPVERSION_IPVERSION_DEFAULT (_LDMAXBAR_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_IPVERSION */
/* Bit fields for LDMAXBAR CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */
#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */
#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */
/** @} End of group EFR32ZG23_LDMAXBAR_BitFields */
/** @} End of group EFR32ZG23_LDMAXBAR */
/** @} End of group Parts */
#endif /* EFR32ZG23_LDMAXBAR_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 LDMA XBAR channel request soruce definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_LDMAXBAR_DEFINES_H
#define EFR32ZG23_LDMAXBAR_DEFINES_H
/* Module source selection indices */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 0x00000002UL /**< Mode TIMER0 for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 0x00000003UL /**< Mode TIMER1 for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 0x00000004UL /**< Mode USART0 for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 0x00000005UL /**< Mode I2C0 for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 0x00000006UL /**< Mode I2C1 for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 0x0000000aUL /**< Mode IADC0 for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MSC 0x0000000bUL /**< Mode MSC for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 0x0000000cUL /**< Mode TIMER2 for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 0x0000000dUL /**< Mode TIMER3 for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 0x0000000eUL /**< Mode TIMER4 for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 0x0000000fUL /**< Mode VDAC0 for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 0x00000010UL /**< Mode EUSART0 for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 0x00000011UL /**< Mode EUSART1 for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 0x00000012UL /**< Mode EUSART2 for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE 0x00000013UL /**< Mode LESENSE for LDMAXBAR_CH_REQSEL */
#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LCD 0x00000014UL /**< Mode LCD for LDMAXBAR_CH_REQSEL */
/* Shifted source selection indices */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_NONE (_LDMAXBAR_CH_REQSEL_SOURCESEL_NONE << 16)
#define LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR (_LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR << 16) /**< Shifted Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted Mode TIMER0 for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted Mode TIMER1 for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted Mode USART0 for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted Mode I2C0 for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted Mode I2C1 for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 << 16) /**< Shifted Mode IADC0 for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_MSC (_LDMAXBAR_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted Mode MSC for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted Mode TIMER2 for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted Mode TIMER3 for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted Mode TIMER4 for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted Mode VDAC0 for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 << 16) /**< Shifted Mode EUSART0 for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 << 16) /**< Shifted Mode EUSART1 for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 << 16) /**< Shifted Mode EUSART2 for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE (_LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted Mode LESENSE for LDMAXBAR_CH_REQSEL */
#define LDMAXBAR_CH_REQSEL_SOURCESEL_LCD (_LDMAXBAR_CH_REQSEL_SOURCESEL_LCD << 16) /**< Shifted Mode LCD for LDMAXBAR_CH_REQSEL */
/* Module signal selection indices */
#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 0x00000000UL /** Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 0x00000001UL /** Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000000UL /** Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000001UL /** Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000002UL /** Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000003UL /** Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000000UL /** Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000001UL /** Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000002UL /** Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000003UL /** Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /** Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT 0x00000001UL /** Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL 0x00000002UL /** Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT 0x00000003UL /** Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000004UL /** Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /** Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /** Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /** Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /** Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN 0x00000000UL /** Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE 0x00000001UL /** Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /** Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000000UL /** Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000001UL /** Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000002UL /** Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000003UL /** Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000000UL /** Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000001UL /** Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000002UL /** Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000003UL /** Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000000UL /** Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000001UL /** Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000002UL /** Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000003UL /** Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ 0x00000000UL /** Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ 0x00000001UL /** Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL 0x00000000UL /** Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL 0x00000001UL /** Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL 0x00000000UL /** Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL 0x00000001UL /** Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL 0x00000000UL /** Mode EUSART2RXFL for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL 0x00000001UL /** Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO 0x00000000UL /** Mode LESENSEFIFO for LDMAXBAR_CH_REQSEL**/
#define _LDMAXBAR_CH_REQSEL_SIGSEL_LCD 0x00000000UL /** Mode LCD for LDMAXBAR_CH_REQSEL**/
/* Shifted Module signal selection indices */
#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 << 0) /** Shifted Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 << 0) /** Shifted Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /** Shifted Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /** Shifted Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /** Shifted Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /** Shifted Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /** Shifted Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /** Shifted Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /** Shifted Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /** Shifted Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /** Shifted Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT << 0) /** Shifted Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL << 0) /** Shifted Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT << 0) /** Shifted Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /** Shifted Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /** Shifted Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /** Shifted Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /** Shifted Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /** Shifted Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN << 0) /** Shifted Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE << 0) /** Shifted Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA (_LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA << 0) /** Shifted Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /** Shifted Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /** Shifted Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /** Shifted Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /** Shifted Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /** Shifted Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /** Shifted Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ << 0) /** Shifted Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ << 0) /** Shifted Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL << 0) /** Shifted Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL << 0) /** Shifted Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL << 0) /** Shifted Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL << 0) /** Shifted Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL << 0) /** Shifted Mode EUSART2RXFL for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL << 0) /** Shifted Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO (_LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO << 0) /** Shifted Mode LESENSEFIFO for LDMAXBAR_CH_REQSEL**/
#define LDMAXBAR_CH_REQSEL_SIGSEL_LCD (_LDMAXBAR_CH_REQSEL_SIGSEL_LCD << 0) /** Shifted Mode LCD for LDMAXBAR_CH_REQSEL**/
#endif /* EFR32ZG23_LDMAXBAR_DEFINES_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 LETIMER register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_LETIMER_H
#define EFR32ZG23_LETIMER_H
#define LETIMER_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_LETIMER LETIMER
* @{
* @brief EFR32ZG23 LETIMER Register Declaration.
*****************************************************************************/
/** LETIMER Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP version */
__IOM uint32_t EN; /**< module en */
__IOM uint32_t SWRST; /**< Software Reset Register */
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t CNT; /**< Counter Value Register */
__IOM uint32_t COMP0; /**< Compare Value Register 0 */
__IOM uint32_t COMP1; /**< Compare Value Register 1 */
__IOM uint32_t TOP; /**< Counter TOP Value Register */
__IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */
__IOM uint32_t REP0; /**< Repeat Counter Register 0 */
__IOM uint32_t REP1; /**< Repeat Counter Register 1 */
__IOM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IOM uint32_t LOCK; /**< Configuration Lock Register */
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
uint32_t RESERVED0[3U]; /**< Reserved for future use */
__IOM uint32_t PRSMODE; /**< PRS Input mode select Register */
uint32_t RESERVED1[1003U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP version */
__IOM uint32_t EN_SET; /**< module en */
__IOM uint32_t SWRST_SET; /**< Software Reset Register */
__IOM uint32_t CTRL_SET; /**< Control Register */
__IOM uint32_t CMD_SET; /**< Command Register */
__IM uint32_t STATUS_SET; /**< Status Register */
__IOM uint32_t CNT_SET; /**< Counter Value Register */
__IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */
__IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */
__IOM uint32_t TOP_SET; /**< Counter TOP Value Register */
__IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */
__IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */
__IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */
__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
__IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
__IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */
uint32_t RESERVED2[3U]; /**< Reserved for future use */
__IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */
uint32_t RESERVED3[1003U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP version */
__IOM uint32_t EN_CLR; /**< module en */
__IOM uint32_t SWRST_CLR; /**< Software Reset Register */
__IOM uint32_t CTRL_CLR; /**< Control Register */
__IOM uint32_t CMD_CLR; /**< Command Register */
__IM uint32_t STATUS_CLR; /**< Status Register */
__IOM uint32_t CNT_CLR; /**< Counter Value Register */
__IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */
__IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */
__IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */
__IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */
__IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */
__IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */
__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
__IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
__IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */
uint32_t RESERVED4[3U]; /**< Reserved for future use */
__IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */
uint32_t RESERVED5[1003U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP version */
__IOM uint32_t EN_TGL; /**< module en */
__IOM uint32_t SWRST_TGL; /**< Software Reset Register */
__IOM uint32_t CTRL_TGL; /**< Control Register */
__IOM uint32_t CMD_TGL; /**< Command Register */
__IM uint32_t STATUS_TGL; /**< Status Register */
__IOM uint32_t CNT_TGL; /**< Counter Value Register */
__IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */
__IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */
__IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */
__IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */
__IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */
__IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */
__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
__IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
__IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */
uint32_t RESERVED6[3U]; /**< Reserved for future use */
__IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */
} LETIMER_TypeDef;
/** @} End of group EFR32ZG23_LETIMER */
/**************************************************************************//**
* @addtogroup EFR32ZG23_LETIMER
* @{
* @defgroup EFR32ZG23_LETIMER_BitFields LETIMER Bit Fields
* @{
*****************************************************************************/
/* Bit fields for LETIMER IPVERSION */
#define _LETIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LETIMER_IPVERSION */
#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */
#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */
#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */
#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LETIMER_IPVERSION */
#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */
/* Bit fields for LETIMER EN */
#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */
#define _LETIMER_EN_MASK 0x00000003UL /**< Mask for LETIMER_EN */
#define LETIMER_EN_EN (0x1UL << 0) /**< module en */
#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */
#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */
#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */
#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */
#define LETIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
#define _LETIMER_EN_DISABLING_SHIFT 1 /**< Shift value for LETIMER_DISABLING */
#define _LETIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for LETIMER_DISABLING */
#define _LETIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */
#define LETIMER_EN_DISABLING_DEFAULT (_LETIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_EN */
/* Bit fields for LETIMER SWRST */
#define _LETIMER_SWRST_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SWRST */
#define _LETIMER_SWRST_MASK 0x00000003UL /**< Mask for LETIMER_SWRST */
#define LETIMER_SWRST_SWRST (0x1UL << 0) /**< Software reset command */
#define _LETIMER_SWRST_SWRST_SHIFT 0 /**< Shift value for LETIMER_SWRST */
#define _LETIMER_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LETIMER_SWRST */
#define _LETIMER_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */
#define LETIMER_SWRST_SWRST_DEFAULT (_LETIMER_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SWRST */
#define LETIMER_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */
#define _LETIMER_SWRST_RESETTING_SHIFT 1 /**< Shift value for LETIMER_RESETTING */
#define _LETIMER_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LETIMER_RESETTING */
#define _LETIMER_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */
#define LETIMER_SWRST_RESETTING_DEFAULT (_LETIMER_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SWRST */
/* Bit fields for LETIMER CTRL */
#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */
#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */
#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */
#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */
#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */
#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */
#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */
#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */
#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */
#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */
#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */
#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */
#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */
#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */
#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */
#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */
#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */
#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */
#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */
#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */
#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */
#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */
#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */
#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */
#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */
#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */
#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */
#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */
#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */
#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */
#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */
#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */
#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */
#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */
#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */
#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */
#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */
#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */
#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */
#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */
#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */
#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */
#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */
#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */
#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */
#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */
#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */
#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */
#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */
#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */
#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */
#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */
#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */
#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */
/* Bit fields for LETIMER CMD */
#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */
#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */
#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */
#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */
#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */
#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */
#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */
#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */
#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */
#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */
#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */
#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */
#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */
#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */
#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */
#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */
#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */
#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */
/* Bit fields for LETIMER STATUS */
#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */
#define _LETIMER_STATUS_MASK 0x00000003UL /**< Mask for LETIMER_STATUS */
#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */
#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */
#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */
#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */
#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */
#define LETIMER_STATUS_LETIMERLOCKSTATUS (0x1UL << 1) /**< LETIMER Lock Status */
#define _LETIMER_STATUS_LETIMERLOCKSTATUS_SHIFT 1 /**< Shift value for LETIMER_LETIMERLOCKSTATUS */
#define _LETIMER_STATUS_LETIMERLOCKSTATUS_MASK 0x2UL /**< Bit mask for LETIMER_LETIMERLOCKSTATUS */
#define _LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */
#define _LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LETIMER_STATUS */
#define _LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for LETIMER_STATUS */
#define LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT (_LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_STATUS */
#define LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for LETIMER_STATUS */
#define LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for LETIMER_STATUS */
/* Bit fields for LETIMER CNT */
#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */
#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */
#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */
#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */
#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */
#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */
/* Bit fields for LETIMER COMP0 */
#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */
#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */
#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */
#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */
#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */
/* Bit fields for LETIMER COMP1 */
#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */
#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */
#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */
#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */
#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */
#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */
/* Bit fields for LETIMER TOP */
#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */
#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */
#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */
#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */
#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */
#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */
/* Bit fields for LETIMER TOPBUFF */
#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */
#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */
#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */
#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */
#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */
#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */
/* Bit fields for LETIMER REP0 */
#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */
#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */
#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */
#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */
/* Bit fields for LETIMER REP1 */
#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */
#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */
#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */
#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */
/* Bit fields for LETIMER IF */
#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */
#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */
#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */
#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */
#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */
#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */
#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */
#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */
/* Bit fields for LETIMER IEN */
#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */
#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */
#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */
#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */
#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */
#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */
#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */
#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */
/* Bit fields for LETIMER LOCK */
#define _LETIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for LETIMER_LOCK */
#define _LETIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for LETIMER_LOCK */
#define _LETIMER_LOCK_LETIMERLOCKKEY_SHIFT 0 /**< Shift value for LETIMER_LETIMERLOCKKEY */
#define _LETIMER_LOCK_LETIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for LETIMER_LETIMERLOCKKEY */
#define _LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_LOCK */
#define _LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK 0x0000CCFCUL /**< Mode UNLOCK for LETIMER_LOCK */
#define LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT (_LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_LOCK */
#define LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK (_LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LETIMER_LOCK */
/* Bit fields for LETIMER SYNCBUSY */
#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */
#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */
#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */
#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */
#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */
#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */
#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */
#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */
#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */
#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */
#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */
#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */
#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */
#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */
#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */
#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */
#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */
#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */
#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */
#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */
#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */
#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */
#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */
#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */
#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
/* Bit fields for LETIMER PRSMODE */
#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */
#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */
#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */
#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */
#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */
#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */
#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */
#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */
#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */
/** @} End of group EFR32ZG23_LETIMER_BitFields */
/** @} End of group EFR32ZG23_LETIMER */
/** @} End of group Parts */
#endif /* EFR32ZG23_LETIMER_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 LFRCO register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_LFRCO_H
#define EFR32ZG23_LFRCO_H
#define LFRCO_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_LFRCO LFRCO
* @{
* @brief EFR32ZG23 LFRCO Register Declaration.
*****************************************************************************/
/** LFRCO Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP version */
uint32_t RESERVED0[1U]; /**< Reserved for future use */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t CAL; /**< Calibration Register */
uint32_t RESERVED1[1U]; /**< Reserved for future use */
__IOM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
__IOM uint32_t LOCK; /**< Configuration Lock Register */
uint32_t RESERVED2[1015U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP version */
uint32_t RESERVED3[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_SET; /**< Status Register */
__IOM uint32_t CAL_SET; /**< Calibration Register */
uint32_t RESERVED4[1U]; /**< Reserved for future use */
__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
__IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */
__IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
uint32_t RESERVED5[1015U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP version */
uint32_t RESERVED6[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_CLR; /**< Status Register */
__IOM uint32_t CAL_CLR; /**< Calibration Register */
uint32_t RESERVED7[1U]; /**< Reserved for future use */
__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
__IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */
__IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
uint32_t RESERVED8[1015U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP version */
uint32_t RESERVED9[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_TGL; /**< Status Register */
__IOM uint32_t CAL_TGL; /**< Calibration Register */
uint32_t RESERVED10[1U]; /**< Reserved for future use */
__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
__IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */
__IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
} LFRCO_TypeDef;
/** @} End of group EFR32ZG23_LFRCO */
/**************************************************************************//**
* @addtogroup EFR32ZG23_LFRCO
* @{
* @defgroup EFR32ZG23_LFRCO_BitFields LFRCO Bit Fields
* @{
*****************************************************************************/
/* Bit fields for LFRCO IPVERSION */
#define _LFRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IPVERSION */
#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */
#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */
#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */
#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IPVERSION */
#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */
/* Bit fields for LFRCO STATUS */
#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */
#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */
#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */
#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */
#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */
#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */
#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */
#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */
#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */
#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */
#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */
#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */
#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */
#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */
#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */
#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */
#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */
#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */
#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */
#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */
#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */
/* Bit fields for LFRCO CAL */
#define _LFRCO_CAL_RESETVALUE 0x000000A5UL /**< Default value for LFRCO_CAL */
#define _LFRCO_CAL_MASK 0x000000FFUL /**< Mask for LFRCO_CAL */
#define _LFRCO_CAL_FREQTRIM_SHIFT 0 /**< Shift value for LFRCO_FREQTRIM */
#define _LFRCO_CAL_FREQTRIM_MASK 0xFFUL /**< Bit mask for LFRCO_FREQTRIM */
#define _LFRCO_CAL_FREQTRIM_DEFAULT 0x000000A5UL /**< Mode DEFAULT for LFRCO_CAL */
#define LFRCO_CAL_FREQTRIM_DEFAULT (_LFRCO_CAL_FREQTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CAL */
/* Bit fields for LFRCO IF */
#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */
#define _LFRCO_IF_MASK 0x00000007UL /**< Mask for LFRCO_IF */
#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */
#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */
#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */
#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */
#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */
#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */
#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */
#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */
#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */
#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */
#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */
#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */
/* Bit fields for LFRCO IEN */
#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */
#define _LFRCO_IEN_MASK 0x00000007UL /**< Mask for LFRCO_IEN */
#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Interrupt Enable */
#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */
#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */
#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */
#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */
#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */
#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */
#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */
#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */
#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */
#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */
#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */
/* Bit fields for LFRCO SYNCBUSY */
#define _LFRCO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFRCO_SYNCBUSY */
#define _LFRCO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFRCO_SYNCBUSY */
#define LFRCO_SYNCBUSY_CAL (0x1UL << 0) /**< CAL Busy */
#define _LFRCO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFRCO_CAL */
#define _LFRCO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFRCO_CAL */
#define _LFRCO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_SYNCBUSY */
#define LFRCO_SYNCBUSY_CAL_DEFAULT (_LFRCO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_SYNCBUSY */
/* Bit fields for LFRCO LOCK */
#define _LFRCO_LOCK_RESETVALUE 0x00002603UL /**< Default value for LFRCO_LOCK */
#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */
#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */
#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */
#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00002603UL /**< Mode DEFAULT for LFRCO_LOCK */
#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */
#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00002603UL /**< Mode UNLOCK for LFRCO_LOCK */
#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */
#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */
#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */
/** @} End of group EFR32ZG23_LFRCO_BitFields */
/** @} End of group EFR32ZG23_LFRCO */
/** @} End of group Parts */
#endif /* EFR32ZG23_LFRCO_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 LFXO register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_LFXO_H
#define EFR32ZG23_LFXO_H
#define LFXO_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_LFXO LFXO
* @{
* @brief EFR32ZG23 LFXO Register Declaration.
*****************************************************************************/
/** LFXO Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< LFXO IP version */
__IOM uint32_t CTRL; /**< LFXO Control Register */
__IOM uint32_t CFG; /**< LFXO Configuration Register */
uint32_t RESERVED0[1U]; /**< Reserved for future use */
__IM uint32_t STATUS; /**< LFXO Status Register */
__IOM uint32_t CAL; /**< LFXO Calibration Register */
__IOM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */
__IOM uint32_t LOCK; /**< Configuration Lock Register */
uint32_t RESERVED1[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< LFXO IP version */
__IOM uint32_t CTRL_SET; /**< LFXO Control Register */
__IOM uint32_t CFG_SET; /**< LFXO Configuration Register */
uint32_t RESERVED2[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_SET; /**< LFXO Status Register */
__IOM uint32_t CAL_SET; /**< LFXO Calibration Register */
__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
__IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */
__IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
uint32_t RESERVED3[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< LFXO IP version */
__IOM uint32_t CTRL_CLR; /**< LFXO Control Register */
__IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */
uint32_t RESERVED4[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_CLR; /**< LFXO Status Register */
__IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */
__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
__IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */
__IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
uint32_t RESERVED5[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< LFXO IP version */
__IOM uint32_t CTRL_TGL; /**< LFXO Control Register */
__IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */
uint32_t RESERVED6[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_TGL; /**< LFXO Status Register */
__IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */
__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
__IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */
__IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
} LFXO_TypeDef;
/** @} End of group EFR32ZG23_LFXO */
/**************************************************************************//**
* @addtogroup EFR32ZG23_LFXO
* @{
* @defgroup EFR32ZG23_LFXO_BitFields LFXO Bit Fields
* @{
*****************************************************************************/
/* Bit fields for LFXO IPVERSION */
#define _LFXO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LFXO_IPVERSION */
#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */
#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */
#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */
#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IPVERSION */
#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */
/* Bit fields for LFXO CTRL */
#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */
#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */
#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */
#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */
#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */
#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */
#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */
#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */
#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */
#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */
#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */
#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */
#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */
#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */
#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */
#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */
#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */
#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */
#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */
#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */
#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */
#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */
/* Bit fields for LFXO CFG */
#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */
#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */
#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */
#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */
#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */
#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */
#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */
#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */
#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */
#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */
#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */
#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */
#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */
#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */
#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */
#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */
#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */
#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */
#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */
#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */
#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */
#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */
#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */
#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */
#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */
#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */
#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */
#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */
#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */
#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */
#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */
#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */
#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */
#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */
#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */
#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */
#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */
#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */
#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */
#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */
#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */
#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */
/* Bit fields for LFXO STATUS */
#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */
#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */
#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */
#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */
#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */
#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */
#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */
#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */
#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */
#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */
#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */
#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */
#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */
#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */
#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */
#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */
#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */
#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */
#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */
#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */
#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */
/* Bit fields for LFXO CAL */
#define _LFXO_CAL_RESETVALUE 0x00000200UL /**< Default value for LFXO_CAL */
#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */
#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */
#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */
#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */
#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */
#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */
#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */
#define _LFXO_CAL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for LFXO_CAL */
#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */
/* Bit fields for LFXO IF */
#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */
#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */
#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */
#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */
#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */
#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */
#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */
#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */
#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */
#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */
#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */
#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */
#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */
#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */
#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */
#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */
#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */
#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */
#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */
#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */
#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */
#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */
/* Bit fields for LFXO IEN */
#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */
#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */
#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */
#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */
#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */
#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */
#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */
#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */
#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */
#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */
#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */
#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */
#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */
#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */
#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */
#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */
#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */
#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */
#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */
#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */
#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */
#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */
/* Bit fields for LFXO SYNCBUSY */
#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */
#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */
#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */
#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */
#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */
#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */
#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */
/* Bit fields for LFXO LOCK */
#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */
#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */
#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */
#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */
#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */
#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */
#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */
#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */
/** @} End of group EFR32ZG23_LFXO_BitFields */
/** @} End of group EFR32ZG23_LFXO */
/** @} End of group Parts */
#endif /* EFR32ZG23_LFXO_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 MAILBOX register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_MAILBOX_H
#define EFR32ZG23_MAILBOX_H
#define MAILBOX_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_MAILBOX MAILBOX
* @{
* @brief EFR32ZG23 MAILBOX Register Declaration.
*****************************************************************************/
/** MAILBOX MSGPTRS Register Group Declaration. */
typedef struct {
__IOM uint32_t MSGPTR; /**< Message Pointer */
} MAILBOX_MSGPTRS_TypeDef;
/** MAILBOX Register Declaration. */
typedef struct {
MAILBOX_MSGPTRS_TypeDef MSGPTRS[4U]; /**< Message Pointers */
uint32_t RESERVED0[12U]; /**< Reserved for future use */
__IOM uint32_t IF; /**< Interrupt Flag register */
__IOM uint32_t IEN; /**< Interrupt Enable register */
uint32_t RESERVED1[1006U]; /**< Reserved for future use */
MAILBOX_MSGPTRS_TypeDef MSGPTRS_SET[4U]; /**< Message Pointers */
uint32_t RESERVED2[12U]; /**< Reserved for future use */
__IOM uint32_t IF_SET; /**< Interrupt Flag register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable register */
uint32_t RESERVED3[1006U]; /**< Reserved for future use */
MAILBOX_MSGPTRS_TypeDef MSGPTRS_CLR[4U]; /**< Message Pointers */
uint32_t RESERVED4[12U]; /**< Reserved for future use */
__IOM uint32_t IF_CLR; /**< Interrupt Flag register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable register */
uint32_t RESERVED5[1006U]; /**< Reserved for future use */
MAILBOX_MSGPTRS_TypeDef MSGPTRS_TGL[4U]; /**< Message Pointers */
uint32_t RESERVED6[12U]; /**< Reserved for future use */
__IOM uint32_t IF_TGL; /**< Interrupt Flag register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable register */
} MAILBOX_TypeDef;
/** @} End of group EFR32ZG23_MAILBOX */
/**************************************************************************//**
* @addtogroup EFR32ZG23_MAILBOX
* @{
* @defgroup EFR32ZG23_MAILBOX_BitFields MAILBOX Bit Fields
* @{
*****************************************************************************/
/* Bit fields for MAILBOX MSGPTR */
#define _MAILBOX_MSGPTR_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_MSGPTR */
#define _MAILBOX_MSGPTR_MASK 0xFFFFFFFFUL /**< Mask for MAILBOX_MSGPTR */
#define _MAILBOX_MSGPTR_PTR_SHIFT 0 /**< Shift value for MAILBOX_PTR */
#define _MAILBOX_MSGPTR_PTR_MASK 0xFFFFFFFFUL /**< Bit mask for MAILBOX_PTR */
#define _MAILBOX_MSGPTR_PTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_MSGPTR */
#define MAILBOX_MSGPTR_PTR_DEFAULT (_MAILBOX_MSGPTR_PTR_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_MSGPTR */
/* Bit fields for MAILBOX IF */
#define _MAILBOX_IF_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IF */
#define _MAILBOX_IF_MASK 0x0000000FUL /**< Mask for MAILBOX_IF */
#define MAILBOX_IF_MBOXIF0 (0x1UL << 0) /**< Mailbox Interupt Flag */
#define _MAILBOX_IF_MBOXIF0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIF0 */
#define _MAILBOX_IF_MBOXIF0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIF0 */
#define _MAILBOX_IF_MBOXIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */
#define MAILBOX_IF_MBOXIF0_DEFAULT (_MAILBOX_IF_MBOXIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IF */
#define MAILBOX_IF_MBOXIF1 (0x1UL << 1) /**< Mailbox Interupt Flag */
#define _MAILBOX_IF_MBOXIF1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIF1 */
#define _MAILBOX_IF_MBOXIF1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIF1 */
#define _MAILBOX_IF_MBOXIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */
#define MAILBOX_IF_MBOXIF1_DEFAULT (_MAILBOX_IF_MBOXIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IF */
#define MAILBOX_IF_MBOXIF2 (0x1UL << 2) /**< Mailbox Interupt Flag */
#define _MAILBOX_IF_MBOXIF2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIF2 */
#define _MAILBOX_IF_MBOXIF2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIF2 */
#define _MAILBOX_IF_MBOXIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */
#define MAILBOX_IF_MBOXIF2_DEFAULT (_MAILBOX_IF_MBOXIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IF */
#define MAILBOX_IF_MBOXIF3 (0x1UL << 3) /**< Mailbox Interupt Flag */
#define _MAILBOX_IF_MBOXIF3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIF3 */
#define _MAILBOX_IF_MBOXIF3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIF3 */
#define _MAILBOX_IF_MBOXIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */
#define MAILBOX_IF_MBOXIF3_DEFAULT (_MAILBOX_IF_MBOXIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IF */
/* Bit fields for MAILBOX IEN */
#define _MAILBOX_IEN_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IEN */
#define _MAILBOX_IEN_MASK 0x0000000FUL /**< Mask for MAILBOX_IEN */
#define MAILBOX_IEN_MBOXIEN0 (0x1UL << 0) /**< Mailbox Interrupt Enable */
#define _MAILBOX_IEN_MBOXIEN0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIEN0 */
#define _MAILBOX_IEN_MBOXIEN0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIEN0 */
#define _MAILBOX_IEN_MBOXIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */
#define MAILBOX_IEN_MBOXIEN0_DEFAULT (_MAILBOX_IEN_MBOXIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IEN */
#define MAILBOX_IEN_MBOXIEN1 (0x1UL << 1) /**< Mailbox Interrupt Enable */
#define _MAILBOX_IEN_MBOXIEN1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIEN1 */
#define _MAILBOX_IEN_MBOXIEN1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIEN1 */
#define _MAILBOX_IEN_MBOXIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */
#define MAILBOX_IEN_MBOXIEN1_DEFAULT (_MAILBOX_IEN_MBOXIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IEN */
#define MAILBOX_IEN_MBOXIEN2 (0x1UL << 2) /**< Mailbox Interrupt Enable */
#define _MAILBOX_IEN_MBOXIEN2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIEN2 */
#define _MAILBOX_IEN_MBOXIEN2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIEN2 */
#define _MAILBOX_IEN_MBOXIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */
#define MAILBOX_IEN_MBOXIEN2_DEFAULT (_MAILBOX_IEN_MBOXIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IEN */
#define MAILBOX_IEN_MBOXIEN3 (0x1UL << 3) /**< Mailbox Interrupt Enable */
#define _MAILBOX_IEN_MBOXIEN3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIEN3 */
#define _MAILBOX_IEN_MBOXIEN3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIEN3 */
#define _MAILBOX_IEN_MBOXIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */
#define MAILBOX_IEN_MBOXIEN3_DEFAULT (_MAILBOX_IEN_MBOXIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IEN */
/** @} End of group EFR32ZG23_MAILBOX_BitFields */
/** @} End of group EFR32ZG23_MAILBOX */
/** @} End of group Parts */
#endif /* EFR32ZG23_MAILBOX_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 MPAHBRAM register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_MPAHBRAM_H
#define EFR32ZG23_MPAHBRAM_H
#define MPAHBRAM_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_MPAHBRAM MPAHBRAM
* @{
* @brief EFR32ZG23 MPAHBRAM Register Declaration.
*****************************************************************************/
/** MPAHBRAM Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP version ID */
__IOM uint32_t CMD; /**< Command register */
__IOM uint32_t CTRL; /**< Control register */
__IM uint32_t ECCERRADDR0; /**< ECC Error Address 0 */
__IM uint32_t ECCERRADDR1; /**< ECC Error Address 1 */
uint32_t RESERVED0[2U]; /**< Reserved for future use */
__IM uint32_t ECCMERRIND; /**< Multiple ECC error indication */
__IOM uint32_t IF; /**< Interrupt Flags */
__IOM uint32_t IEN; /**< Interrupt Enable */
uint32_t RESERVED1[7U]; /**< Reserved for future use */
uint32_t RESERVED2[1U]; /**< Reserved for future use */
uint32_t RESERVED3[1006U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP version ID */
__IOM uint32_t CMD_SET; /**< Command register */
__IOM uint32_t CTRL_SET; /**< Control register */
__IM uint32_t ECCERRADDR0_SET; /**< ECC Error Address 0 */
__IM uint32_t ECCERRADDR1_SET; /**< ECC Error Address 1 */
uint32_t RESERVED4[2U]; /**< Reserved for future use */
__IM uint32_t ECCMERRIND_SET; /**< Multiple ECC error indication */
__IOM uint32_t IF_SET; /**< Interrupt Flags */
__IOM uint32_t IEN_SET; /**< Interrupt Enable */
uint32_t RESERVED5[7U]; /**< Reserved for future use */
uint32_t RESERVED6[1U]; /**< Reserved for future use */
uint32_t RESERVED7[1006U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP version ID */
__IOM uint32_t CMD_CLR; /**< Command register */
__IOM uint32_t CTRL_CLR; /**< Control register */
__IM uint32_t ECCERRADDR0_CLR; /**< ECC Error Address 0 */
__IM uint32_t ECCERRADDR1_CLR; /**< ECC Error Address 1 */
uint32_t RESERVED8[2U]; /**< Reserved for future use */
__IM uint32_t ECCMERRIND_CLR; /**< Multiple ECC error indication */
__IOM uint32_t IF_CLR; /**< Interrupt Flags */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable */
uint32_t RESERVED9[7U]; /**< Reserved for future use */
uint32_t RESERVED10[1U]; /**< Reserved for future use */
uint32_t RESERVED11[1006U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP version ID */
__IOM uint32_t CMD_TGL; /**< Command register */
__IOM uint32_t CTRL_TGL; /**< Control register */
__IM uint32_t ECCERRADDR0_TGL; /**< ECC Error Address 0 */
__IM uint32_t ECCERRADDR1_TGL; /**< ECC Error Address 1 */
uint32_t RESERVED12[2U]; /**< Reserved for future use */
__IM uint32_t ECCMERRIND_TGL; /**< Multiple ECC error indication */
__IOM uint32_t IF_TGL; /**< Interrupt Flags */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable */
uint32_t RESERVED13[7U]; /**< Reserved for future use */
uint32_t RESERVED14[1U]; /**< Reserved for future use */
} MPAHBRAM_TypeDef;
/** @} End of group EFR32ZG23_MPAHBRAM */
/**************************************************************************//**
* @addtogroup EFR32ZG23_MPAHBRAM
* @{
* @defgroup EFR32ZG23_MPAHBRAM_BitFields MPAHBRAM Bit Fields
* @{
*****************************************************************************/
/* Bit fields for MPAHBRAM IPVERSION */
#define _MPAHBRAM_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for MPAHBRAM_IPVERSION */
#define _MPAHBRAM_IPVERSION_MASK 0x00000001UL /**< Mask for MPAHBRAM_IPVERSION */
#define MPAHBRAM_IPVERSION_IPVERSION (0x1UL << 0) /**< New BitField */
#define _MPAHBRAM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MPAHBRAM_IPVERSION */
#define _MPAHBRAM_IPVERSION_IPVERSION_MASK 0x1UL /**< Bit mask for MPAHBRAM_IPVERSION */
#define _MPAHBRAM_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_IPVERSION */
#define MPAHBRAM_IPVERSION_IPVERSION_DEFAULT (_MPAHBRAM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IPVERSION */
/* Bit fields for MPAHBRAM CMD */
#define _MPAHBRAM_CMD_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CMD */
#define _MPAHBRAM_CMD_MASK 0x00000003UL /**< Mask for MPAHBRAM_CMD */
#define MPAHBRAM_CMD_CLEARECCADDR0 (0x1UL << 0) /**< Clear ECCERRADDR0 */
#define _MPAHBRAM_CMD_CLEARECCADDR0_SHIFT 0 /**< Shift value for MPAHBRAM_CLEARECCADDR0 */
#define _MPAHBRAM_CMD_CLEARECCADDR0_MASK 0x1UL /**< Bit mask for MPAHBRAM_CLEARECCADDR0 */
#define _MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */
#define MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */
#define MPAHBRAM_CMD_CLEARECCADDR1 (0x1UL << 1) /**< Clear ECCERRADDR1 */
#define _MPAHBRAM_CMD_CLEARECCADDR1_SHIFT 1 /**< Shift value for MPAHBRAM_CLEARECCADDR1 */
#define _MPAHBRAM_CMD_CLEARECCADDR1_MASK 0x2UL /**< Bit mask for MPAHBRAM_CLEARECCADDR1 */
#define _MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */
#define MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */
/* Bit fields for MPAHBRAM CTRL */
#define _MPAHBRAM_CTRL_RESETVALUE 0x00000040UL /**< Default value for MPAHBRAM_CTRL */
#define _MPAHBRAM_CTRL_MASK 0x0000007FUL /**< Mask for MPAHBRAM_CTRL */
#define MPAHBRAM_CTRL_ECCEN (0x1UL << 0) /**< Enable ECC functionality */
#define _MPAHBRAM_CTRL_ECCEN_SHIFT 0 /**< Shift value for MPAHBRAM_ECCEN */
#define _MPAHBRAM_CTRL_ECCEN_MASK 0x1UL /**< Bit mask for MPAHBRAM_ECCEN */
#define _MPAHBRAM_CTRL_ECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */
#define MPAHBRAM_CTRL_ECCEN_DEFAULT (_MPAHBRAM_CTRL_ECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */
#define MPAHBRAM_CTRL_ECCWEN (0x1UL << 1) /**< Enable ECC syndrome writes */
#define _MPAHBRAM_CTRL_ECCWEN_SHIFT 1 /**< Shift value for MPAHBRAM_ECCWEN */
#define _MPAHBRAM_CTRL_ECCWEN_MASK 0x2UL /**< Bit mask for MPAHBRAM_ECCWEN */
#define _MPAHBRAM_CTRL_ECCWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */
#define MPAHBRAM_CTRL_ECCWEN_DEFAULT (_MPAHBRAM_CTRL_ECCWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */
#define MPAHBRAM_CTRL_ECCERRFAULTEN (0x1UL << 2) /**< ECC Error bus fault enable */
#define _MPAHBRAM_CTRL_ECCERRFAULTEN_SHIFT 2 /**< Shift value for MPAHBRAM_ECCERRFAULTEN */
#define _MPAHBRAM_CTRL_ECCERRFAULTEN_MASK 0x4UL /**< Bit mask for MPAHBRAM_ECCERRFAULTEN */
#define _MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */
#define MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */
#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT 3 /**< Shift value for MPAHBRAM_AHBPORTPRIORITY */
#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK 0x38UL /**< Bit mask for MPAHBRAM_AHBPORTPRIORITY */
#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */
#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE 0x00000000UL /**< Mode NONE for MPAHBRAM_CTRL */
#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 0x00000001UL /**< Mode PORT0 for MPAHBRAM_CTRL */
#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 0x00000002UL /**< Mode PORT1 for MPAHBRAM_CTRL */
#define MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT (_MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */
#define MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE (_MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE << 3) /**< Shifted mode NONE for MPAHBRAM_CTRL */
#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 << 3) /**< Shifted mode PORT0 for MPAHBRAM_CTRL */
#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 << 3) /**< Shifted mode PORT1 for MPAHBRAM_CTRL */
#define MPAHBRAM_CTRL_ADDRFAULTEN (0x1UL << 6) /**< Address fault bus fault enable */
#define _MPAHBRAM_CTRL_ADDRFAULTEN_SHIFT 6 /**< Shift value for MPAHBRAM_ADDRFAULTEN */
#define _MPAHBRAM_CTRL_ADDRFAULTEN_MASK 0x40UL /**< Bit mask for MPAHBRAM_ADDRFAULTEN */
#define _MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_CTRL */
#define MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */
/* Bit fields for MPAHBRAM ECCERRADDR0 */
#define _MPAHBRAM_ECCERRADDR0_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR0 */
#define _MPAHBRAM_ECCERRADDR0_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR0 */
#define _MPAHBRAM_ECCERRADDR0_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */
#define _MPAHBRAM_ECCERRADDR0_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */
#define _MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR0 */
#define MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR0*/
/* Bit fields for MPAHBRAM ECCERRADDR1 */
#define _MPAHBRAM_ECCERRADDR1_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR1 */
#define _MPAHBRAM_ECCERRADDR1_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR1 */
#define _MPAHBRAM_ECCERRADDR1_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */
#define _MPAHBRAM_ECCERRADDR1_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */
#define _MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR1 */
#define MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR1*/
/* Bit fields for MPAHBRAM ECCMERRIND */
#define _MPAHBRAM_ECCMERRIND_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCMERRIND */
#define _MPAHBRAM_ECCMERRIND_MASK 0x00000003UL /**< Mask for MPAHBRAM_ECCMERRIND */
#define MPAHBRAM_ECCMERRIND_P0 (0x1UL << 0) /**< Multiple ECC errors on AHB port 0 */
#define _MPAHBRAM_ECCMERRIND_P0_SHIFT 0 /**< Shift value for MPAHBRAM_P0 */
#define _MPAHBRAM_ECCMERRIND_P0_MASK 0x1UL /**< Bit mask for MPAHBRAM_P0 */
#define _MPAHBRAM_ECCMERRIND_P0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */
#define MPAHBRAM_ECCMERRIND_P0_DEFAULT (_MPAHBRAM_ECCMERRIND_P0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/
#define MPAHBRAM_ECCMERRIND_P1 (0x1UL << 1) /**< Multiple ECC errors on AHB port 1 */
#define _MPAHBRAM_ECCMERRIND_P1_SHIFT 1 /**< Shift value for MPAHBRAM_P1 */
#define _MPAHBRAM_ECCMERRIND_P1_MASK 0x2UL /**< Bit mask for MPAHBRAM_P1 */
#define _MPAHBRAM_ECCMERRIND_P1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */
#define MPAHBRAM_ECCMERRIND_P1_DEFAULT (_MPAHBRAM_ECCMERRIND_P1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/
/* Bit fields for MPAHBRAM IF */
#define _MPAHBRAM_IF_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IF */
#define _MPAHBRAM_IF_MASK 0x00000033UL /**< Mask for MPAHBRAM_IF */
#define MPAHBRAM_IF_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Flag */
#define _MPAHBRAM_IF_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */
#define _MPAHBRAM_IF_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */
#define _MPAHBRAM_IF_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */
#define MPAHBRAM_IF_AHB0ERR1B_DEFAULT (_MPAHBRAM_IF_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IF */
#define MPAHBRAM_IF_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Flag */
#define _MPAHBRAM_IF_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */
#define _MPAHBRAM_IF_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */
#define _MPAHBRAM_IF_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */
#define MPAHBRAM_IF_AHB1ERR1B_DEFAULT (_MPAHBRAM_IF_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IF */
#define MPAHBRAM_IF_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Flag */
#define _MPAHBRAM_IF_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */
#define _MPAHBRAM_IF_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */
#define _MPAHBRAM_IF_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */
#define MPAHBRAM_IF_AHB0ERR2B_DEFAULT (_MPAHBRAM_IF_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IF */
#define MPAHBRAM_IF_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Flag */
#define _MPAHBRAM_IF_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */
#define _MPAHBRAM_IF_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */
#define _MPAHBRAM_IF_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */
#define MPAHBRAM_IF_AHB1ERR2B_DEFAULT (_MPAHBRAM_IF_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IF */
/* Bit fields for MPAHBRAM IEN */
#define _MPAHBRAM_IEN_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IEN */
#define _MPAHBRAM_IEN_MASK 0x00000033UL /**< Mask for MPAHBRAM_IEN */
#define MPAHBRAM_IEN_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Enable */
#define _MPAHBRAM_IEN_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */
#define _MPAHBRAM_IEN_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */
#define _MPAHBRAM_IEN_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */
#define MPAHBRAM_IEN_AHB0ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */
#define MPAHBRAM_IEN_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Enable */
#define _MPAHBRAM_IEN_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */
#define _MPAHBRAM_IEN_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */
#define _MPAHBRAM_IEN_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */
#define MPAHBRAM_IEN_AHB1ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */
#define MPAHBRAM_IEN_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Enable */
#define _MPAHBRAM_IEN_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */
#define _MPAHBRAM_IEN_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */
#define _MPAHBRAM_IEN_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */
#define MPAHBRAM_IEN_AHB0ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */
#define MPAHBRAM_IEN_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Enable */
#define _MPAHBRAM_IEN_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */
#define _MPAHBRAM_IEN_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */
#define _MPAHBRAM_IEN_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */
#define MPAHBRAM_IEN_AHB1ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */
/** @} End of group EFR32ZG23_MPAHBRAM_BitFields */
/** @} End of group EFR32ZG23_MPAHBRAM */
/** @} End of group Parts */
#endif /* EFR32ZG23_MPAHBRAM_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 MSC register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_MSC_H
#define EFR32ZG23_MSC_H
#define MSC_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_MSC MSC
* @{
* @brief EFR32ZG23 MSC Register Declaration.
*****************************************************************************/
/** MSC Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP version ID */
__IOM uint32_t READCTRL; /**< Read Control Register */
__IOM uint32_t RDATACTRL; /**< Read Data Control Register */
__IOM uint32_t WRITECTRL; /**< Write Control Register */
__IOM uint32_t WRITECMD; /**< Write Command Register */
__IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
__IOM uint32_t WDATA; /**< Write Data Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
uint32_t RESERVED0[3U]; /**< Reserved for future use */
__IM uint32_t USERDATASIZE; /**< User Data Region Size Register */
__IOM uint32_t CMD; /**< Command Register */
__IOM uint32_t LOCK; /**< Configuration Lock Register */
__IOM uint32_t MISCLOCKWORD; /**< Mass erase and User data page lock word */
uint32_t RESERVED1[3U]; /**< Reserved for future use */
__IOM uint32_t PWRCTRL; /**< Power control register */
uint32_t RESERVED2[51U]; /**< Reserved for future use */
__IOM uint32_t PAGELOCK0; /**< Main space page 0-31 lock word */
__IOM uint32_t PAGELOCK1; /**< Main space page 32-63 lock word */
uint32_t RESERVED3[2U]; /**< Reserved for future use */
uint32_t RESERVED4[4U]; /**< Reserved for future use */
uint32_t RESERVED5[4U]; /**< Reserved for future use */
uint32_t RESERVED6[4U]; /**< Reserved for future use */
uint32_t RESERVED7[4U]; /**< Reserved for future use */
uint32_t RESERVED8[12U]; /**< Reserved for future use */
uint32_t RESERVED9[1U]; /**< Reserved for future use */
uint32_t RESERVED10[8U]; /**< Reserved for future use */
uint32_t RESERVED11[1U]; /**< Reserved for future use */
uint32_t RESERVED12[910U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP version ID */
__IOM uint32_t READCTRL_SET; /**< Read Control Register */
__IOM uint32_t RDATACTRL_SET; /**< Read Data Control Register */
__IOM uint32_t WRITECTRL_SET; /**< Write Control Register */
__IOM uint32_t WRITECMD_SET; /**< Write Command Register */
__IOM uint32_t ADDRB_SET; /**< Page Erase/Write Address Buffer */
__IOM uint32_t WDATA_SET; /**< Write Data Register */
__IM uint32_t STATUS_SET; /**< Status Register */
__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
uint32_t RESERVED13[3U]; /**< Reserved for future use */
__IM uint32_t USERDATASIZE_SET; /**< User Data Region Size Register */
__IOM uint32_t CMD_SET; /**< Command Register */
__IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
__IOM uint32_t MISCLOCKWORD_SET; /**< Mass erase and User data page lock word */
uint32_t RESERVED14[3U]; /**< Reserved for future use */
__IOM uint32_t PWRCTRL_SET; /**< Power control register */
uint32_t RESERVED15[51U]; /**< Reserved for future use */
__IOM uint32_t PAGELOCK0_SET; /**< Main space page 0-31 lock word */
__IOM uint32_t PAGELOCK1_SET; /**< Main space page 32-63 lock word */
uint32_t RESERVED16[2U]; /**< Reserved for future use */
uint32_t RESERVED17[4U]; /**< Reserved for future use */
uint32_t RESERVED18[4U]; /**< Reserved for future use */
uint32_t RESERVED19[4U]; /**< Reserved for future use */
uint32_t RESERVED20[4U]; /**< Reserved for future use */
uint32_t RESERVED21[12U]; /**< Reserved for future use */
uint32_t RESERVED22[1U]; /**< Reserved for future use */
uint32_t RESERVED23[8U]; /**< Reserved for future use */
uint32_t RESERVED24[1U]; /**< Reserved for future use */
uint32_t RESERVED25[910U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP version ID */
__IOM uint32_t READCTRL_CLR; /**< Read Control Register */
__IOM uint32_t RDATACTRL_CLR; /**< Read Data Control Register */
__IOM uint32_t WRITECTRL_CLR; /**< Write Control Register */
__IOM uint32_t WRITECMD_CLR; /**< Write Command Register */
__IOM uint32_t ADDRB_CLR; /**< Page Erase/Write Address Buffer */
__IOM uint32_t WDATA_CLR; /**< Write Data Register */
__IM uint32_t STATUS_CLR; /**< Status Register */
__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
uint32_t RESERVED26[3U]; /**< Reserved for future use */
__IM uint32_t USERDATASIZE_CLR; /**< User Data Region Size Register */
__IOM uint32_t CMD_CLR; /**< Command Register */
__IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
__IOM uint32_t MISCLOCKWORD_CLR; /**< Mass erase and User data page lock word */
uint32_t RESERVED27[3U]; /**< Reserved for future use */
__IOM uint32_t PWRCTRL_CLR; /**< Power control register */
uint32_t RESERVED28[51U]; /**< Reserved for future use */
__IOM uint32_t PAGELOCK0_CLR; /**< Main space page 0-31 lock word */
__IOM uint32_t PAGELOCK1_CLR; /**< Main space page 32-63 lock word */
uint32_t RESERVED29[2U]; /**< Reserved for future use */
uint32_t RESERVED30[4U]; /**< Reserved for future use */
uint32_t RESERVED31[4U]; /**< Reserved for future use */
uint32_t RESERVED32[4U]; /**< Reserved for future use */
uint32_t RESERVED33[4U]; /**< Reserved for future use */
uint32_t RESERVED34[12U]; /**< Reserved for future use */
uint32_t RESERVED35[1U]; /**< Reserved for future use */
uint32_t RESERVED36[8U]; /**< Reserved for future use */
uint32_t RESERVED37[1U]; /**< Reserved for future use */
uint32_t RESERVED38[910U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP version ID */
__IOM uint32_t READCTRL_TGL; /**< Read Control Register */
__IOM uint32_t RDATACTRL_TGL; /**< Read Data Control Register */
__IOM uint32_t WRITECTRL_TGL; /**< Write Control Register */
__IOM uint32_t WRITECMD_TGL; /**< Write Command Register */
__IOM uint32_t ADDRB_TGL; /**< Page Erase/Write Address Buffer */
__IOM uint32_t WDATA_TGL; /**< Write Data Register */
__IM uint32_t STATUS_TGL; /**< Status Register */
__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
uint32_t RESERVED39[3U]; /**< Reserved for future use */
__IM uint32_t USERDATASIZE_TGL; /**< User Data Region Size Register */
__IOM uint32_t CMD_TGL; /**< Command Register */
__IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
__IOM uint32_t MISCLOCKWORD_TGL; /**< Mass erase and User data page lock word */
uint32_t RESERVED40[3U]; /**< Reserved for future use */
__IOM uint32_t PWRCTRL_TGL; /**< Power control register */
uint32_t RESERVED41[51U]; /**< Reserved for future use */
__IOM uint32_t PAGELOCK0_TGL; /**< Main space page 0-31 lock word */
__IOM uint32_t PAGELOCK1_TGL; /**< Main space page 32-63 lock word */
uint32_t RESERVED42[2U]; /**< Reserved for future use */
uint32_t RESERVED43[4U]; /**< Reserved for future use */
uint32_t RESERVED44[4U]; /**< Reserved for future use */
uint32_t RESERVED45[4U]; /**< Reserved for future use */
uint32_t RESERVED46[4U]; /**< Reserved for future use */
uint32_t RESERVED47[12U]; /**< Reserved for future use */
uint32_t RESERVED48[1U]; /**< Reserved for future use */
uint32_t RESERVED49[8U]; /**< Reserved for future use */
uint32_t RESERVED50[1U]; /**< Reserved for future use */
} MSC_TypeDef;
/** @} End of group EFR32ZG23_MSC */
/**************************************************************************//**
* @addtogroup EFR32ZG23_MSC
* @{
* @defgroup EFR32ZG23_MSC_BitFields MSC Bit Fields
* @{
*****************************************************************************/
/* Bit fields for MSC IPVERSION */
#define _MSC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for MSC_IPVERSION */
#define _MSC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MSC_IPVERSION */
#define _MSC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MSC_IPVERSION */
#define _MSC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_IPVERSION */
#define _MSC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_IPVERSION */
#define MSC_IPVERSION_IPVERSION_DEFAULT (_MSC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IPVERSION */
/* Bit fields for MSC READCTRL */
#define _MSC_READCTRL_RESETVALUE 0x00200000UL /**< Default value for MSC_READCTRL */
#define _MSC_READCTRL_MASK 0x00300000UL /**< Mask for MSC_READCTRL */
#define _MSC_READCTRL_MODE_SHIFT 20 /**< Shift value for MSC_MODE */
#define _MSC_READCTRL_MODE_MASK 0x300000UL /**< Bit mask for MSC_MODE */
#define _MSC_READCTRL_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_READCTRL */
#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */
#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */
#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */
#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */
#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 20) /**< Shifted mode WS0 for MSC_READCTRL */
#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 20) /**< Shifted mode WS1 for MSC_READCTRL */
#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 20) /**< Shifted mode WS2 for MSC_READCTRL */
#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 20) /**< Shifted mode WS3 for MSC_READCTRL */
/* Bit fields for MSC RDATACTRL */
#define _MSC_RDATACTRL_RESETVALUE 0x00001000UL /**< Default value for MSC_RDATACTRL */
#define _MSC_RDATACTRL_MASK 0x00001002UL /**< Mask for MSC_RDATACTRL */
#define MSC_RDATACTRL_AFDIS (0x1UL << 1) /**< Automatic Invalidate Disable */
#define _MSC_RDATACTRL_AFDIS_SHIFT 1 /**< Shift value for MSC_AFDIS */
#define _MSC_RDATACTRL_AFDIS_MASK 0x2UL /**< Bit mask for MSC_AFDIS */
#define _MSC_RDATACTRL_AFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RDATACTRL */
#define MSC_RDATACTRL_AFDIS_DEFAULT (_MSC_RDATACTRL_AFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RDATACTRL */
#define MSC_RDATACTRL_DOUTBUFEN (0x1UL << 12) /**< Flash dout pipeline buffer enable */
#define _MSC_RDATACTRL_DOUTBUFEN_SHIFT 12 /**< Shift value for MSC_DOUTBUFEN */
#define _MSC_RDATACTRL_DOUTBUFEN_MASK 0x1000UL /**< Bit mask for MSC_DOUTBUFEN */
#define _MSC_RDATACTRL_DOUTBUFEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_RDATACTRL */
#define MSC_RDATACTRL_DOUTBUFEN_DEFAULT (_MSC_RDATACTRL_DOUTBUFEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_RDATACTRL */
/* Bit fields for MSC WRITECTRL */
#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
#define _MSC_WRITECTRL_MASK 0x00FF000BUL /**< Mask for MSC_WRITECTRL */
#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */
#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */
#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */
#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
#define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Write */
#define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */
#define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */
#define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
#define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
#define _MSC_WRITECTRL_RANGECOUNT_SHIFT 16 /**< Shift value for MSC_RANGECOUNT */
#define _MSC_WRITECTRL_RANGECOUNT_MASK 0xFF0000UL /**< Bit mask for MSC_RANGECOUNT */
#define _MSC_WRITECTRL_RANGECOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
#define MSC_WRITECTRL_RANGECOUNT_DEFAULT (_MSC_WRITECTRL_RANGECOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
/* Bit fields for MSC WRITECMD */
#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
#define _MSC_WRITECMD_MASK 0x00001136UL /**< Mask for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */
#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */
#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */
#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */
#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */
#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */
#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASERANGE (0x1UL << 4) /**< Erase range of pages */
#define _MSC_WRITECMD_ERASERANGE_SHIFT 4 /**< Shift value for MSC_ERASERANGE */
#define _MSC_WRITECMD_ERASERANGE_MASK 0x10UL /**< Bit mask for MSC_ERASERANGE */
#define _MSC_WRITECMD_ERASERANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASERANGE_DEFAULT (_MSC_WRITECMD_ERASERANGE_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */
#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */
#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */
#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
/* Bit fields for MSC ADDRB */
#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */
#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */
#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */
#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */
#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */
#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
/* Bit fields for MSC WDATA */
#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */
#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */
#define _MSC_WDATA_DATAW_SHIFT 0 /**< Shift value for MSC_DATAW */
#define _MSC_WDATA_DATAW_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_DATAW */
#define _MSC_WDATA_DATAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */
#define MSC_WDATA_DATAW_DEFAULT (_MSC_WDATA_DATAW_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
/* Bit fields for MSC STATUS */
#define _MSC_STATUS_RESETVALUE 0x08000008UL /**< Default value for MSC_STATUS */
#define _MSC_STATUS_MASK 0xF90100FFUL /**< Mask for MSC_STATUS */
#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */
#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */
#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */
#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */
#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */
#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */
#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */
#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */
#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */
#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */
#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */
#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */
#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_ERASEABORTED (0x1UL << 4) /**< The Current Flash Erase Operation Aborte */
#define _MSC_STATUS_ERASEABORTED_SHIFT 4 /**< Shift value for MSC_ERASEABORTED */
#define _MSC_STATUS_ERASEABORTED_MASK 0x10UL /**< Bit mask for MSC_ERASEABORTED */
#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_PENDING (0x1UL << 5) /**< Write command is in queue */
#define _MSC_STATUS_PENDING_SHIFT 5 /**< Shift value for MSC_PENDING */
#define _MSC_STATUS_PENDING_MASK 0x20UL /**< Bit mask for MSC_PENDING */
#define _MSC_STATUS_PENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_PENDING_DEFAULT (_MSC_STATUS_PENDING_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_TIMEOUT (0x1UL << 6) /**< Write command timeout flag */
#define _MSC_STATUS_TIMEOUT_SHIFT 6 /**< Shift value for MSC_TIMEOUT */
#define _MSC_STATUS_TIMEOUT_MASK 0x40UL /**< Bit mask for MSC_TIMEOUT */
#define _MSC_STATUS_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_TIMEOUT_DEFAULT (_MSC_STATUS_TIMEOUT_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_RANGEPARTIAL (0x1UL << 7) /**< EraseRange with skipped locked pages */
#define _MSC_STATUS_RANGEPARTIAL_SHIFT 7 /**< Shift value for MSC_RANGEPARTIAL */
#define _MSC_STATUS_RANGEPARTIAL_MASK 0x80UL /**< Bit mask for MSC_RANGEPARTIAL */
#define _MSC_STATUS_RANGEPARTIAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_RANGEPARTIAL_DEFAULT (_MSC_STATUS_RANGEPARTIAL_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_REGLOCK (0x1UL << 16) /**< Register Lock Status */
#define _MSC_STATUS_REGLOCK_SHIFT 16 /**< Shift value for MSC_REGLOCK */
#define _MSC_STATUS_REGLOCK_MASK 0x10000UL /**< Bit mask for MSC_REGLOCK */
#define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define _MSC_STATUS_REGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_STATUS */
#define _MSC_STATUS_REGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_STATUS */
#define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_REGLOCK_UNLOCKED (_MSC_STATUS_REGLOCK_UNLOCKED << 16) /**< Shifted mode UNLOCKED for MSC_STATUS */
#define MSC_STATUS_REGLOCK_LOCKED (_MSC_STATUS_REGLOCK_LOCKED << 16) /**< Shifted mode LOCKED for MSC_STATUS */
#define MSC_STATUS_PWRON (0x1UL << 24) /**< Flash power on status */
#define _MSC_STATUS_PWRON_SHIFT 24 /**< Shift value for MSC_PWRON */
#define _MSC_STATUS_PWRON_MASK 0x1000000UL /**< Bit mask for MSC_PWRON */
#define _MSC_STATUS_PWRON_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_PWRON_DEFAULT (_MSC_STATUS_PWRON_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_WREADY (0x1UL << 27) /**< Flash Write Ready */
#define _MSC_STATUS_WREADY_SHIFT 27 /**< Shift value for MSC_WREADY */
#define _MSC_STATUS_WREADY_MASK 0x8000000UL /**< Bit mask for MSC_WREADY */
#define _MSC_STATUS_WREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_WREADY_DEFAULT (_MSC_STATUS_WREADY_DEFAULT << 27) /**< Shifted mode DEFAULT for MSC_STATUS */
#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */
#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */
#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */
/* Bit fields for MSC IF */
#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */
#define _MSC_IF_MASK 0x00000307UL /**< Mask for MSC_IF */
#define MSC_IF_ERASE (0x1UL << 0) /**< Host Erase Done Interrupt Read Flag */
#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
#define MSC_IF_WRITE (0x1UL << 1) /**< Host Write Done Interrupt Read Flag */
#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
#define MSC_IF_WDATAOV (0x1UL << 2) /**< Host write buffer overflow */
#define _MSC_IF_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */
#define _MSC_IF_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */
#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */
#define MSC_IF_PWRUPF (0x1UL << 8) /**< Flash Power Up Sequence Complete Flag */
#define _MSC_IF_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */
#define _MSC_IF_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */
#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */
#define MSC_IF_PWROFF (0x1UL << 9) /**< Flash Power Off Sequence Complete Flag */
#define _MSC_IF_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */
#define _MSC_IF_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */
#define _MSC_IF_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_PWROFF_DEFAULT (_MSC_IF_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IF */
/* Bit fields for MSC IEN */
#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */
#define _MSC_IEN_MASK 0x00000307UL /**< Mask for MSC_IEN */
#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt enable */
#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt enable */
#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
#define MSC_IEN_WDATAOV (0x1UL << 2) /**< write data buffer overflow irq enable */
#define _MSC_IEN_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */
#define _MSC_IEN_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */
#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */
#define MSC_IEN_PWRUPF (0x1UL << 8) /**< Flash Power Up Seq done irq enable */
#define _MSC_IEN_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */
#define _MSC_IEN_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */
#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */
#define MSC_IEN_PWROFF (0x1UL << 9) /**< Flash Power Off Seq done irq enable */
#define _MSC_IEN_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */
#define _MSC_IEN_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */
#define _MSC_IEN_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_PWROFF_DEFAULT (_MSC_IEN_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IEN */
/* Bit fields for MSC USERDATASIZE */
#define _MSC_USERDATASIZE_RESETVALUE 0x00000004UL /**< Default value for MSC_USERDATASIZE */
#define _MSC_USERDATASIZE_MASK 0x0000003FUL /**< Mask for MSC_USERDATASIZE */
#define _MSC_USERDATASIZE_USERDATASIZE_SHIFT 0 /**< Shift value for MSC_USERDATASIZE */
#define _MSC_USERDATASIZE_USERDATASIZE_MASK 0x3FUL /**< Bit mask for MSC_USERDATASIZE */
#define _MSC_USERDATASIZE_USERDATASIZE_DEFAULT 0x00000004UL /**< Mode DEFAULT for MSC_USERDATASIZE */
#define MSC_USERDATASIZE_USERDATASIZE_DEFAULT (_MSC_USERDATASIZE_USERDATASIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_USERDATASIZE */
/* Bit fields for MSC CMD */
#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */
#define _MSC_CMD_MASK 0x00000011UL /**< Mask for MSC_CMD */
#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */
#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */
#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */
#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
#define MSC_CMD_PWROFF (0x1UL << 4) /**< Flash power off/sleep command */
#define _MSC_CMD_PWROFF_SHIFT 4 /**< Shift value for MSC_PWROFF */
#define _MSC_CMD_PWROFF_MASK 0x10UL /**< Bit mask for MSC_PWROFF */
#define _MSC_CMD_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
#define MSC_CMD_PWROFF_DEFAULT (_MSC_CMD_PWROFF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CMD */
/* Bit fields for MSC LOCK */
#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */
#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
/* Bit fields for MSC MISCLOCKWORD */
#define _MSC_MISCLOCKWORD_RESETVALUE 0x00000011UL /**< Default value for MSC_MISCLOCKWORD */
#define _MSC_MISCLOCKWORD_MASK 0x00000011UL /**< Mask for MSC_MISCLOCKWORD */
#define MSC_MISCLOCKWORD_MELOCKBIT (0x1UL << 0) /**< Mass Erase Lock */
#define _MSC_MISCLOCKWORD_MELOCKBIT_SHIFT 0 /**< Shift value for MSC_MELOCKBIT */
#define _MSC_MISCLOCKWORD_MELOCKBIT_MASK 0x1UL /**< Bit mask for MSC_MELOCKBIT */
#define _MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */
#define MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */
#define MSC_MISCLOCKWORD_UDLOCKBIT (0x1UL << 4) /**< User Data Lock */
#define _MSC_MISCLOCKWORD_UDLOCKBIT_SHIFT 4 /**< Shift value for MSC_UDLOCKBIT */
#define _MSC_MISCLOCKWORD_UDLOCKBIT_MASK 0x10UL /**< Bit mask for MSC_UDLOCKBIT */
#define _MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */
#define MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */
/* Bit fields for MSC PWRCTRL */
#define _MSC_PWRCTRL_RESETVALUE 0x00100002UL /**< Default value for MSC_PWRCTRL */
#define _MSC_PWRCTRL_MASK 0x00FF0013UL /**< Mask for MSC_PWRCTRL */
#define MSC_PWRCTRL_PWROFFONEM1ENTRY (0x1UL << 0) /**< Power down Flash macro when enter EM1 */
#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_SHIFT 0 /**< Shift value for MSC_PWROFFONEM1ENTRY */
#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_MASK 0x1UL /**< Bit mask for MSC_PWROFFONEM1ENTRY */
#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */
#define MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PWRCTRL */
#define MSC_PWRCTRL_PWROFFONEM1PENTRY (0x1UL << 1) /**< Power down Flash macro when enter EM1P */
#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_SHIFT 1 /**< Shift value for MSC_PWROFFONEM1PENTRY */
#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_MASK 0x2UL /**< Bit mask for MSC_PWROFFONEM1PENTRY */
#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_PWRCTRL */
#define MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_PWRCTRL */
#define MSC_PWRCTRL_PWROFFENTRYAGAIN (0x1UL << 4) /**< POWER down flash again in EM1/EM1p */
#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_SHIFT 4 /**< Shift value for MSC_PWROFFENTRYAGAIN */
#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_MASK 0x10UL /**< Bit mask for MSC_PWROFFENTRYAGAIN */
#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */
#define MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT (_MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_PWRCTRL */
#define _MSC_PWRCTRL_PWROFFDLY_SHIFT 16 /**< Shift value for MSC_PWROFFDLY */
#define _MSC_PWRCTRL_PWROFFDLY_MASK 0xFF0000UL /**< Bit mask for MSC_PWROFFDLY */
#define _MSC_PWRCTRL_PWROFFDLY_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_PWRCTRL */
#define MSC_PWRCTRL_PWROFFDLY_DEFAULT (_MSC_PWRCTRL_PWROFFDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_PWRCTRL */
/* Bit fields for MSC PAGELOCK0 */
#define _MSC_PAGELOCK0_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK0 */
#define _MSC_PAGELOCK0_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK0 */
#define _MSC_PAGELOCK0_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */
#define _MSC_PAGELOCK0_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */
#define _MSC_PAGELOCK0_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK0 */
#define MSC_PAGELOCK0_LOCKBIT_DEFAULT (_MSC_PAGELOCK0_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK0 */
/* Bit fields for MSC PAGELOCK1 */
#define _MSC_PAGELOCK1_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK1 */
#define _MSC_PAGELOCK1_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK1 */
#define _MSC_PAGELOCK1_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */
#define _MSC_PAGELOCK1_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */
#define _MSC_PAGELOCK1_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK1 */
#define MSC_PAGELOCK1_LOCKBIT_DEFAULT (_MSC_PAGELOCK1_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK1 */
/** @} End of group EFR32ZG23_MSC_BitFields */
/** @} End of group EFR32ZG23_MSC */
/** @} End of group Parts */
#endif /* EFR32ZG23_MSC_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 PCNT register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_PCNT_H
#define EFR32ZG23_PCNT_H
#define PCNT_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_PCNT PCNT
* @{
* @brief EFR32ZG23 PCNT Register Declaration.
*****************************************************************************/
/** PCNT Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP version ID */
__IOM uint32_t EN; /**< Module Enable Register */
__IOM uint32_t SWRST; /**< Software Reset Register */
__IOM uint32_t CFG; /**< Configuration Register */
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IM uint32_t CNT; /**< Counter Value Register */
__IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */
__IOM uint32_t TOP; /**< Top Value Register */
__IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */
__IOM uint32_t OVSCTRL; /**< Oversampling Control Register */
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
__IOM uint32_t LOCK; /**< Configuration Lock Register */
uint32_t RESERVED0[1008U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP version ID */
__IOM uint32_t EN_SET; /**< Module Enable Register */
__IOM uint32_t SWRST_SET; /**< Software Reset Register */
__IOM uint32_t CFG_SET; /**< Configuration Register */
__IOM uint32_t CTRL_SET; /**< Control Register */
__IOM uint32_t CMD_SET; /**< Command Register */
__IM uint32_t STATUS_SET; /**< Status Register */
__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
__IM uint32_t CNT_SET; /**< Counter Value Register */
__IM uint32_t AUXCNT_SET; /**< Auxiliary Counter Value Register */
__IOM uint32_t TOP_SET; /**< Top Value Register */
__IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */
__IOM uint32_t OVSCTRL_SET; /**< Oversampling Control Register */
__IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */
__IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
uint32_t RESERVED1[1008U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP version ID */
__IOM uint32_t EN_CLR; /**< Module Enable Register */
__IOM uint32_t SWRST_CLR; /**< Software Reset Register */
__IOM uint32_t CFG_CLR; /**< Configuration Register */
__IOM uint32_t CTRL_CLR; /**< Control Register */
__IOM uint32_t CMD_CLR; /**< Command Register */
__IM uint32_t STATUS_CLR; /**< Status Register */
__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
__IM uint32_t CNT_CLR; /**< Counter Value Register */
__IM uint32_t AUXCNT_CLR; /**< Auxiliary Counter Value Register */
__IOM uint32_t TOP_CLR; /**< Top Value Register */
__IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */
__IOM uint32_t OVSCTRL_CLR; /**< Oversampling Control Register */
__IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */
__IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
uint32_t RESERVED2[1008U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP version ID */
__IOM uint32_t EN_TGL; /**< Module Enable Register */
__IOM uint32_t SWRST_TGL; /**< Software Reset Register */
__IOM uint32_t CFG_TGL; /**< Configuration Register */
__IOM uint32_t CTRL_TGL; /**< Control Register */
__IOM uint32_t CMD_TGL; /**< Command Register */
__IM uint32_t STATUS_TGL; /**< Status Register */
__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
__IM uint32_t CNT_TGL; /**< Counter Value Register */
__IM uint32_t AUXCNT_TGL; /**< Auxiliary Counter Value Register */
__IOM uint32_t TOP_TGL; /**< Top Value Register */
__IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */
__IOM uint32_t OVSCTRL_TGL; /**< Oversampling Control Register */
__IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */
__IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
} PCNT_TypeDef;
/** @} End of group EFR32ZG23_PCNT */
/**************************************************************************//**
* @addtogroup EFR32ZG23_PCNT
* @{
* @defgroup EFR32ZG23_PCNT_BitFields PCNT Bit Fields
* @{
*****************************************************************************/
/* Bit fields for PCNT IPVERSION */
#define _PCNT_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PCNT_IPVERSION */
#define _PCNT_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PCNT_IPVERSION */
#define _PCNT_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PCNT_IPVERSION */
#define _PCNT_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PCNT_IPVERSION */
#define _PCNT_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PCNT_IPVERSION */
#define PCNT_IPVERSION_IPVERSION_DEFAULT (_PCNT_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IPVERSION */
/* Bit fields for PCNT EN */
#define _PCNT_EN_RESETVALUE 0x00000000UL /**< Default value for PCNT_EN */
#define _PCNT_EN_MASK 0x00000003UL /**< Mask for PCNT_EN */
#define PCNT_EN_EN (0x1UL << 0) /**< PCNT Module Enable */
#define _PCNT_EN_EN_SHIFT 0 /**< Shift value for PCNT_EN */
#define _PCNT_EN_EN_MASK 0x1UL /**< Bit mask for PCNT_EN */
#define _PCNT_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */
#define PCNT_EN_EN_DEFAULT (_PCNT_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_EN */
#define PCNT_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
#define _PCNT_EN_DISABLING_SHIFT 1 /**< Shift value for PCNT_DISABLING */
#define _PCNT_EN_DISABLING_MASK 0x2UL /**< Bit mask for PCNT_DISABLING */
#define _PCNT_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */
#define PCNT_EN_DISABLING_DEFAULT (_PCNT_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_EN */
/* Bit fields for PCNT SWRST */
#define _PCNT_SWRST_RESETVALUE 0x00000000UL /**< Default value for PCNT_SWRST */
#define _PCNT_SWRST_MASK 0x00000003UL /**< Mask for PCNT_SWRST */
#define PCNT_SWRST_SWRST (0x1UL << 0) /**< Software reset command */
#define _PCNT_SWRST_SWRST_SHIFT 0 /**< Shift value for PCNT_SWRST */
#define _PCNT_SWRST_SWRST_MASK 0x1UL /**< Bit mask for PCNT_SWRST */
#define _PCNT_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */
#define PCNT_SWRST_SWRST_DEFAULT (_PCNT_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SWRST */
#define PCNT_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */
#define _PCNT_SWRST_RESETTING_SHIFT 1 /**< Shift value for PCNT_RESETTING */
#define _PCNT_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for PCNT_RESETTING */
#define _PCNT_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */
#define PCNT_SWRST_RESETTING_DEFAULT (_PCNT_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SWRST */
/* Bit fields for PCNT CFG */
#define _PCNT_CFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_CFG */
#define _PCNT_CFG_MASK 0x00000377UL /**< Mask for PCNT_CFG */
#define _PCNT_CFG_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */
#define _PCNT_CFG_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */
#define _PCNT_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */
#define _PCNT_CFG_MODE_OVSSINGLE 0x00000000UL /**< Mode OVSSINGLE for PCNT_CFG */
#define _PCNT_CFG_MODE_EXTCLKSINGLE 0x00000001UL /**< Mode EXTCLKSINGLE for PCNT_CFG */
#define _PCNT_CFG_MODE_EXTCLKQUAD 0x00000002UL /**< Mode EXTCLKQUAD for PCNT_CFG */
#define _PCNT_CFG_MODE_OVSQUAD1X 0x00000003UL /**< Mode OVSQUAD1X for PCNT_CFG */
#define _PCNT_CFG_MODE_OVSQUAD2X 0x00000004UL /**< Mode OVSQUAD2X for PCNT_CFG */
#define _PCNT_CFG_MODE_OVSQUAD4X 0x00000005UL /**< Mode OVSQUAD4X for PCNT_CFG */
#define PCNT_CFG_MODE_DEFAULT (_PCNT_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CFG */
#define PCNT_CFG_MODE_OVSSINGLE (_PCNT_CFG_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CFG */
#define PCNT_CFG_MODE_EXTCLKSINGLE (_PCNT_CFG_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CFG */
#define PCNT_CFG_MODE_EXTCLKQUAD (_PCNT_CFG_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CFG */
#define PCNT_CFG_MODE_OVSQUAD1X (_PCNT_CFG_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CFG */
#define PCNT_CFG_MODE_OVSQUAD2X (_PCNT_CFG_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CFG */
#define PCNT_CFG_MODE_OVSQUAD4X (_PCNT_CFG_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CFG */
#define PCNT_CFG_DEBUGHALT (0x1UL << 4) /**< Debug Mode Halt Enable */
#define _PCNT_CFG_DEBUGHALT_SHIFT 4 /**< Shift value for PCNT_DEBUGHALT */
#define _PCNT_CFG_DEBUGHALT_MASK 0x10UL /**< Bit mask for PCNT_DEBUGHALT */
#define _PCNT_CFG_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */
#define _PCNT_CFG_DEBUGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CFG */
#define _PCNT_CFG_DEBUGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for PCNT_CFG */
#define PCNT_CFG_DEBUGHALT_DEFAULT (_PCNT_CFG_DEBUGHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CFG */
#define PCNT_CFG_DEBUGHALT_DISABLE (_PCNT_CFG_DEBUGHALT_DISABLE << 4) /**< Shifted mode DISABLE for PCNT_CFG */
#define PCNT_CFG_DEBUGHALT_ENABLE (_PCNT_CFG_DEBUGHALT_ENABLE << 4) /**< Shifted mode ENABLE for PCNT_CFG */
#define PCNT_CFG_FILTEN (0x1UL << 5) /**< Enable Digital Pulse Width Filter */
#define _PCNT_CFG_FILTEN_SHIFT 5 /**< Shift value for PCNT_FILTEN */
#define _PCNT_CFG_FILTEN_MASK 0x20UL /**< Bit mask for PCNT_FILTEN */
#define _PCNT_CFG_FILTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */
#define PCNT_CFG_FILTEN_DEFAULT (_PCNT_CFG_FILTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CFG */
#define PCNT_CFG_HYST (0x1UL << 6) /**< Enable Hysteresis */
#define _PCNT_CFG_HYST_SHIFT 6 /**< Shift value for PCNT_HYST */
#define _PCNT_CFG_HYST_MASK 0x40UL /**< Bit mask for PCNT_HYST */
#define _PCNT_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */
#define PCNT_CFG_HYST_DEFAULT (_PCNT_CFG_HYST_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CFG */
#define PCNT_CFG_S0PRSEN (0x1UL << 8) /**< S0IN PRS Enable */
#define _PCNT_CFG_S0PRSEN_SHIFT 8 /**< Shift value for PCNT_S0PRSEN */
#define _PCNT_CFG_S0PRSEN_MASK 0x100UL /**< Bit mask for PCNT_S0PRSEN */
#define _PCNT_CFG_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */
#define PCNT_CFG_S0PRSEN_DEFAULT (_PCNT_CFG_S0PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CFG */
#define PCNT_CFG_S1PRSEN (0x1UL << 9) /**< S1IN PRS Enable */
#define _PCNT_CFG_S1PRSEN_SHIFT 9 /**< Shift value for PCNT_S1PRSEN */
#define _PCNT_CFG_S1PRSEN_MASK 0x200UL /**< Bit mask for PCNT_S1PRSEN */
#define _PCNT_CFG_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */
#define PCNT_CFG_S1PRSEN_DEFAULT (_PCNT_CFG_S1PRSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CFG */
/* Bit fields for PCNT CTRL */
#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */
#define _PCNT_CTRL_MASK 0x000000F7UL /**< Mask for PCNT_CTRL */
#define PCNT_CTRL_S1CDIR (0x1UL << 0) /**< Count Direction Determined By S1 */
#define _PCNT_CTRL_S1CDIR_SHIFT 0 /**< Shift value for PCNT_S1CDIR */
#define _PCNT_CTRL_S1CDIR_MASK 0x1UL /**< Bit mask for PCNT_S1CDIR */
#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_CNTDIR (0x1UL << 1) /**< Non-Quadrature Mode Counter Direction Co */
#define _PCNT_CTRL_CNTDIR_SHIFT 1 /**< Shift value for PCNT_CNTDIR */
#define _PCNT_CTRL_CNTDIR_MASK 0x2UL /**< Bit mask for PCNT_CNTDIR */
#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */
#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */
#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 1) /**< Shifted mode UP for PCNT_CTRL */
#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 1) /**< Shifted mode DOWN for PCNT_CTRL */
#define PCNT_CTRL_EDGE (0x1UL << 2) /**< Edge Select */
#define _PCNT_CTRL_EDGE_SHIFT 2 /**< Shift value for PCNT_EDGE */
#define _PCNT_CTRL_EDGE_MASK 0x4UL /**< Bit mask for PCNT_EDGE */
#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */
#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */
#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 2) /**< Shifted mode POS for PCNT_CTRL */
#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 2) /**< Shifted mode NEG for PCNT_CTRL */
#define _PCNT_CTRL_CNTEV_SHIFT 4 /**< Shift value for PCNT_CNTEV */
#define _PCNT_CTRL_CNTEV_MASK 0x30UL /**< Bit mask for PCNT_CNTEV */
#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */
#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */
#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */
#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 4) /**< Shifted mode BOTH for PCNT_CTRL */
#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 4) /**< Shifted mode UP for PCNT_CTRL */
#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 4) /**< Shifted mode DOWN for PCNT_CTRL */
#define _PCNT_CTRL_AUXCNTEV_SHIFT 6 /**< Shift value for PCNT_AUXCNTEV */
#define _PCNT_CTRL_AUXCNTEV_MASK 0xC0UL /**< Bit mask for PCNT_AUXCNTEV */
#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */
#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */
#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 6) /**< Shifted mode BOTH for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 6) /**< Shifted mode UP for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 6) /**< Shifted mode DOWN for PCNT_CTRL */
/* Bit fields for PCNT CMD */
#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */
#define _PCNT_CMD_MASK 0x00000F17UL /**< Mask for PCNT_CMD */
#define PCNT_CMD_CORERST (0x1UL << 0) /**< PCNT Clock Domain Reset */
#define _PCNT_CMD_CORERST_SHIFT 0 /**< Shift value for PCNT_CORERST */
#define _PCNT_CMD_CORERST_MASK 0x1UL /**< Bit mask for PCNT_CORERST */
#define _PCNT_CMD_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_CORERST_DEFAULT (_PCNT_CMD_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_CNTRST (0x1UL << 1) /**< CNT Reset */
#define _PCNT_CMD_CNTRST_SHIFT 1 /**< Shift value for PCNT_CNTRST */
#define _PCNT_CMD_CNTRST_MASK 0x2UL /**< Bit mask for PCNT_CNTRST */
#define _PCNT_CMD_CNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_CNTRST_DEFAULT (_PCNT_CMD_CNTRST_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_AUXCNTRST (0x1UL << 2) /**< AUXCNT Reset */
#define _PCNT_CMD_AUXCNTRST_SHIFT 2 /**< Shift value for PCNT_AUXCNTRST */
#define _PCNT_CMD_AUXCNTRST_MASK 0x4UL /**< Bit mask for PCNT_AUXCNTRST */
#define _PCNT_CMD_AUXCNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_AUXCNTRST_DEFAULT (_PCNT_CMD_AUXCNTRST_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_LCNTIM (0x1UL << 4) /**< Load CNT Immediately */
#define _PCNT_CMD_LCNTIM_SHIFT 4 /**< Shift value for PCNT_LCNTIM */
#define _PCNT_CMD_LCNTIM_MASK 0x10UL /**< Bit mask for PCNT_LCNTIM */
#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_STARTCNT (0x1UL << 8) /**< Start Main Counter */
#define _PCNT_CMD_STARTCNT_SHIFT 8 /**< Shift value for PCNT_STARTCNT */
#define _PCNT_CMD_STARTCNT_MASK 0x100UL /**< Bit mask for PCNT_STARTCNT */
#define _PCNT_CMD_STARTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_STARTCNT_DEFAULT (_PCNT_CMD_STARTCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_STARTAUXCNT (0x1UL << 9) /**< Start Aux Counter */
#define _PCNT_CMD_STARTAUXCNT_SHIFT 9 /**< Shift value for PCNT_STARTAUXCNT */
#define _PCNT_CMD_STARTAUXCNT_MASK 0x200UL /**< Bit mask for PCNT_STARTAUXCNT */
#define _PCNT_CMD_STARTAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_STARTAUXCNT_DEFAULT (_PCNT_CMD_STARTAUXCNT_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_STOPCNT (0x1UL << 10) /**< Stop Main Counter */
#define _PCNT_CMD_STOPCNT_SHIFT 10 /**< Shift value for PCNT_STOPCNT */
#define _PCNT_CMD_STOPCNT_MASK 0x400UL /**< Bit mask for PCNT_STOPCNT */
#define _PCNT_CMD_STOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_STOPCNT_DEFAULT (_PCNT_CMD_STOPCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_STOPAUXCNT (0x1UL << 11) /**< Stop Aux Counter */
#define _PCNT_CMD_STOPAUXCNT_SHIFT 11 /**< Shift value for PCNT_STOPAUXCNT */
#define _PCNT_CMD_STOPAUXCNT_MASK 0x800UL /**< Bit mask for PCNT_STOPAUXCNT */
#define _PCNT_CMD_STOPAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_STOPAUXCNT_DEFAULT (_PCNT_CMD_STOPAUXCNT_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_CMD */
/* Bit fields for PCNT STATUS */
#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */
#define _PCNT_STATUS_MASK 0x0000001FUL /**< Mask for PCNT_STATUS */
#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */
#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */
#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */
#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */
#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */
#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */
#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */
#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */
#define PCNT_STATUS_TOPBV (0x1UL << 1) /**< TOP Buffer Valid */
#define _PCNT_STATUS_TOPBV_SHIFT 1 /**< Shift value for PCNT_TOPBV */
#define _PCNT_STATUS_TOPBV_MASK 0x2UL /**< Bit mask for PCNT_TOPBV */
#define _PCNT_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
#define PCNT_STATUS_TOPBV_DEFAULT (_PCNT_STATUS_TOPBV_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_STATUS */
#define PCNT_STATUS_PCNTLOCKSTATUS (0x1UL << 2) /**< Lock Status */
#define _PCNT_STATUS_PCNTLOCKSTATUS_SHIFT 2 /**< Shift value for PCNT_PCNTLOCKSTATUS */
#define _PCNT_STATUS_PCNTLOCKSTATUS_MASK 0x4UL /**< Bit mask for PCNT_PCNTLOCKSTATUS */
#define _PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
#define _PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for PCNT_STATUS */
#define _PCNT_STATUS_PCNTLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for PCNT_STATUS */
#define PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT (_PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_STATUS */
#define PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED << 2) /**< Shifted mode UNLOCKED for PCNT_STATUS */
#define PCNT_STATUS_PCNTLOCKSTATUS_LOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_LOCKED << 2) /**< Shifted mode LOCKED for PCNT_STATUS */
#define PCNT_STATUS_CNTRUNNING (0x1UL << 3) /**< Main Counter running status */
#define _PCNT_STATUS_CNTRUNNING_SHIFT 3 /**< Shift value for PCNT_CNTRUNNING */
#define _PCNT_STATUS_CNTRUNNING_MASK 0x8UL /**< Bit mask for PCNT_CNTRUNNING */
#define _PCNT_STATUS_CNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
#define PCNT_STATUS_CNTRUNNING_DEFAULT (_PCNT_STATUS_CNTRUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_STATUS */
#define PCNT_STATUS_AUXCNTRUNNING (0x1UL << 4) /**< Aux Counter running status */
#define _PCNT_STATUS_AUXCNTRUNNING_SHIFT 4 /**< Shift value for PCNT_AUXCNTRUNNING */
#define _PCNT_STATUS_AUXCNTRUNNING_MASK 0x10UL /**< Bit mask for PCNT_AUXCNTRUNNING */
#define _PCNT_STATUS_AUXCNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
#define PCNT_STATUS_AUXCNTRUNNING_DEFAULT (_PCNT_STATUS_AUXCNTRUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_STATUS */
/* Bit fields for PCNT IF */
#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */
#define _PCNT_IF_MASK 0x0000001FUL /**< Mask for PCNT_IF */
#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */
#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */
#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */
#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */
#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */
#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */
#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */
#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */
#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */
#define PCNT_IF_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */
#define _PCNT_IF_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */
#define _PCNT_IF_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */
#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */
/* Bit fields for PCNT IEN */
#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */
#define _PCNT_IEN_MASK 0x0000001FUL /**< Mask for PCNT_IEN */
#define PCNT_IEN_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */
#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */
#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */
#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */
#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */
#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */
#define _PCNT_IEN_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */
#define _PCNT_IEN_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */
#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */
/* Bit fields for PCNT CNT */
#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */
#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */
#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */
#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */
#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */
#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */
/* Bit fields for PCNT AUXCNT */
#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */
#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */
#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */
#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */
#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */
#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */
/* Bit fields for PCNT TOP */
#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */
#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */
#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */
#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */
#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */
#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */
/* Bit fields for PCNT TOPB */
#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */
#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */
#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */
#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */
#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */
#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */
/* Bit fields for PCNT OVSCTRL */
#define _PCNT_OVSCTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCTRL */
#define _PCNT_OVSCTRL_MASK 0x000010FFUL /**< Mask for PCNT_OVSCTRL */
#define _PCNT_OVSCTRL_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */
#define _PCNT_OVSCTRL_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */
#define _PCNT_OVSCTRL_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */
#define PCNT_OVSCTRL_FILTLEN_DEFAULT (_PCNT_OVSCTRL_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */
#define PCNT_OVSCTRL_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */
#define _PCNT_OVSCTRL_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */
#define _PCNT_OVSCTRL_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */
#define _PCNT_OVSCTRL_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */
#define PCNT_OVSCTRL_FLUTTERRM_DEFAULT (_PCNT_OVSCTRL_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */
/* Bit fields for PCNT SYNCBUSY */
#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */
#define _PCNT_SYNCBUSY_MASK 0x0000001FUL /**< Mask for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */
#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */
#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */
#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */
#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_TOP (0x1UL << 2) /**< TOP Register Busy */
#define _PCNT_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for PCNT_TOP */
#define _PCNT_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for PCNT_TOP */
#define _PCNT_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_TOP_DEFAULT (_PCNT_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_TOPB (0x1UL << 3) /**< TOPB Register Busy */
#define _PCNT_SYNCBUSY_TOPB_SHIFT 3 /**< Shift value for PCNT_TOPB */
#define _PCNT_SYNCBUSY_TOPB_MASK 0x8UL /**< Bit mask for PCNT_TOPB */
#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_OVSCTRL (0x1UL << 4) /**< OVSCTRL Register Busy */
#define _PCNT_SYNCBUSY_OVSCTRL_SHIFT 4 /**< Shift value for PCNT_OVSCTRL */
#define _PCNT_SYNCBUSY_OVSCTRL_MASK 0x10UL /**< Bit mask for PCNT_OVSCTRL */
#define _PCNT_SYNCBUSY_OVSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_OVSCTRL_DEFAULT (_PCNT_SYNCBUSY_OVSCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
/* Bit fields for PCNT LOCK */
#define _PCNT_LOCK_RESETVALUE 0x00000000UL /**< Default value for PCNT_LOCK */
#define _PCNT_LOCK_MASK 0x0000FFFFUL /**< Mask for PCNT_LOCK */
#define _PCNT_LOCK_PCNTLOCKKEY_SHIFT 0 /**< Shift value for PCNT_PCNTLOCKKEY */
#define _PCNT_LOCK_PCNTLOCKKEY_MASK 0xFFFFUL /**< Bit mask for PCNT_PCNTLOCKKEY */
#define _PCNT_LOCK_PCNTLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_LOCK */
#define _PCNT_LOCK_PCNTLOCKKEY_UNLOCK 0x0000A7E0UL /**< Mode UNLOCK for PCNT_LOCK */
#define PCNT_LOCK_PCNTLOCKKEY_DEFAULT (_PCNT_LOCK_PCNTLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_LOCK */
#define PCNT_LOCK_PCNTLOCKKEY_UNLOCK (_PCNT_LOCK_PCNTLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for PCNT_LOCK */
/** @} End of group EFR32ZG23_PCNT_BitFields */
/** @} End of group EFR32ZG23_PCNT */
/** @} End of group Parts */
#endif /* EFR32ZG23_PCNT_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 PFMXPPRF register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_PFMXPPRF_H
#define EFR32ZG23_PFMXPPRF_H
#define PFMXPPRF_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_PFMXPPRF PFMXPPRF
* @{
* @brief EFR32ZG23 PFMXPPRF Register Declaration.
*****************************************************************************/
/** PFMXPPRF Register Declaration. */
typedef struct {
__IOM uint32_t RFIMDCDCCTRL0; /**< New Register */
__IOM uint32_t RFIMDCDCCTRL1; /**< New Register */
__IOM uint32_t RFIMDCDCCTRL2; /**< New Register */
__IM uint32_t RFIMDCDCSTATUS; /**< New Register */
__IOM uint32_t RPURATD0; /**< Root Access Type Descriptor Register */
uint32_t RESERVED0[1019U]; /**< Reserved for future use */
__IOM uint32_t RFIMDCDCCTRL0_SET; /**< New Register */
__IOM uint32_t RFIMDCDCCTRL1_SET; /**< New Register */
__IOM uint32_t RFIMDCDCCTRL2_SET; /**< New Register */
__IM uint32_t RFIMDCDCSTATUS_SET; /**< New Register */
__IOM uint32_t RPURATD0_SET; /**< Root Access Type Descriptor Register */
uint32_t RESERVED1[1019U]; /**< Reserved for future use */
__IOM uint32_t RFIMDCDCCTRL0_CLR; /**< New Register */
__IOM uint32_t RFIMDCDCCTRL1_CLR; /**< New Register */
__IOM uint32_t RFIMDCDCCTRL2_CLR; /**< New Register */
__IM uint32_t RFIMDCDCSTATUS_CLR; /**< New Register */
__IOM uint32_t RPURATD0_CLR; /**< Root Access Type Descriptor Register */
uint32_t RESERVED2[1019U]; /**< Reserved for future use */
__IOM uint32_t RFIMDCDCCTRL0_TGL; /**< New Register */
__IOM uint32_t RFIMDCDCCTRL1_TGL; /**< New Register */
__IOM uint32_t RFIMDCDCCTRL2_TGL; /**< New Register */
__IM uint32_t RFIMDCDCSTATUS_TGL; /**< New Register */
__IOM uint32_t RPURATD0_TGL; /**< Root Access Type Descriptor Register */
} PFMXPPRF_TypeDef;
/** @} End of group EFR32ZG23_PFMXPPRF */
/**************************************************************************//**
* @addtogroup EFR32ZG23_PFMXPPRF
* @{
* @defgroup EFR32ZG23_PFMXPPRF_BitFields PFMXPPRF Bit Fields
* @{
*****************************************************************************/
/* Bit fields for PFMXPPRF RFIMDCDCCTRL0 */
#define _PFMXPPRF_RFIMDCDCCTRL0_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL0 */
#define _PFMXPPRF_RFIMDCDCCTRL0_MASK 0x80000003UL /**< Mask for PFMXPPRF_RFIMDCDCCTRL0 */
#define PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ (0x1UL << 0) /**< TX Max Req */
#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_SHIFT 0 /**< Shift value for PFMXPPRF_TXMAXREQ */
#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_MASK 0x1UL /**< Bit mask for PFMXPPRF_TXMAXREQ */
#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0 */
#define PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0*/
#define PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ (0x1UL << 1) /**< RX PP Req */
#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_SHIFT 1 /**< Shift value for PFMXPPRF_RXPPREQ */
#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_MASK 0x2UL /**< Bit mask for PFMXPPRF_RXPPREQ */
#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0 */
#define PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0*/
/* Bit fields for PFMXPPRF RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_RESETVALUE 0x00000014UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_MASK 0x0000003FUL /**< Mask for PFMXPPRF_RFIMDCDCCTRL1 */
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN (0x1UL << 0) /**< DCDC DIV Enable */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_SHIFT 0 /**< Shift value for PFMXPPRF_DCDCDIVEN */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_MASK 0x1UL /**< Bit mask for PFMXPPRF_DCDCDIVEN */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN (0x1UL << 1) /**< DCDC DIV Inverter Enable */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_SHIFT 1 /**< Shift value for PFMXPPRF_DCDCDIVINVEN */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_MASK 0x2UL /**< Bit mask for PFMXPPRF_DCDCDIVINVEN */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_SHIFT 2 /**< Shift value for PFMXPPRF_DCDCDIVRATIO */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_MASK 0x3CUL /**< Bit mask for PFMXPPRF_DCDCDIVRATIO */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT 0x00000005UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 0x00000000UL /**< Mode DIVRATIO8 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 0x00000001UL /**< Mode DIVRATIO9 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 0x00000002UL /**< Mode DIVRATIO10 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 0x00000003UL /**< Mode DIVRATIO11 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 0x00000004UL /**< Mode DIVRATIO12 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 0x00000005UL /**< Mode DIVRATIO13 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 0x00000006UL /**< Mode DIVRATIO14 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 0x00000007UL /**< Mode DIVRATIO15 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 0x00000008UL /**< Mode DIVRATIO16 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 0x00000009UL /**< Mode DIVRATIO17 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 0x0000000AUL /**< Mode DIVRATIO18 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 0x0000000BUL /**< Mode DIVRATIO19 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 0x0000000CUL /**< Mode DIVRATIO20 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 0x0000000DUL /**< Mode DIVRATIO21 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 0x0000000EUL /**< Mode DIVRATIO22 for PFMXPPRF_RFIMDCDCCTRL1 */
#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 0x0000000FUL /**< Mode DIVRATIO23 for PFMXPPRF_RFIMDCDCCTRL1 */
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 << 2) /**< Shifted mode DIVRATIO8 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 << 2) /**< Shifted mode DIVRATIO9 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 << 2) /**< Shifted mode DIVRATIO10 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 << 2) /**< Shifted mode DIVRATIO11 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 << 2) /**< Shifted mode DIVRATIO12 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 << 2) /**< Shifted mode DIVRATIO13 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 << 2) /**< Shifted mode DIVRATIO14 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 << 2) /**< Shifted mode DIVRATIO15 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 << 2) /**< Shifted mode DIVRATIO16 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 << 2) /**< Shifted mode DIVRATIO17 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 << 2) /**< Shifted mode DIVRATIO18 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 << 2) /**< Shifted mode DIVRATIO19 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 << 2) /**< Shifted mode DIVRATIO20 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 << 2) /**< Shifted mode DIVRATIO21 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 << 2) /**< Shifted mode DIVRATIO22 for PFMXPPRF_RFIMDCDCCTRL1*/
#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 << 2) /**< Shifted mode DIVRATIO23 for PFMXPPRF_RFIMDCDCCTRL1*/
/* Bit fields for PFMXPPRF RFIMDCDCCTRL2 */
#define _PFMXPPRF_RFIMDCDCCTRL2_RESETVALUE 0x0AD0B4A0UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL2 */
#define _PFMXPPRF_RFIMDCDCCTRL2_MASK 0x9FFFFFFFUL /**< Mask for PFMXPPRF_RFIMDCDCCTRL2 */
#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_SHIFT 0 /**< Shift value for PFMXPPRF_PPTMAX */
#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_MASK 0x1FFUL /**< Bit mask for PFMXPPRF_PPTMAX */
#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT 0x000000A0UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */
#define PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/
#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_SHIFT 9 /**< Shift value for PFMXPPRF_PPTMIN */
#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_MASK 0x3FE00UL /**< Bit mask for PFMXPPRF_PPTMIN */
#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT 0x0000005AUL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */
#define PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT << 9) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/
#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_SHIFT 18 /**< Shift value for PFMXPPRF_PPND */
#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_MASK 0x7FC0000UL /**< Bit mask for PFMXPPRF_PPND */
#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT 0x000000B4UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */
#define PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT << 18) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/
#define PFMXPPRF_RFIMDCDCCTRL2_PPCALEN (0x1UL << 27) /**< Pulse Pairing Calibration Loop Enable */
#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_SHIFT 27 /**< Shift value for PFMXPPRF_PPCALEN */
#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_MASK 0x8000000UL /**< Bit mask for PFMXPPRF_PPCALEN */
#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */
#define PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT << 27) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/
#define PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY (0x1UL << 28) /**< Pulse Pairing Sync Only */
#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_SHIFT 28 /**< Shift value for PFMXPPRF_PPSYNCONLY */
#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_MASK 0x10000000UL /**< Bit mask for PFMXPPRF_PPSYNCONLY */
#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */
#define PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT << 28) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/
/* Bit fields for PFMXPPRF RFIMDCDCSTATUS */
#define _PFMXPPRF_RFIMDCDCSTATUS_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RFIMDCDCSTATUS */
#define _PFMXPPRF_RFIMDCDCSTATUS_MASK 0x0001FF07UL /**< Mask for PFMXPPRF_RFIMDCDCSTATUS */
#define PFMXPPRF_RFIMDCDCSTATUS_DCDCEN (0x1UL << 0) /**< DCDC Enable Status */
#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_SHIFT 0 /**< Shift value for PFMXPPRF_DCDCEN */
#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_MASK 0x1UL /**< Bit mask for PFMXPPRF_DCDCEN */
#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */
#define PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/
#define PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS (0x1UL << 1) /**< TX MAX Status */
#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_SHIFT 1 /**< Shift value for PFMXPPRF_TXMAXSTATUS */
#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_MASK 0x2UL /**< Bit mask for PFMXPPRF_TXMAXSTATUS */
#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */
#define PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/
#define PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS (0x1UL << 2) /**< RX PP Status */
#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_SHIFT 2 /**< Shift value for PFMXPPRF_RXPPSTATUS */
#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_MASK 0x4UL /**< Bit mask for PFMXPPRF_RXPPSTATUS */
#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */
#define PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/
#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_SHIFT 8 /**< Shift value for PFMXPPRF_WNO1 */
#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_MASK 0x1FF00UL /**< Bit mask for PFMXPPRF_WNO1 */
#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */
#define PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT << 8) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/
/* Bit fields for PFMXPPRF RPURATD0 */
#define _PFMXPPRF_RPURATD0_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RPURATD0 */
#define _PFMXPPRF_RPURATD0_MASK 0x00000007UL /**< Mask for PFMXPPRF_RPURATD0 */
#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0 (0x1UL << 0) /**< RFIMDCDCCTRL0 Protection Bit */
#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_SHIFT 0 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL0 */
#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_MASK 0x1UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL0 */
#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */
#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */
#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1 (0x1UL << 1) /**< RFIMDCDCCTRL1 Protection Bit */
#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_SHIFT 1 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL1 */
#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_MASK 0x2UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL1 */
#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */
#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */
#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2 (0x1UL << 2) /**< RFIMDCDCCTRL2 Protection Bit */
#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_SHIFT 2 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL2 */
#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_MASK 0x4UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL2 */
#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */
#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */
/** @} End of group EFR32ZG23_PFMXPPRF_BitFields */
/** @} End of group EFR32ZG23_PFMXPPRF */
/** @} End of group Parts */
#endif /* EFR32ZG23_PFMXPPRF_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 PRS register signal bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_PRS_SIGNALS_H
#define EFR32ZG23_PRS_SIGNALS_H
/** Synchronous signal sources enumeration: */
#define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL)
#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL)
#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000002UL)
#define _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000003UL)
#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000004UL)
#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000005UL)
#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000006UL)
#define _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 (0x00000007UL)
/** Synchronous signal sources enumeration aligned with register bit field: */
#define PRS_SYNC_CH_CTRL_SOURCESEL_NONE (_PRS_SYNC_CH_CTRL_SOURCESEL_NONE << 8)
#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 << 8)
#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 << 8)
#define PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 << 8)
#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 << 8)
#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 << 8)
#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 << 8)
#define PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 << 8)
/** Synchronous signals enumeration: */
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC (0x00000000UL)
#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC (0x00000001UL)
/** Synchronous signals enumeration aligned with register bit field: */
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC << 0)
#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC << 0)
/** Synchronous signals and sources combined and aligned with register bit fields: */
#define PRS_SYNC_TIMER0_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF)
#define PRS_SYNC_TIMER0_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF)
#define PRS_SYNC_TIMER0_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0)
#define PRS_SYNC_TIMER0_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1)
#define PRS_SYNC_TIMER0_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2)
#define PRS_SYNC_TIMER1_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF)
#define PRS_SYNC_TIMER1_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF)
#define PRS_SYNC_TIMER1_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0)
#define PRS_SYNC_TIMER1_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1)
#define PRS_SYNC_TIMER1_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2)
#define PRS_SYNC_IADC0_SCAN_ENTRY_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE)
#define PRS_SYNC_IADC0_SCAN_TABLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE)
#define PRS_SYNC_IADC0_SINGLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE)
#define PRS_SYNC_TIMER2_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF)
#define PRS_SYNC_TIMER2_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF)
#define PRS_SYNC_TIMER2_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0)
#define PRS_SYNC_TIMER2_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1)
#define PRS_SYNC_TIMER2_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2)
#define PRS_SYNC_TIMER3_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF)
#define PRS_SYNC_TIMER3_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF)
#define PRS_SYNC_TIMER3_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0)
#define PRS_SYNC_TIMER3_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1)
#define PRS_SYNC_TIMER3_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2)
#define PRS_SYNC_TIMER4_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF)
#define PRS_SYNC_TIMER4_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF)
#define PRS_SYNC_TIMER4_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0)
#define PRS_SYNC_TIMER4_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1)
#define PRS_SYNC_TIMER4_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2)
#define PRS_SYNC_VDAC0_CH0_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC)
#define PRS_SYNC_VDAC0_CH1_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC)
/** Asynchronous signal sources enumeration: */
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (0x00000006UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (0x00000007UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (0x00000008UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (0x00000009UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (0x0000000aUL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 (0x0000000bUL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L (0x0000000cUL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 (0x0000000dUL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 (0x0000000eUL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 (0x0000000fUL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LESENSE (0x00000010UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L (0x00000011UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (0x00000012UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (0x00000013UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (0x00000014UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (0x00000015UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (0x00000016UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 (0x00000017UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LCD (0x00000018UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (0x00000020UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000021UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000022UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000023UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000024UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (0x00000025UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (0x00000026UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (0x00000027UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (0x00000028UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (0x00000029UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (0x0000002aUL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (0x0000002bUL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (0x0000002cUL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (0x0000002dUL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (0x0000002eUL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (0x0000002fUL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (0x00000030UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (0x00000031UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000032UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (0x00000033UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (0x00000034UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L (0x00000035UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 (0x00000036UL)
#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (0x00000037UL)
/** Asynchronous signal sources enumeration aligned with register bit field: */
#define PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (_PRS_ASYNC_CH_CTRL_SOURCESEL_NONE << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (_PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (_PRS_ASYNC_CH_CTRL_SOURCESEL_CORE << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMU << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGC << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (_PRS_ASYNC_CH_CTRL_SOURCESEL_FRC << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRS << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (_PRS_ASYNC_CH_CTRL_SOURCESEL_RACL << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RAC << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_LESENSE (_PRS_ASYNC_CH_CTRL_SOURCESEL_LESENSE << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMU << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 << 8)
#define PRS_ASYNC_CH_CTRL_SOURCESEL_LCD (_PRS_ASYNC_CH_CTRL_SOURCESEL_LCD << 8)
/** Asynchronous signals enumeration: */
#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (0x00000006UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (0x00000007UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (0x00000006UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (0x00000007UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (0x00000006UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (0x00000006UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (0x00000007UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (0x00000006UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (0x00000007UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (0x00000006UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (0x00000007UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (0x00000006UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (0x00000006UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (0x00000007UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (0x00000006UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (0x00000007UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT0 (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT1 (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT2 (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECCMP (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (0x00000006UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (0x00000007UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (0x00000006UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (0x00000007UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LCS (0x00000000UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LIRDATX (0x00000001UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRTS (0x00000002UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXDATAV (0x00000003UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTX (0x00000004UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXC (0x00000005UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXFL (0x00000006UL)
#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXFL (0x00000007UL)
/** Asynchronous signals enumeration aligned with register bit field: */
#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT0 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT2 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECCMP << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS (_PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 (_PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LCS << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LIRDATX << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRTS << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXDATAV << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTX << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXC << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXFL << 0)
#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXFL << 0)
/** Asynchronous signals and sources combined and aligned with register bit fields: */
#define PRS_ASYNC_USART0_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS)
#define PRS_ASYNC_USART0_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX)
#define PRS_ASYNC_USART0_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS)
#define PRS_ASYNC_USART0_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA)
#define PRS_ASYNC_USART0_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX)
#define PRS_ASYNC_USART0_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC)
#define PRS_ASYNC_TIMER0_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF)
#define PRS_ASYNC_TIMER0_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF)
#define PRS_ASYNC_TIMER0_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0)
#define PRS_ASYNC_TIMER0_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1)
#define PRS_ASYNC_TIMER0_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2)
#define PRS_ASYNC_TIMER1_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF)
#define PRS_ASYNC_TIMER1_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF)
#define PRS_ASYNC_TIMER1_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0)
#define PRS_ASYNC_TIMER1_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1)
#define PRS_ASYNC_TIMER1_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2)
#define PRS_ASYNC_IADC0_SCANENTRYDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE)
#define PRS_ASYNC_IADC0_SCANTABLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE)
#define PRS_ASYNC_IADC0_SINGLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE)
#define PRS_ASYNC_LETIMER0_CH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0)
#define PRS_ASYNC_LETIMER0_CH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1)
#define PRS_ASYNC_BURTC_COMP (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP)
#define PRS_ASYNC_BURTC_OVERFLOW (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW)
#define PRS_ASYNC_GPIO_PIN0 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0)
#define PRS_ASYNC_GPIO_PIN1 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1)
#define PRS_ASYNC_GPIO_PIN2 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2)
#define PRS_ASYNC_GPIO_PIN3 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3)
#define PRS_ASYNC_GPIO_PIN4 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4)
#define PRS_ASYNC_GPIO_PIN5 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5)
#define PRS_ASYNC_GPIO_PIN6 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6)
#define PRS_ASYNC_GPIO_PIN7 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7)
#define PRS_ASYNC_TIMER2_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF)
#define PRS_ASYNC_TIMER2_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF)
#define PRS_ASYNC_TIMER2_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0)
#define PRS_ASYNC_TIMER2_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1)
#define PRS_ASYNC_TIMER2_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2)
#define PRS_ASYNC_TIMER3_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF)
#define PRS_ASYNC_TIMER3_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF)
#define PRS_ASYNC_TIMER3_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0)
#define PRS_ASYNC_TIMER3_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1)
#define PRS_ASYNC_TIMER3_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2)
#define PRS_ASYNC_CORE_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0)
#define PRS_ASYNC_CORE_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1)
#define PRS_ASYNC_CORE_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2)
#define PRS_ASYNC_CORE_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3)
#define PRS_ASYNC_CMUL_CLKOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0)
#define PRS_ASYNC_CMUL_CLKOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1)
#define PRS_ASYNC_CMUL_CLKOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2)
#define PRS_ASYNC_AGCL_CCA (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA)
#define PRS_ASYNC_AGCL_CCAREQ (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ)
#define PRS_ASYNC_AGCL_GAINADJUST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST)
#define PRS_ASYNC_AGCL_GAINOK (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK)
#define PRS_ASYNC_AGCL_GAINREDUCED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED)
#define PRS_ASYNC_AGCL_IFPKI1 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1)
#define PRS_ASYNC_AGCL_IFPKQ2 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2)
#define PRS_ASYNC_AGCL_IFPKRST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST)
#define PRS_ASYNC_AGC_PEAKDET (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET)
#define PRS_ASYNC_AGC_PROPAGATED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED)
#define PRS_ASYNC_AGC_RSSIDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE)
#define PRS_ASYNC_BUFC_THR0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0)
#define PRS_ASYNC_BUFC_THR1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1)
#define PRS_ASYNC_BUFC_THR2 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2)
#define PRS_ASYNC_BUFC_THR3 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3)
#define PRS_ASYNC_BUFC_CNT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0)
#define PRS_ASYNC_BUFC_CNT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1)
#define PRS_ASYNC_BUFC_FULL (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL)
#define PRS_ASYNC_MODEML_ADVANCE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE)
#define PRS_ASYNC_MODEML_ANT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0)
#define PRS_ASYNC_MODEML_ANT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1)
#define PRS_ASYNC_MODEML_COHDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET)
#define PRS_ASYNC_MODEML_COHDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE)
#define PRS_ASYNC_MODEML_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK)
#define PRS_ASYNC_MODEML_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT)
#define PRS_ASYNC_MODEML_FRAMEDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET)
#define PRS_ASYNC_MODEM_FRAMESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT)
#define PRS_ASYNC_MODEM_LOWCORR (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR)
#define PRS_ASYNC_MODEM_LRDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET)
#define PRS_ASYNC_MODEM_LRDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE)
#define PRS_ASYNC_MODEM_NEWSYMBOL (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL)
#define PRS_ASYNC_MODEM_NEWWND (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND)
#define PRS_ASYNC_MODEM_POSTPONE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE)
#define PRS_ASYNC_MODEM_PREDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET)
#define PRS_ASYNC_MODEMH_PRESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT)
#define PRS_ASYNC_MODEMH_RSSIJUMP (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP)
#define PRS_ASYNC_MODEMH_SYNCSENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT)
#define PRS_ASYNC_MODEMH_TIMDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET)
#define PRS_ASYNC_MODEMH_WEAK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK)
#define PRS_ASYNC_MODEMH_EOF (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF)
#define PRS_ASYNC_FRC_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK)
#define PRS_ASYNC_FRC_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT)
#define PRS_ASYNC_PROTIMERL_BOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF)
#define PRS_ASYNC_PROTIMERL_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0)
#define PRS_ASYNC_PROTIMERL_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1)
#define PRS_ASYNC_PROTIMERL_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2)
#define PRS_ASYNC_PROTIMERL_CC3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3)
#define PRS_ASYNC_PROTIMERL_CC4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4)
#define PRS_ASYNC_PROTIMERL_LBTF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF)
#define PRS_ASYNC_PROTIMERL_LBTR (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR)
#define PRS_ASYNC_PROTIMER_LBTS (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS)
#define PRS_ASYNC_PROTIMER_POF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF)
#define PRS_ASYNC_PROTIMER_T0MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH)
#define PRS_ASYNC_PROTIMER_T0UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF)
#define PRS_ASYNC_PROTIMER_T1MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH)
#define PRS_ASYNC_PROTIMER_T1UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF)
#define PRS_ASYNC_PROTIMER_WOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF)
#define PRS_ASYNC_SYNTH_MUX0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0)
#define PRS_ASYNC_SYNTH_MUX1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1)
#define PRS_ASYNC_PRSL_ASYNCH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0)
#define PRS_ASYNC_PRSL_ASYNCH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1)
#define PRS_ASYNC_PRSL_ASYNCH2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2)
#define PRS_ASYNC_PRSL_ASYNCH3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3)
#define PRS_ASYNC_PRSL_ASYNCH4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4)
#define PRS_ASYNC_PRSL_ASYNCH5 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5)
#define PRS_ASYNC_PRSL_ASYNCH6 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6)
#define PRS_ASYNC_PRSL_ASYNCH7 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7)
#define PRS_ASYNC_PRS_ASYNCH8 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8)
#define PRS_ASYNC_PRS_ASYNCH9 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9)
#define PRS_ASYNC_PRS_ASYNCH10 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10)
#define PRS_ASYNC_PRS_ASYNCH11 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11)
#define PRS_ASYNC_RACL_ACTIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE)
#define PRS_ASYNC_RACL_LNAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN)
#define PRS_ASYNC_RACL_PAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN)
#define PRS_ASYNC_RACL_RX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX)
#define PRS_ASYNC_RACL_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX)
#define PRS_ASYNC_RACL_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0)
#define PRS_ASYNC_RACL_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1)
#define PRS_ASYNC_RACL_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2)
#define PRS_ASYNC_RAC_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3)
#define PRS_ASYNC_RAC_AUXADCDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA)
#define PRS_ASYNC_RAC_AUXADCDATAVALID (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID)
#define PRS_ASYNC_TIMER4_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF)
#define PRS_ASYNC_TIMER4_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF)
#define PRS_ASYNC_TIMER4_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0)
#define PRS_ASYNC_TIMER4_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1)
#define PRS_ASYNC_TIMER4_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2)
#define PRS_ASYNC_ACMP0_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT)
#define PRS_ASYNC_ACMP1_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT)
#define PRS_ASYNC_VDAC0L_CH0WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM)
#define PRS_ASYNC_VDAC0L_CH1WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM)
#define PRS_ASYNC_VDAC0L_CH0DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC)
#define PRS_ASYNC_VDAC0L_CH1DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC)
#define PRS_ASYNC_VDAC0L_INTERNALTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF)
#define PRS_ASYNC_VDAC0L_REFRESHTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF)
#define PRS_ASYNC_PCNT0_DIR (PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 | PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR)
#define PRS_ASYNC_PCNT0_UFOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 | PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF)
#define PRS_ASYNC_SYSRTC0_GRP0OUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0)
#define PRS_ASYNC_SYSRTC0_GRP0OUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1)
#define PRS_ASYNC_SYSRTC0_GRP1OUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0)
#define PRS_ASYNC_SYSRTC0_GRP1OUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1)
#define PRS_ASYNC_LESENSE_DECOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_LESENSE | PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT0)
#define PRS_ASYNC_LESENSE_DECOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_LESENSE | PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT1)
#define PRS_ASYNC_LESENSE_DECOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_LESENSE | PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT2)
#define PRS_ASYNC_LESENSE_DECCMP (PRS_ASYNC_CH_CTRL_SOURCESEL_LESENSE | PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECCMP)
#define PRS_ASYNC_HFXO0L_STATUS (PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L | PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS)
#define PRS_ASYNC_HFXO0L_STATUS1 (PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L | PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1)
#define PRS_ASYNC_EUSART0L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS)
#define PRS_ASYNC_EUSART0L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX)
#define PRS_ASYNC_EUSART0L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS)
#define PRS_ASYNC_EUSART0L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV)
#define PRS_ASYNC_EUSART0L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX)
#define PRS_ASYNC_EUSART0L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC)
#define PRS_ASYNC_EUSART0L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL)
#define PRS_ASYNC_EUSART0L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL)
#define PRS_ASYNC_EUSART1L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS)
#define PRS_ASYNC_EUSART1L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX)
#define PRS_ASYNC_EUSART1L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS)
#define PRS_ASYNC_EUSART1L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV)
#define PRS_ASYNC_EUSART1L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX)
#define PRS_ASYNC_EUSART1L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC)
#define PRS_ASYNC_EUSART1L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL)
#define PRS_ASYNC_EUSART1L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL)
#define PRS_ASYNC_EUSART2L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LCS)
#define PRS_ASYNC_EUSART2L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LIRDATX)
#define PRS_ASYNC_EUSART2L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRTS)
#define PRS_ASYNC_EUSART2L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXDATAV)
#define PRS_ASYNC_EUSART2L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTX)
#define PRS_ASYNC_EUSART2L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXC)
#define PRS_ASYNC_EUSART2L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXFL)
#define PRS_ASYNC_EUSART2L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXFL)
/**
* Asynchronous signals and sources combined and aligned with register bit fields
* without the '_ASYNCH_' infix in order for backward compatibility:
*/
#define PRS_USART0_CS (PRS_ASYNC_USART0_CS)
#define PRS_USART0_IRTX (PRS_ASYNC_USART0_IRTX)
#define PRS_USART0_RTS (PRS_ASYNC_USART0_RTS)
#define PRS_USART0_RXDATA (PRS_ASYNC_USART0_RXDATA)
#define PRS_USART0_TX (PRS_ASYNC_USART0_TX)
#define PRS_USART0_TXC (PRS_ASYNC_USART0_TXC)
#define PRS_TIMER0_UF (PRS_ASYNC_TIMER0_UF)
#define PRS_TIMER0_OF (PRS_ASYNC_TIMER0_OF)
#define PRS_TIMER0_CC0 (PRS_ASYNC_TIMER0_CC0)
#define PRS_TIMER0_CC1 (PRS_ASYNC_TIMER0_CC1)
#define PRS_TIMER0_CC2 (PRS_ASYNC_TIMER0_CC2)
#define PRS_TIMER1_UF (PRS_ASYNC_TIMER1_UF)
#define PRS_TIMER1_OF (PRS_ASYNC_TIMER1_OF)
#define PRS_TIMER1_CC0 (PRS_ASYNC_TIMER1_CC0)
#define PRS_TIMER1_CC1 (PRS_ASYNC_TIMER1_CC1)
#define PRS_TIMER1_CC2 (PRS_ASYNC_TIMER1_CC2)
#define PRS_IADC0_SCANENTRYDONE (PRS_ASYNC_IADC0_SCANENTRYDONE)
#define PRS_IADC0_SCANTABLEDONE (PRS_ASYNC_IADC0_SCANTABLEDONE)
#define PRS_IADC0_SINGLEDONE (PRS_ASYNC_IADC0_SINGLEDONE)
#define PRS_LETIMER0_CH0 (PRS_ASYNC_LETIMER0_CH0)
#define PRS_LETIMER0_CH1 (PRS_ASYNC_LETIMER0_CH1)
#define PRS_BURTC_COMP (PRS_ASYNC_BURTC_COMP)
#define PRS_BURTC_OVERFLOW (PRS_ASYNC_BURTC_OVERFLOW)
#define PRS_GPIO_PIN0 (PRS_ASYNC_GPIO_PIN0)
#define PRS_GPIO_PIN1 (PRS_ASYNC_GPIO_PIN1)
#define PRS_GPIO_PIN2 (PRS_ASYNC_GPIO_PIN2)
#define PRS_GPIO_PIN3 (PRS_ASYNC_GPIO_PIN3)
#define PRS_GPIO_PIN4 (PRS_ASYNC_GPIO_PIN4)
#define PRS_GPIO_PIN5 (PRS_ASYNC_GPIO_PIN5)
#define PRS_GPIO_PIN6 (PRS_ASYNC_GPIO_PIN6)
#define PRS_GPIO_PIN7 (PRS_ASYNC_GPIO_PIN7)
#define PRS_TIMER2_UF (PRS_ASYNC_TIMER2_UF)
#define PRS_TIMER2_OF (PRS_ASYNC_TIMER2_OF)
#define PRS_TIMER2_CC0 (PRS_ASYNC_TIMER2_CC0)
#define PRS_TIMER2_CC1 (PRS_ASYNC_TIMER2_CC1)
#define PRS_TIMER2_CC2 (PRS_ASYNC_TIMER2_CC2)
#define PRS_TIMER3_UF (PRS_ASYNC_TIMER3_UF)
#define PRS_TIMER3_OF (PRS_ASYNC_TIMER3_OF)
#define PRS_TIMER3_CC0 (PRS_ASYNC_TIMER3_CC0)
#define PRS_TIMER3_CC1 (PRS_ASYNC_TIMER3_CC1)
#define PRS_TIMER3_CC2 (PRS_ASYNC_TIMER3_CC2)
#define PRS_CORE_CTIOUT0 (PRS_ASYNC_CORE_CTIOUT0)
#define PRS_CORE_CTIOUT1 (PRS_ASYNC_CORE_CTIOUT1)
#define PRS_CORE_CTIOUT2 (PRS_ASYNC_CORE_CTIOUT2)
#define PRS_CORE_CTIOUT3 (PRS_ASYNC_CORE_CTIOUT3)
#define PRS_CMUL_CLKOUT0 (PRS_ASYNC_CMUL_CLKOUT0)
#define PRS_CMUL_CLKOUT1 (PRS_ASYNC_CMUL_CLKOUT1)
#define PRS_CMUL_CLKOUT2 (PRS_ASYNC_CMUL_CLKOUT2)
#define PRS_AGCL_CCA (PRS_ASYNC_AGCL_CCA)
#define PRS_AGCL_CCAREQ (PRS_ASYNC_AGCL_CCAREQ)
#define PRS_AGCL_GAINADJUST (PRS_ASYNC_AGCL_GAINADJUST)
#define PRS_AGCL_GAINOK (PRS_ASYNC_AGCL_GAINOK)
#define PRS_AGCL_GAINREDUCED (PRS_ASYNC_AGCL_GAINREDUCED)
#define PRS_AGCL_IFPKI1 (PRS_ASYNC_AGCL_IFPKI1)
#define PRS_AGCL_IFPKQ2 (PRS_ASYNC_AGCL_IFPKQ2)
#define PRS_AGCL_IFPKRST (PRS_ASYNC_AGCL_IFPKRST)
#define PRS_AGC_PEAKDET (PRS_ASYNC_AGC_PEAKDET)
#define PRS_AGC_PROPAGATED (PRS_ASYNC_AGC_PROPAGATED)
#define PRS_AGC_RSSIDONE (PRS_ASYNC_AGC_RSSIDONE)
#define PRS_BUFC_THR0 (PRS_ASYNC_BUFC_THR0)
#define PRS_BUFC_THR1 (PRS_ASYNC_BUFC_THR1)
#define PRS_BUFC_THR2 (PRS_ASYNC_BUFC_THR2)
#define PRS_BUFC_THR3 (PRS_ASYNC_BUFC_THR3)
#define PRS_BUFC_CNT0 (PRS_ASYNC_BUFC_CNT0)
#define PRS_BUFC_CNT1 (PRS_ASYNC_BUFC_CNT1)
#define PRS_BUFC_FULL (PRS_ASYNC_BUFC_FULL)
#define PRS_MODEML_ADVANCE (PRS_ASYNC_MODEML_ADVANCE)
#define PRS_MODEML_ANT0 (PRS_ASYNC_MODEML_ANT0)
#define PRS_MODEML_ANT1 (PRS_ASYNC_MODEML_ANT1)
#define PRS_MODEML_COHDSADET (PRS_ASYNC_MODEML_COHDSADET)
#define PRS_MODEML_COHDSALIVE (PRS_ASYNC_MODEML_COHDSALIVE)
#define PRS_MODEML_DCLK (PRS_ASYNC_MODEML_DCLK)
#define PRS_MODEML_DOUT (PRS_ASYNC_MODEML_DOUT)
#define PRS_MODEML_FRAMEDET (PRS_ASYNC_MODEML_FRAMEDET)
#define PRS_MODEM_FRAMESENT (PRS_ASYNC_MODEM_FRAMESENT)
#define PRS_MODEM_LOWCORR (PRS_ASYNC_MODEM_LOWCORR)
#define PRS_MODEM_LRDSADET (PRS_ASYNC_MODEM_LRDSADET)
#define PRS_MODEM_LRDSALIVE (PRS_ASYNC_MODEM_LRDSALIVE)
#define PRS_MODEM_NEWSYMBOL (PRS_ASYNC_MODEM_NEWSYMBOL)
#define PRS_MODEM_NEWWND (PRS_ASYNC_MODEM_NEWWND)
#define PRS_MODEM_POSTPONE (PRS_ASYNC_MODEM_POSTPONE)
#define PRS_MODEM_PREDET (PRS_ASYNC_MODEM_PREDET)
#define PRS_MODEMH_PRESENT (PRS_ASYNC_MODEMH_PRESENT)
#define PRS_MODEMH_RSSIJUMP (PRS_ASYNC_MODEMH_RSSIJUMP)
#define PRS_MODEMH_SYNCSENT (PRS_ASYNC_MODEMH_SYNCSENT)
#define PRS_MODEMH_TIMDET (PRS_ASYNC_MODEMH_TIMDET)
#define PRS_MODEMH_WEAK (PRS_ASYNC_MODEMH_WEAK)
#define PRS_MODEMH_EOF (PRS_ASYNC_MODEMH_EOF)
#define PRS_FRC_DCLK (PRS_ASYNC_FRC_DCLK)
#define PRS_FRC_DOUT (PRS_ASYNC_FRC_DOUT)
#define PRS_PROTIMERL_BOF (PRS_ASYNC_PROTIMERL_BOF)
#define PRS_PROTIMERL_CC0 (PRS_ASYNC_PROTIMERL_CC0)
#define PRS_PROTIMERL_CC1 (PRS_ASYNC_PROTIMERL_CC1)
#define PRS_PROTIMERL_CC2 (PRS_ASYNC_PROTIMERL_CC2)
#define PRS_PROTIMERL_CC3 (PRS_ASYNC_PROTIMERL_CC3)
#define PRS_PROTIMERL_CC4 (PRS_ASYNC_PROTIMERL_CC4)
#define PRS_PROTIMERL_LBTF (PRS_ASYNC_PROTIMERL_LBTF)
#define PRS_PROTIMERL_LBTR (PRS_ASYNC_PROTIMERL_LBTR)
#define PRS_PROTIMER_LBTS (PRS_ASYNC_PROTIMER_LBTS)
#define PRS_PROTIMER_POF (PRS_ASYNC_PROTIMER_POF)
#define PRS_PROTIMER_T0MATCH (PRS_ASYNC_PROTIMER_T0MATCH)
#define PRS_PROTIMER_T0UF (PRS_ASYNC_PROTIMER_T0UF)
#define PRS_PROTIMER_T1MATCH (PRS_ASYNC_PROTIMER_T1MATCH)
#define PRS_PROTIMER_T1UF (PRS_ASYNC_PROTIMER_T1UF)
#define PRS_PROTIMER_WOF (PRS_ASYNC_PROTIMER_WOF)
#define PRS_SYNTH_MUX0 (PRS_ASYNC_SYNTH_MUX0)
#define PRS_SYNTH_MUX1 (PRS_ASYNC_SYNTH_MUX1)
#define PRS_PRSL_ASYNCH0 (PRS_ASYNC_PRSL_ASYNCH0)
#define PRS_PRSL_ASYNCH1 (PRS_ASYNC_PRSL_ASYNCH1)
#define PRS_PRSL_ASYNCH2 (PRS_ASYNC_PRSL_ASYNCH2)
#define PRS_PRSL_ASYNCH3 (PRS_ASYNC_PRSL_ASYNCH3)
#define PRS_PRSL_ASYNCH4 (PRS_ASYNC_PRSL_ASYNCH4)
#define PRS_PRSL_ASYNCH5 (PRS_ASYNC_PRSL_ASYNCH5)
#define PRS_PRSL_ASYNCH6 (PRS_ASYNC_PRSL_ASYNCH6)
#define PRS_PRSL_ASYNCH7 (PRS_ASYNC_PRSL_ASYNCH7)
#define PRS_PRS_ASYNCH8 (PRS_ASYNC_PRS_ASYNCH8)
#define PRS_PRS_ASYNCH9 (PRS_ASYNC_PRS_ASYNCH9)
#define PRS_PRS_ASYNCH10 (PRS_ASYNC_PRS_ASYNCH10)
#define PRS_PRS_ASYNCH11 (PRS_ASYNC_PRS_ASYNCH11)
#define PRS_RACL_ACTIVE (PRS_ASYNC_RACL_ACTIVE)
#define PRS_RACL_LNAEN (PRS_ASYNC_RACL_LNAEN)
#define PRS_RACL_PAEN (PRS_ASYNC_RACL_PAEN)
#define PRS_RACL_RX (PRS_ASYNC_RACL_RX)
#define PRS_RACL_TX (PRS_ASYNC_RACL_TX)
#define PRS_RACL_CTIOUT0 (PRS_ASYNC_RACL_CTIOUT0)
#define PRS_RACL_CTIOUT1 (PRS_ASYNC_RACL_CTIOUT1)
#define PRS_RACL_CTIOUT2 (PRS_ASYNC_RACL_CTIOUT2)
#define PRS_RAC_CTIOUT3 (PRS_ASYNC_RAC_CTIOUT3)
#define PRS_RAC_AUXADCDATA (PRS_ASYNC_RAC_AUXADCDATA)
#define PRS_RAC_AUXADCDATAVALID (PRS_ASYNC_RAC_AUXADCDATAVALID)
#define PRS_TIMER4_UF (PRS_ASYNC_TIMER4_UF)
#define PRS_TIMER4_OF (PRS_ASYNC_TIMER4_OF)
#define PRS_TIMER4_CC0 (PRS_ASYNC_TIMER4_CC0)
#define PRS_TIMER4_CC1 (PRS_ASYNC_TIMER4_CC1)
#define PRS_TIMER4_CC2 (PRS_ASYNC_TIMER4_CC2)
#define PRS_ACMP0_OUT (PRS_ASYNC_ACMP0_OUT)
#define PRS_ACMP1_OUT (PRS_ASYNC_ACMP1_OUT)
#define PRS_VDAC0L_CH0WARM (PRS_ASYNC_VDAC0L_CH0WARM)
#define PRS_VDAC0L_CH1WARM (PRS_ASYNC_VDAC0L_CH1WARM)
#define PRS_VDAC0L_CH0DONEASYNC (PRS_ASYNC_VDAC0L_CH0DONEASYNC)
#define PRS_VDAC0L_CH1DONEASYNC (PRS_ASYNC_VDAC0L_CH1DONEASYNC)
#define PRS_VDAC0L_INTERNALTIMEROF (PRS_ASYNC_VDAC0L_INTERNALTIMEROF)
#define PRS_VDAC0L_REFRESHTIMEROF (PRS_ASYNC_VDAC0L_REFRESHTIMEROF)
#define PRS_PCNT0_DIR (PRS_ASYNC_PCNT0_DIR)
#define PRS_PCNT0_UFOF (PRS_ASYNC_PCNT0_UFOF)
#define PRS_SYSRTC0_GRP0OUT0 (PRS_ASYNC_SYSRTC0_GRP0OUT0)
#define PRS_SYSRTC0_GRP0OUT1 (PRS_ASYNC_SYSRTC0_GRP0OUT1)
#define PRS_SYSRTC0_GRP1OUT0 (PRS_ASYNC_SYSRTC0_GRP1OUT0)
#define PRS_SYSRTC0_GRP1OUT1 (PRS_ASYNC_SYSRTC0_GRP1OUT1)
#define PRS_LESENSE_DECOUT0 (PRS_ASYNC_LESENSE_DECOUT0)
#define PRS_LESENSE_DECOUT1 (PRS_ASYNC_LESENSE_DECOUT1)
#define PRS_LESENSE_DECOUT2 (PRS_ASYNC_LESENSE_DECOUT2)
#define PRS_LESENSE_DECCMP (PRS_ASYNC_LESENSE_DECCMP)
#define PRS_HFXO0L_STATUS (PRS_ASYNC_HFXO0L_STATUS)
#define PRS_HFXO0L_STATUS1 (PRS_ASYNC_HFXO0L_STATUS1)
#define PRS_EUSART0L_CS (PRS_ASYNC_EUSART0L_CS)
#define PRS_EUSART0L_IRDATX (PRS_ASYNC_EUSART0L_IRDATX)
#define PRS_EUSART0L_RTS (PRS_ASYNC_EUSART0L_RTS)
#define PRS_EUSART0L_RXDATAV (PRS_ASYNC_EUSART0L_RXDATAV)
#define PRS_EUSART0L_TX (PRS_ASYNC_EUSART0L_TX)
#define PRS_EUSART0L_TXC (PRS_ASYNC_EUSART0L_TXC)
#define PRS_EUSART0L_RXFL (PRS_ASYNC_EUSART0L_RXFL)
#define PRS_EUSART0L_TXFL (PRS_ASYNC_EUSART0L_TXFL)
#define PRS_EUSART1L_CS (PRS_ASYNC_EUSART1L_CS)
#define PRS_EUSART1L_IRDATX (PRS_ASYNC_EUSART1L_IRDATX)
#define PRS_EUSART1L_RTS (PRS_ASYNC_EUSART1L_RTS)
#define PRS_EUSART1L_RXDATAV (PRS_ASYNC_EUSART1L_RXDATAV)
#define PRS_EUSART1L_TX (PRS_ASYNC_EUSART1L_TX)
#define PRS_EUSART1L_TXC (PRS_ASYNC_EUSART1L_TXC)
#define PRS_EUSART1L_RXFL (PRS_ASYNC_EUSART1L_RXFL)
#define PRS_EUSART1L_TXFL (PRS_ASYNC_EUSART1L_TXFL)
#define PRS_EUSART2L_CS (PRS_ASYNC_EUSART2L_CS)
#define PRS_EUSART2L_IRDATX (PRS_ASYNC_EUSART2L_IRDATX)
#define PRS_EUSART2L_RTS (PRS_ASYNC_EUSART2L_RTS)
#define PRS_EUSART2L_RXDATAV (PRS_ASYNC_EUSART2L_RXDATAV)
#define PRS_EUSART2L_TX (PRS_ASYNC_EUSART2L_TX)
#define PRS_EUSART2L_TXC (PRS_ASYNC_EUSART2L_TXC)
#define PRS_EUSART2L_RXFL (PRS_ASYNC_EUSART2L_RXFL)
#define PRS_EUSART2L_TXFL (PRS_ASYNC_EUSART2L_TXFL)
#endif /* EFR32ZG23_PRS_SIGNALS_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 SCRATCHPAD register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_SCRATCHPAD_H
#define EFR32ZG23_SCRATCHPAD_H
#define SCRATCHPAD_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_SCRATCHPAD SCRATCHPAD
* @{
* @brief EFR32ZG23 SCRATCHPAD Register Declaration.
*****************************************************************************/
/** SCRATCHPAD Register Declaration. */
typedef struct {
__IOM uint32_t SREG0; /**< Scratchpad Register 0 */
__IOM uint32_t SREG1; /**< Scratchpad Register 1 */
uint32_t RESERVED0[1022U]; /**< Reserved for future use */
__IOM uint32_t SREG0_SET; /**< Scratchpad Register 0 */
__IOM uint32_t SREG1_SET; /**< Scratchpad Register 1 */
uint32_t RESERVED1[1022U]; /**< Reserved for future use */
__IOM uint32_t SREG0_CLR; /**< Scratchpad Register 0 */
__IOM uint32_t SREG1_CLR; /**< Scratchpad Register 1 */
uint32_t RESERVED2[1022U]; /**< Reserved for future use */
__IOM uint32_t SREG0_TGL; /**< Scratchpad Register 0 */
__IOM uint32_t SREG1_TGL; /**< Scratchpad Register 1 */
} SCRATCHPAD_TypeDef;
/** @} End of group EFR32ZG23_SCRATCHPAD */
/**************************************************************************//**
* @addtogroup EFR32ZG23_SCRATCHPAD
* @{
* @defgroup EFR32ZG23_SCRATCHPAD_BitFields SCRATCHPAD Bit Fields
* @{
*****************************************************************************/
/* Bit fields for SCRATCHPAD SREG0 */
#define _SCRATCHPAD_SREG0_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG0 */
#define _SCRATCHPAD_SREG0_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG0 */
#define _SCRATCHPAD_SREG0_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */
#define _SCRATCHPAD_SREG0_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */
#define _SCRATCHPAD_SREG0_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG0 */
#define SCRATCHPAD_SREG0_SCRATCH_DEFAULT (_SCRATCHPAD_SREG0_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG0 */
/* Bit fields for SCRATCHPAD SREG1 */
#define _SCRATCHPAD_SREG1_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG1 */
#define _SCRATCHPAD_SREG1_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG1 */
#define _SCRATCHPAD_SREG1_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */
#define _SCRATCHPAD_SREG1_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */
#define _SCRATCHPAD_SREG1_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG1 */
#define SCRATCHPAD_SREG1_SCRATCH_DEFAULT (_SCRATCHPAD_SREG1_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG1 */
/** @} End of group EFR32ZG23_SCRATCHPAD_BitFields */
/** @} End of group EFR32ZG23_SCRATCHPAD */
/** @} End of group Parts */
#endif /* EFR32ZG23_SCRATCHPAD_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 SEMAILBOX register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_SEMAILBOX_H
#define EFR32ZG23_SEMAILBOX_H
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_SEMAILBOX_HOST SEMAILBOX_HOST
* @{
* @brief EFR32ZG23 SEMAILBOX_HOST Register Declaration.
*****************************************************************************/
/** SEMAILBOX_HOST Register Declaration. */
typedef struct {
__IOM uint32_t FIFO; /**< ESECURE_MAILBOX_FIFO */
uint32_t RESERVED0[15U]; /**< Reserved for future use */
__IM uint32_t TX_STATUS; /**< ESECURE_MAILBOX_TXSTAT */
__IM uint32_t RX_STATUS; /**< ESECURE_MAILBOX_RXSTAT */
__IM uint32_t TX_PROT; /**< ESECURE_MAILBOX_TXPROTECT */
__IM uint32_t RX_PROT; /**< ESECURE_MAILBOX_RXPROTECT */
__IOM uint32_t TX_HEADER; /**< ESECURE_MAILBOX_TXHEADER */
__IM uint32_t RX_HEADER; /**< ESECURE_MAILBOX_RXHEADER */
__IOM uint32_t CONFIGURATION; /**< ESECURE_MAILBOX_CONFIG */
} SEMAILBOX_HOST_TypeDef;
/** @} End of group EFR32ZG23_SEMAILBOX_HOST */
/**************************************************************************//**
* @addtogroup EFR32ZG23_SEMAILBOX_HOST
* @{
* @defgroup EFR32ZG23_SEMAILBOX_HOST_BitFields SEMAILBOX_HOST Bit Fields
* @{
*****************************************************************************/
/* Bit fields for SEMAILBOX FIFO */
#define _SEMAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_FIFO */
#define _SEMAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_FIFO */
#define _SEMAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */
#define _SEMAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */
#define _SEMAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_FIFO */
#define SEMAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_FIFO */
/* Bit fields for SEMAILBOX TX_STATUS */
#define _SEMAILBOX_TX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_STATUS */
#define _SEMAILBOX_TX_STATUS_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_TX_STATUS */
#define _SEMAILBOX_TX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */
#define _SEMAILBOX_TX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */
#define _SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */
#define SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/
#define _SEMAILBOX_TX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */
#define _SEMAILBOX_TX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */
#define _SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */
#define SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/
#define SEMAILBOX_TX_STATUS_TXINT (0x1UL << 20) /**< TXINT */
#define _SEMAILBOX_TX_STATUS_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */
#define _SEMAILBOX_TX_STATUS_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */
#define _SEMAILBOX_TX_STATUS_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */
#define SEMAILBOX_TX_STATUS_TXINT_DEFAULT (_SEMAILBOX_TX_STATUS_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/
#define SEMAILBOX_TX_STATUS_TXFULL (0x1UL << 21) /**< TXFULL */
#define _SEMAILBOX_TX_STATUS_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */
#define _SEMAILBOX_TX_STATUS_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */
#define _SEMAILBOX_TX_STATUS_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */
#define SEMAILBOX_TX_STATUS_TXFULL_DEFAULT (_SEMAILBOX_TX_STATUS_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/
#define SEMAILBOX_TX_STATUS_TXERROR (0x1UL << 23) /**< TXERROR */
#define _SEMAILBOX_TX_STATUS_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */
#define _SEMAILBOX_TX_STATUS_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */
#define _SEMAILBOX_TX_STATUS_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */
#define SEMAILBOX_TX_STATUS_TXERROR_DEFAULT (_SEMAILBOX_TX_STATUS_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/
/* Bit fields for SEMAILBOX RX_STATUS */
#define _SEMAILBOX_RX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_STATUS */
#define _SEMAILBOX_RX_STATUS_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_RX_STATUS */
#define _SEMAILBOX_RX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */
#define _SEMAILBOX_RX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */
#define _SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */
#define SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/
#define _SEMAILBOX_RX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */
#define _SEMAILBOX_RX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */
#define _SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */
#define SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/
#define SEMAILBOX_RX_STATUS_RXINT (0x1UL << 20) /**< RXINT */
#define _SEMAILBOX_RX_STATUS_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */
#define _SEMAILBOX_RX_STATUS_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */
#define _SEMAILBOX_RX_STATUS_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */
#define SEMAILBOX_RX_STATUS_RXINT_DEFAULT (_SEMAILBOX_RX_STATUS_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/
#define SEMAILBOX_RX_STATUS_RXEMPTY (0x1UL << 21) /**< RXEMPTY */
#define _SEMAILBOX_RX_STATUS_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */
#define _SEMAILBOX_RX_STATUS_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */
#define _SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */
#define SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT (_SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/
#define SEMAILBOX_RX_STATUS_RXHDR (0x1UL << 22) /**< RXHDR */
#define _SEMAILBOX_RX_STATUS_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */
#define _SEMAILBOX_RX_STATUS_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */
#define _SEMAILBOX_RX_STATUS_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */
#define SEMAILBOX_RX_STATUS_RXHDR_DEFAULT (_SEMAILBOX_RX_STATUS_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/
#define SEMAILBOX_RX_STATUS_RXERROR (0x1UL << 23) /**< RXERROR */
#define _SEMAILBOX_RX_STATUS_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */
#define _SEMAILBOX_RX_STATUS_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */
#define _SEMAILBOX_RX_STATUS_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */
#define SEMAILBOX_RX_STATUS_RXERROR_DEFAULT (_SEMAILBOX_RX_STATUS_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/
/* Bit fields for SEMAILBOX TX_PROT */
#define _SEMAILBOX_TX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_PROT */
#define _SEMAILBOX_TX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_TX_PROT */
#define SEMAILBOX_TX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */
#define _SEMAILBOX_TX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */
#define _SEMAILBOX_TX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */
#define _SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */
#define SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */
#define SEMAILBOX_TX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */
#define _SEMAILBOX_TX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */
#define _SEMAILBOX_TX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */
#define _SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */
#define SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */
#define SEMAILBOX_TX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */
#define _SEMAILBOX_TX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */
#define _SEMAILBOX_TX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */
#define _SEMAILBOX_TX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */
#define SEMAILBOX_TX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_TX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */
#define _SEMAILBOX_TX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */
#define _SEMAILBOX_TX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */
#define _SEMAILBOX_TX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */
#define SEMAILBOX_TX_PROT_USER_DEFAULT (_SEMAILBOX_TX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */
/* Bit fields for SEMAILBOX RX_PROT */
#define _SEMAILBOX_RX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_PROT */
#define _SEMAILBOX_RX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_RX_PROT */
#define SEMAILBOX_RX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */
#define _SEMAILBOX_RX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */
#define _SEMAILBOX_RX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */
#define _SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */
#define SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */
#define SEMAILBOX_RX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */
#define _SEMAILBOX_RX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */
#define _SEMAILBOX_RX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */
#define _SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */
#define SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */
#define SEMAILBOX_RX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */
#define _SEMAILBOX_RX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */
#define _SEMAILBOX_RX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */
#define _SEMAILBOX_RX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */
#define SEMAILBOX_RX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_RX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */
#define _SEMAILBOX_RX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */
#define _SEMAILBOX_RX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */
#define _SEMAILBOX_RX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */
#define SEMAILBOX_RX_PROT_USER_DEFAULT (_SEMAILBOX_RX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */
/* Bit fields for SEMAILBOX TX_HEADER */
#define _SEMAILBOX_TX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_HEADER */
#define _SEMAILBOX_TX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_TX_HEADER */
#define _SEMAILBOX_TX_HEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */
#define _SEMAILBOX_TX_HEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */
#define _SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */
#define SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT (_SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/
/* Bit fields for SEMAILBOX RX_HEADER */
#define _SEMAILBOX_RX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_HEADER */
#define _SEMAILBOX_RX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_RX_HEADER */
#define _SEMAILBOX_RX_HEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */
#define _SEMAILBOX_RX_HEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */
#define _SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */
#define SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT (_SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/
/* Bit fields for SEMAILBOX CONFIGURATION */
#define _SEMAILBOX_CONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_CONFIGURATION */
#define _SEMAILBOX_CONFIGURATION_MASK 0x00000003UL /**< Mask for SEMAILBOX_CONFIGURATION */
#define SEMAILBOX_CONFIGURATION_TXINTEN (0x1UL << 0) /**< TXINTEN */
#define _SEMAILBOX_CONFIGURATION_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */
#define _SEMAILBOX_CONFIGURATION_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */
#define _SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */
#define SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/
#define SEMAILBOX_CONFIGURATION_RXINTEN (0x1UL << 1) /**< RXINTEN */
#define _SEMAILBOX_CONFIGURATION_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */
#define _SEMAILBOX_CONFIGURATION_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */
#define _SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */
#define SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/
/** @} End of group EFR32ZG23_SEMAILBOX_HOST_BitFields */
/** @} End of group EFR32ZG23_SEMAILBOX_HOST */
/**************************************************************************//**
* @defgroup EFR32ZG23_SEMAILBOX_APBSE SEMAILBOX_APBSE
* @{
* @brief EFR32ZG23 SEMAILBOX_APBSE Register Declaration.
*****************************************************************************/
/** SEMAILBOX_APBSE Register Declaration. */
typedef struct {
__IOM uint32_t SE_ESECURE_MAILBOX_FIFO; /**< ESECURE_MAILBOX_FIFO */
uint32_t RESERVED0[15U]; /**< Reserved for future use */
__IM uint32_t SE_ESECURE_MAILBOX_TXSTAT; /**< ESECURE_MAILBOX_TXSTAT */
__IM uint32_t SE_ESECURE_MAILBOX_RXSTAT; /**< ESECURE_MAILBOX_RXSTAT */
__IM uint32_t SE_ESECURE_MAILBOX_TXPROTECT; /**< ESECURE_MAILBOX_TXPROTECT */
__IM uint32_t SE_ESECURE_MAILBOX_RXPROTECT; /**< ESECURE_MAILBOX_RXPROTECT */
__IOM uint32_t SE_ESECURE_MAILBOX_TXHEADER; /**< ESECURE_MAILBOX_TXHEADER */
__IM uint32_t SE_ESECURE_MAILBOX_RXHEADER; /**< ESECURE_MAILBOX_RXHEADER */
__IOM uint32_t SE_ESECURE_MAILBOX_CONFIG; /**< ESECURE_MAILBOX_CONFIG */
} SEMAILBOX_APBSE_TypeDef;
/** @} End of group EFR32ZG23_SEMAILBOX_APBSE */
/**************************************************************************//**
* @addtogroup EFR32ZG23_SEMAILBOX_APBSE
* @{
* @defgroup EFR32ZG23_SEMAILBOX_APBSE_BitFields SEMAILBOX_APBSE Bit Fields
* @{
*****************************************************************************/
/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_FIFO */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/
/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXSTAT */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT (0x1UL << 20) /**< TXINT */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL (0x1UL << 21) /**< TXFULL */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR (0x1UL << 23) /**< TXERROR */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXSTAT */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT (0x1UL << 20) /**< RXINT */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY (0x1UL << 21) /**< RXEMPTY */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR (0x1UL << 22) /**< RXHDR */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR (0x1UL << 23) /**< RXERROR */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXPROTECT */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXPROTECT */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXHEADER */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/
/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXHEADER */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/
/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_CONFIG */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/
#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_MASK 0x00000003UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN (0x1UL << 0) /**< TXINTEN */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN (0x1UL << 1) /**< RXINTEN */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */
#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/
#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/
/** @} End of group EFR32ZG23_SEMAILBOX_APBSE_BitFields */
/** @} End of group EFR32ZG23_SEMAILBOX_APBSE */
/** @} End of group Parts */
#endif /* EFR32ZG23_SEMAILBOX_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 SYSCFG register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_SYSCFG_H
#define EFR32ZG23_SYSCFG_H
#define SYSCFG_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_SYSCFG SYSCFG
* @{
* @brief EFR32ZG23 SYSCFG Register Declaration.
*****************************************************************************/
/** SYSCFG Register Declaration. */
typedef struct {
uint32_t RESERVED0[1U]; /**< Reserved for future use */
__IM uint32_t IPVERSION; /**< IP version ID */
__IOM uint32_t IF; /**< Interrupt Flag */
__IOM uint32_t IEN; /**< Interrupt Enable */
uint32_t RESERVED1[1U]; /**< Reserved for future use */
__IOM uint32_t CHIPREVHW; /**< Chip Revision, Hard-wired */
__IOM uint32_t CHIPREV; /**< Part Family and Revision Values */
uint32_t RESERVED2[2U]; /**< Reserved for future use */
__IOM uint32_t CFGSYSTIC; /**< SysTick clock source */
uint32_t RESERVED3[54U]; /**< Reserved for future use */
uint32_t RESERVED4[1U]; /**< Reserved for future use */
uint32_t RESERVED5[63U]; /**< Reserved for future use */
__IOM uint32_t CTRL; /**< Control */
uint32_t RESERVED6[1U]; /**< Reserved for future use */
__IOM uint32_t DMEM0RETNCTRL; /**< DMEM0 Retention Control */
uint32_t RESERVED7[64U]; /**< Reserved for future use */
__IOM uint32_t RAMBIASCONF; /**< RAM Bias Configuration */
uint32_t RESERVED8[60U]; /**< Reserved for future use */
__IOM uint32_t RADIORAMRETNCTRL; /**< RADIO RAM Retention Control Register */
uint32_t RESERVED9[1U]; /**< Reserved for future use */
__IOM uint32_t RADIOECCCTRL; /**< RADIO RAM ECC Control Register */
uint32_t RESERVED10[1U]; /**< Reserved for future use */
__IM uint32_t SEQRAMECCADDR; /**< SEQRAM ECC Address */
__IM uint32_t FRCRAMECCADDR; /**< FRCRAM ECC Address */
__IOM uint32_t ICACHERAMRETNCTRL; /**< HOST ICACHERAM Retention Control */
__IOM uint32_t DMEM0PORTMAPSEL; /**< DMEM0 port remap selection */
uint32_t RESERVED11[120U]; /**< Reserved for future use */
__IOM uint32_t ROOTDATA0; /**< Data Register 0 */
__IOM uint32_t ROOTDATA1; /**< Data Register 1 */
__IM uint32_t ROOTLOCKSTATUS; /**< Lock Status */
__IOM uint32_t ROOTSESWVERSION; /**< SE SW Version */
uint32_t RESERVED12[1U]; /**< Reserved for future use */
uint32_t RESERVED13[635U]; /**< Reserved for future use */
uint32_t RESERVED14[1U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP version ID */
__IOM uint32_t IF_SET; /**< Interrupt Flag */
__IOM uint32_t IEN_SET; /**< Interrupt Enable */
uint32_t RESERVED15[1U]; /**< Reserved for future use */
__IOM uint32_t CHIPREVHW_SET; /**< Chip Revision, Hard-wired */
__IOM uint32_t CHIPREV_SET; /**< Part Family and Revision Values */
uint32_t RESERVED16[2U]; /**< Reserved for future use */
__IOM uint32_t CFGSYSTIC_SET; /**< SysTick clock source */
uint32_t RESERVED17[54U]; /**< Reserved for future use */
uint32_t RESERVED18[1U]; /**< Reserved for future use */
uint32_t RESERVED19[63U]; /**< Reserved for future use */
__IOM uint32_t CTRL_SET; /**< Control */
uint32_t RESERVED20[1U]; /**< Reserved for future use */
__IOM uint32_t DMEM0RETNCTRL_SET; /**< DMEM0 Retention Control */
uint32_t RESERVED21[64U]; /**< Reserved for future use */
__IOM uint32_t RAMBIASCONF_SET; /**< RAM Bias Configuration */
uint32_t RESERVED22[60U]; /**< Reserved for future use */
__IOM uint32_t RADIORAMRETNCTRL_SET; /**< RADIO RAM Retention Control Register */
uint32_t RESERVED23[1U]; /**< Reserved for future use */
__IOM uint32_t RADIOECCCTRL_SET; /**< RADIO RAM ECC Control Register */
uint32_t RESERVED24[1U]; /**< Reserved for future use */
__IM uint32_t SEQRAMECCADDR_SET; /**< SEQRAM ECC Address */
__IM uint32_t FRCRAMECCADDR_SET; /**< FRCRAM ECC Address */
__IOM uint32_t ICACHERAMRETNCTRL_SET; /**< HOST ICACHERAM Retention Control */
__IOM uint32_t DMEM0PORTMAPSEL_SET; /**< DMEM0 port remap selection */
uint32_t RESERVED25[120U]; /**< Reserved for future use */
__IOM uint32_t ROOTDATA0_SET; /**< Data Register 0 */
__IOM uint32_t ROOTDATA1_SET; /**< Data Register 1 */
__IM uint32_t ROOTLOCKSTATUS_SET; /**< Lock Status */
__IOM uint32_t ROOTSESWVERSION_SET; /**< SE SW Version */
uint32_t RESERVED26[1U]; /**< Reserved for future use */
uint32_t RESERVED27[635U]; /**< Reserved for future use */
uint32_t RESERVED28[1U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP version ID */
__IOM uint32_t IF_CLR; /**< Interrupt Flag */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable */
uint32_t RESERVED29[1U]; /**< Reserved for future use */
__IOM uint32_t CHIPREVHW_CLR; /**< Chip Revision, Hard-wired */
__IOM uint32_t CHIPREV_CLR; /**< Part Family and Revision Values */
uint32_t RESERVED30[2U]; /**< Reserved for future use */
__IOM uint32_t CFGSYSTIC_CLR; /**< SysTick clock source */
uint32_t RESERVED31[54U]; /**< Reserved for future use */
uint32_t RESERVED32[1U]; /**< Reserved for future use */
uint32_t RESERVED33[63U]; /**< Reserved for future use */
__IOM uint32_t CTRL_CLR; /**< Control */
uint32_t RESERVED34[1U]; /**< Reserved for future use */
__IOM uint32_t DMEM0RETNCTRL_CLR; /**< DMEM0 Retention Control */
uint32_t RESERVED35[64U]; /**< Reserved for future use */
__IOM uint32_t RAMBIASCONF_CLR; /**< RAM Bias Configuration */
uint32_t RESERVED36[60U]; /**< Reserved for future use */
__IOM uint32_t RADIORAMRETNCTRL_CLR; /**< RADIO RAM Retention Control Register */
uint32_t RESERVED37[1U]; /**< Reserved for future use */
__IOM uint32_t RADIOECCCTRL_CLR; /**< RADIO RAM ECC Control Register */
uint32_t RESERVED38[1U]; /**< Reserved for future use */
__IM uint32_t SEQRAMECCADDR_CLR; /**< SEQRAM ECC Address */
__IM uint32_t FRCRAMECCADDR_CLR; /**< FRCRAM ECC Address */
__IOM uint32_t ICACHERAMRETNCTRL_CLR; /**< HOST ICACHERAM Retention Control */
__IOM uint32_t DMEM0PORTMAPSEL_CLR; /**< DMEM0 port remap selection */
uint32_t RESERVED39[120U]; /**< Reserved for future use */
__IOM uint32_t ROOTDATA0_CLR; /**< Data Register 0 */
__IOM uint32_t ROOTDATA1_CLR; /**< Data Register 1 */
__IM uint32_t ROOTLOCKSTATUS_CLR; /**< Lock Status */
__IOM uint32_t ROOTSESWVERSION_CLR; /**< SE SW Version */
uint32_t RESERVED40[1U]; /**< Reserved for future use */
uint32_t RESERVED41[635U]; /**< Reserved for future use */
uint32_t RESERVED42[1U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP version ID */
__IOM uint32_t IF_TGL; /**< Interrupt Flag */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable */
uint32_t RESERVED43[1U]; /**< Reserved for future use */
__IOM uint32_t CHIPREVHW_TGL; /**< Chip Revision, Hard-wired */
__IOM uint32_t CHIPREV_TGL; /**< Part Family and Revision Values */
uint32_t RESERVED44[2U]; /**< Reserved for future use */
__IOM uint32_t CFGSYSTIC_TGL; /**< SysTick clock source */
uint32_t RESERVED45[54U]; /**< Reserved for future use */
uint32_t RESERVED46[1U]; /**< Reserved for future use */
uint32_t RESERVED47[63U]; /**< Reserved for future use */
__IOM uint32_t CTRL_TGL; /**< Control */
uint32_t RESERVED48[1U]; /**< Reserved for future use */
__IOM uint32_t DMEM0RETNCTRL_TGL; /**< DMEM0 Retention Control */
uint32_t RESERVED49[64U]; /**< Reserved for future use */
__IOM uint32_t RAMBIASCONF_TGL; /**< RAM Bias Configuration */
uint32_t RESERVED50[60U]; /**< Reserved for future use */
__IOM uint32_t RADIORAMRETNCTRL_TGL; /**< RADIO RAM Retention Control Register */
uint32_t RESERVED51[1U]; /**< Reserved for future use */
__IOM uint32_t RADIOECCCTRL_TGL; /**< RADIO RAM ECC Control Register */
uint32_t RESERVED52[1U]; /**< Reserved for future use */
__IM uint32_t SEQRAMECCADDR_TGL; /**< SEQRAM ECC Address */
__IM uint32_t FRCRAMECCADDR_TGL; /**< FRCRAM ECC Address */
__IOM uint32_t ICACHERAMRETNCTRL_TGL; /**< HOST ICACHERAM Retention Control */
__IOM uint32_t DMEM0PORTMAPSEL_TGL; /**< DMEM0 port remap selection */
uint32_t RESERVED53[120U]; /**< Reserved for future use */
__IOM uint32_t ROOTDATA0_TGL; /**< Data Register 0 */
__IOM uint32_t ROOTDATA1_TGL; /**< Data Register 1 */
__IM uint32_t ROOTLOCKSTATUS_TGL; /**< Lock Status */
__IOM uint32_t ROOTSESWVERSION_TGL; /**< SE SW Version */
uint32_t RESERVED54[1U]; /**< Reserved for future use */
} SYSCFG_TypeDef;
/** @} End of group EFR32ZG23_SYSCFG */
/**************************************************************************//**
* @addtogroup EFR32ZG23_SYSCFG
* @{
* @defgroup EFR32ZG23_SYSCFG_BitFields SYSCFG Bit Fields
* @{
*****************************************************************************/
/* Bit fields for SYSCFG IPVERSION */
#define _SYSCFG_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for SYSCFG_IPVERSION */
#define _SYSCFG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_IPVERSION */
#define _SYSCFG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSCFG_IPVERSION */
#define _SYSCFG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_IPVERSION */
#define _SYSCFG_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_IPVERSION */
#define SYSCFG_IPVERSION_IPVERSION_DEFAULT (_SYSCFG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IPVERSION */
/* Bit fields for SYSCFG IF */
#define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */
#define _SYSCFG_IF_MASK 0x33003F0FUL /**< Mask for SYSCFG_IF */
#define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt Flag */
#define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */
#define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */
#define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt Flag */
#define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */
#define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */
#define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt Flag */
#define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */
#define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */
#define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt Flag */
#define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */
#define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */
#define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FPIOC (0x1UL << 8) /**< FPU Invalid Operation interrupt flag */
#define _SYSCFG_IF_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */
#define _SYSCFG_IF_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */
#define _SYSCFG_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FPIOC_DEFAULT (_SYSCFG_IF_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FPDZC (0x1UL << 9) /**< FPU Divide by zero interrupt flag */
#define _SYSCFG_IF_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */
#define _SYSCFG_IF_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */
#define _SYSCFG_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FPDZC_DEFAULT (_SYSCFG_IF_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FPUFC (0x1UL << 10) /**< FPU Underflow interrupt flag */
#define _SYSCFG_IF_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */
#define _SYSCFG_IF_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */
#define _SYSCFG_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FPUFC_DEFAULT (_SYSCFG_IF_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FPOFC (0x1UL << 11) /**< FPU Overflow interrupt flag */
#define _SYSCFG_IF_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */
#define _SYSCFG_IF_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */
#define _SYSCFG_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FPOFC_DEFAULT (_SYSCFG_IF_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FPIDC (0x1UL << 12) /**< FPU Input denormal interrupt flag */
#define _SYSCFG_IF_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */
#define _SYSCFG_IF_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */
#define _SYSCFG_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FPIDC_DEFAULT (_SYSCFG_IF_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FPIXC (0x1UL << 13) /**< FPU Inexact interrupt flag */
#define _SYSCFG_IF_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */
#define _SYSCFG_IF_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */
#define _SYSCFG_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FPIXC_DEFAULT (_SYSCFG_IF_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Flag */
#define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */
#define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */
#define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Flag */
#define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */
#define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */
#define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Flag */
#define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */
#define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */
#define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Flag */
#define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */
#define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */
#define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
#define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */
/* Bit fields for SYSCFG IEN */
#define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */
#define _SYSCFG_IEN_MASK 0x33003F0FUL /**< Mask for SYSCFG_IEN */
#define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software Interrupt Enable */
#define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */
#define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */
#define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software Interrupt Enable */
#define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */
#define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */
#define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software Interrupt Enable */
#define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */
#define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */
#define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software Interrupt Enable */
#define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */
#define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */
#define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FPIOC (0x1UL << 8) /**< FPU Invalid Operation Interrupt Enable */
#define _SYSCFG_IEN_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */
#define _SYSCFG_IEN_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */
#define _SYSCFG_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FPIOC_DEFAULT (_SYSCFG_IEN_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FPDZC (0x1UL << 9) /**< FPU Divide by zero Interrupt Enable */
#define _SYSCFG_IEN_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */
#define _SYSCFG_IEN_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */
#define _SYSCFG_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FPDZC_DEFAULT (_SYSCFG_IEN_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FPUFC (0x1UL << 10) /**< FPU Underflow Interrupt Enable */
#define _SYSCFG_IEN_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */
#define _SYSCFG_IEN_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */
#define _SYSCFG_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FPUFC_DEFAULT (_SYSCFG_IEN_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FPOFC (0x1UL << 11) /**< FPU Overflow Interrupt Enable */
#define _SYSCFG_IEN_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */
#define _SYSCFG_IEN_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */
#define _SYSCFG_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FPOFC_DEFAULT (_SYSCFG_IEN_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FPIDC (0x1UL << 12) /**< FPU Input denormal Interrupt Enable */
#define _SYSCFG_IEN_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */
#define _SYSCFG_IEN_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */
#define _SYSCFG_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FPIDC_DEFAULT (_SYSCFG_IEN_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FPIXC (0x1UL << 13) /**< FPU Inexact Interrupt Enable */
#define _SYSCFG_IEN_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */
#define _SYSCFG_IEN_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */
#define _SYSCFG_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FPIXC_DEFAULT (_SYSCFG_IEN_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Enable */
#define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */
#define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */
#define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Enable */
#define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */
#define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */
#define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Enable */
#define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */
#define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */
#define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Enable */
#define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */
#define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */
#define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
#define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */
/* Bit fields for SYSCFG CHIPREVHW */
#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00000E01UL /**< Default value for SYSCFG_CHIPREVHW */
#define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */
#define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */
#define _SYSCFG_CHIPREVHW_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */
#define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */
#define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */
#define _SYSCFG_CHIPREVHW_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */
#define _SYSCFG_CHIPREVHW_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */
#define _SYSCFG_CHIPREVHW_FAMILY_DEFAULT 0x00000038UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */
#define SYSCFG_CHIPREVHW_FAMILY_DEFAULT (_SYSCFG_CHIPREVHW_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */
#define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */
#define _SYSCFG_CHIPREVHW_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */
#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */
#define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */
/* Bit fields for SYSCFG CHIPREV */
#define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */
#define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */
#define _SYSCFG_CHIPREV_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */
#define _SYSCFG_CHIPREV_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */
#define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */
#define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */
#define _SYSCFG_CHIPREV_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */
#define _SYSCFG_CHIPREV_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */
#define _SYSCFG_CHIPREV_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */
#define SYSCFG_CHIPREV_FAMILY_DEFAULT (_SYSCFG_CHIPREV_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */
#define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */
#define _SYSCFG_CHIPREV_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */
#define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */
#define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */
/* Bit fields for SYSCFG CFGSYSTIC */
#define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */
#define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */
#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */
#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */
#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */
#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */
#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */
/* Bit fields for SYSCFG CTRL */
#define _SYSCFG_CTRL_RESETVALUE 0x00000023UL /**< Default value for SYSCFG_CTRL */
#define _SYSCFG_CTRL_MASK 0x00000023UL /**< Mask for SYSCFG_CTRL */
#define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enabl */
#define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */
#define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */
#define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */
#define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */
#define SYSCFG_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Disabled Clkbus Bus Fault Enable */
#define _SYSCFG_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for SYSCFG_CLKDISFAULTEN */
#define _SYSCFG_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for SYSCFG_CLKDISFAULTEN */
#define _SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */
#define SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT (_SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_CTRL */
#define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC error bus fault response ena */
#define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */
#define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */
#define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */
#define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */
/* Bit fields for SYSCFG DMEM0RETNCTRL */
#define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */
#define _SYSCFG_DMEM0RETNCTRL_MASK 0x00000007UL /**< Mask for SYSCFG_DMEM0RETNCTRL */
#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */
#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0x7UL /**< Bit mask for SYSCFG_RAMRETNCTRL */
#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */
#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */
#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3 0x00000004UL /**< Mode BLK3 for SYSCFG_DMEM0RETNCTRL */
#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO3 0x00000006UL /**< Mode BLK2TO3 for SYSCFG_DMEM0RETNCTRL */
#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO3 0x00000007UL /**< Mode BLK1TO3 for SYSCFG_DMEM0RETNCTRL */
#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/
#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */
#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3 << 0) /**< Shifted mode BLK3 for SYSCFG_DMEM0RETNCTRL */
#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO3 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for SYSCFG_DMEM0RETNCTRL*/
#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO3 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for SYSCFG_DMEM0RETNCTRL*/
/* Bit fields for SYSCFG RAMBIASCONF */
#define _SYSCFG_RAMBIASCONF_RESETVALUE 0x00000002UL /**< Default value for SYSCFG_RAMBIASCONF */
#define _SYSCFG_RAMBIASCONF_MASK 0x0000000FUL /**< Mask for SYSCFG_RAMBIASCONF */
#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMBIASCTRL */
#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_MASK 0xFUL /**< Bit mask for SYSCFG_RAMBIASCTRL */
#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_RAMBIASCONF */
#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_No 0x00000000UL /**< Mode No for SYSCFG_RAMBIASCONF */
#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 0x00000001UL /**< Mode VSB100 for SYSCFG_RAMBIASCONF */
#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 0x00000002UL /**< Mode VSB200 for SYSCFG_RAMBIASCONF */
#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 0x00000004UL /**< Mode VSB300 for SYSCFG_RAMBIASCONF */
#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 0x00000008UL /**< Mode VSB400 for SYSCFG_RAMBIASCONF */
#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RAMBIASCONF */
#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_No (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_No << 0) /**< Shifted mode No for SYSCFG_RAMBIASCONF */
#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 << 0) /**< Shifted mode VSB100 for SYSCFG_RAMBIASCONF */
#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 << 0) /**< Shifted mode VSB200 for SYSCFG_RAMBIASCONF */
#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 << 0) /**< Shifted mode VSB300 for SYSCFG_RAMBIASCONF */
#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 << 0) /**< Shifted mode VSB400 for SYSCFG_RAMBIASCONF */
/* Bit fields for SYSCFG RADIORAMRETNCTRL */
#define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */
#define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */
#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */
#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */
#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */
#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */
#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */
#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */
#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */
#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/
#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/
#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/
#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/
#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/
#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */
#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */
#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */
#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */
#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */
#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */
#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/
#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/
#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/
/* Bit fields for SYSCFG RADIOECCCTRL */
#define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */
#define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */
#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */
#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */
#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */
#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */
#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/
#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */
#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */
#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */
#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */
#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/
#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */
#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */
#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */
#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */
#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/
#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */
#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */
#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */
#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */
#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/
/* Bit fields for SYSCFG SEQRAMECCADDR */
#define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */
#define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */
#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */
#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */
#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */
#define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/
/* Bit fields for SYSCFG FRCRAMECCADDR */
#define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */
#define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */
#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */
#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */
#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */
#define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/
/* Bit fields for SYSCFG ICACHERAMRETNCTRL */
#define _SYSCFG_ICACHERAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ICACHERAMRETNCTRL */
#define _SYSCFG_ICACHERAMRETNCTRL_MASK 0x00000001UL /**< Mask for SYSCFG_ICACHERAMRETNCTRL */
#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL (0x1UL << 0) /**< ICACHERAM Retention control */
#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */
#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_MASK 0x1UL /**< Bit mask for SYSCFG_RAMRETNCTRL */
#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL */
#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_ICACHERAMRETNCTRL */
#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL */
#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL*/
#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_ICACHERAMRETNCTRL*/
#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL*/
/* Bit fields for SYSCFG DMEM0PORTMAPSEL */
#define _SYSCFG_DMEM0PORTMAPSEL_RESETVALUE 0x00000013UL /**< Default value for SYSCFG_DMEM0PORTMAPSEL */
#define _SYSCFG_DMEM0PORTMAPSEL_MASK 0x0000001FUL /**< Mask for SYSCFG_DMEM0PORTMAPSEL */
#define SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL (0x1UL << 0) /**< LDMA portmap selection */
#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT 0 /**< Shift value for SYSCFG_LDMAPORTSEL */
#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_MASK 0x1UL /**< Bit mask for SYSCFG_LDMAPORTSEL */
#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */
#define SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/
#define SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL (0x1UL << 1) /**< SRWAES portmap selection */
#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT 1 /**< Shift value for SYSCFG_SRWAESPORTSEL */
#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_MASK 0x2UL /**< Bit mask for SYSCFG_SRWAESPORTSEL */
#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */
#define SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/
#define SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL (0x1UL << 2) /**< AHBSRW portmap selection */
#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT 2 /**< Shift value for SYSCFG_AHBSRWPORTSEL */
#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_MASK 0x4UL /**< Bit mask for SYSCFG_AHBSRWPORTSEL */
#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */
#define SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/
#define SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL (0x1UL << 3) /**< SRWECA0 portmap selection */
#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT 3 /**< Shift value for SYSCFG_SRWECA0PORTSEL */
#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_MASK 0x8UL /**< Bit mask for SYSCFG_SRWECA0PORTSEL */
#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */
#define SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/
#define SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL (0x1UL << 4) /**< SRWECA1 portmap selection */
#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT 4 /**< Shift value for SYSCFG_SRWECA1PORTSEL */
#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_MASK 0x10UL /**< Bit mask for SYSCFG_SRWECA1PORTSEL */
#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */
#define SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/
/* Bit fields for SYSCFG ROOTDATA0 */
#define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */
#define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */
#define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */
#define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */
#define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */
#define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */
/* Bit fields for SYSCFG ROOTDATA1 */
#define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */
#define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */
#define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */
#define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */
#define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */
#define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */
/* Bit fields for SYSCFG ROOTLOCKSTATUS */
#define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x007F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */
#define _SYSCFG_ROOTLOCKSTATUS_MASK 0x807F0107UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */
#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */
#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
#define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */
#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
#define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */
#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */
#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 16) /**< User Debug Access Port Lock */
#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGAPLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 17) /**< User Invasive Debug Lock */
#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERDBGLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERDBGLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 18) /**< User Non-invasive Debug Lock */
#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERNIDLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERNIDLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 19) /**< User Secure Invasive Debug Lock */
#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPIDLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 20) /**< User Secure Non-invasive Debug Lock */
#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERSPNIDLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK (0x1UL << 21) /**< Radio Invasive Debug Lock */
#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_SHIFT 21 /**< Shift value for SYSCFG_RADIOIDBGLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_MASK 0x200000UL /**< Bit mask for SYSCFG_RADIOIDBGLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK (0x1UL << 22) /**< Radio Non-invasive Debug Lock */
#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_SHIFT 22 /**< Shift value for SYSCFG_RADIONIDBGLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_MASK 0x400000UL /**< Bit mask for SYSCFG_RADIONIDBGLOCK */
#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED (0x1UL << 31) /**< E-Fuse Unlocked */
#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_SHIFT 31 /**< Shift value for SYSCFG_EFUSEUNLOCKED */
#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_MASK 0x80000000UL /**< Bit mask for SYSCFG_EFUSEUNLOCKED */
#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT << 31) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
/* Bit fields for SYSCFG ROOTSESWVERSION */
#define _SYSCFG_ROOTSESWVERSION_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTSESWVERSION */
#define _SYSCFG_ROOTSESWVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTSESWVERSION */
#define _SYSCFG_ROOTSESWVERSION_SWVERSION_SHIFT 0 /**< Shift value for SYSCFG_SWVERSION */
#define _SYSCFG_ROOTSESWVERSION_SWVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SWVERSION */
#define _SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTSESWVERSION */
#define SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT (_SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTSESWVERSION*/
/** @} End of group EFR32ZG23_SYSCFG_BitFields */
/** @} End of group EFR32ZG23_SYSCFG */
/**************************************************************************//**
* @defgroup EFR32ZG23_SYSCFG_CFGNS SYSCFG_CFGNS
* @{
* @brief EFR32ZG23 SYSCFG_CFGNS Register Declaration.
*****************************************************************************/
/** SYSCFG_CFGNS Register Declaration. */
typedef struct {
uint32_t RESERVED0[7U]; /**< Reserved for future use */
__IOM uint32_t CFGNSTCALIB; /**< Configure Non-Secure Sys-Tick cal. */
uint32_t RESERVED1[376U]; /**< Reserved for future use */
__IOM uint32_t ROOTNSDATA0; /**< Data Register 0 */
__IOM uint32_t ROOTNSDATA1; /**< Data Register 1 */
uint32_t RESERVED2[1U]; /**< Reserved for future use */
uint32_t RESERVED3[637U]; /**< Reserved for future use */
uint32_t RESERVED4[7U]; /**< Reserved for future use */
__IOM uint32_t CFGNSTCALIB_SET; /**< Configure Non-Secure Sys-Tick cal. */
uint32_t RESERVED5[376U]; /**< Reserved for future use */
__IOM uint32_t ROOTNSDATA0_SET; /**< Data Register 0 */
__IOM uint32_t ROOTNSDATA1_SET; /**< Data Register 1 */
uint32_t RESERVED6[1U]; /**< Reserved for future use */
uint32_t RESERVED7[637U]; /**< Reserved for future use */
uint32_t RESERVED8[7U]; /**< Reserved for future use */
__IOM uint32_t CFGNSTCALIB_CLR; /**< Configure Non-Secure Sys-Tick cal. */
uint32_t RESERVED9[376U]; /**< Reserved for future use */
__IOM uint32_t ROOTNSDATA0_CLR; /**< Data Register 0 */
__IOM uint32_t ROOTNSDATA1_CLR; /**< Data Register 1 */
uint32_t RESERVED10[1U]; /**< Reserved for future use */
uint32_t RESERVED11[637U]; /**< Reserved for future use */
uint32_t RESERVED12[7U]; /**< Reserved for future use */
__IOM uint32_t CFGNSTCALIB_TGL; /**< Configure Non-Secure Sys-Tick cal. */
uint32_t RESERVED13[376U]; /**< Reserved for future use */
__IOM uint32_t ROOTNSDATA0_TGL; /**< Data Register 0 */
__IOM uint32_t ROOTNSDATA1_TGL; /**< Data Register 1 */
uint32_t RESERVED14[1U]; /**< Reserved for future use */
} SYSCFG_CFGNS_TypeDef;
/** @} End of group EFR32ZG23_SYSCFG_CFGNS */
/**************************************************************************//**
* @addtogroup EFR32ZG23_SYSCFG_CFGNS
* @{
* @defgroup EFR32ZG23_SYSCFG_CFGNS_BitFields SYSCFG_CFGNS Bit Fields
* @{
*****************************************************************************/
/* Bit fields for SYSCFG CFGNSTCALIB */
#define _SYSCFG_CFGNSTCALIB_RESETVALUE 0x01004A37UL /**< Default value for SYSCFG_CFGNSTCALIB */
#define _SYSCFG_CFGNSTCALIB_MASK 0x03FFFFFFUL /**< Mask for SYSCFG_CFGNSTCALIB */
#define _SYSCFG_CFGNSTCALIB_TENMS_SHIFT 0 /**< Shift value for SYSCFG_TENMS */
#define _SYSCFG_CFGNSTCALIB_TENMS_MASK 0xFFFFFFUL /**< Bit mask for SYSCFG_TENMS */
#define _SYSCFG_CFGNSTCALIB_TENMS_DEFAULT 0x00004A37UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */
#define SYSCFG_CFGNSTCALIB_TENMS_DEFAULT (_SYSCFG_CFGNSTCALIB_TENMS_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */
#define SYSCFG_CFGNSTCALIB_SKEW (0x1UL << 24) /**< Skew */
#define _SYSCFG_CFGNSTCALIB_SKEW_SHIFT 24 /**< Shift value for SYSCFG_SKEW */
#define _SYSCFG_CFGNSTCALIB_SKEW_MASK 0x1000000UL /**< Bit mask for SYSCFG_SKEW */
#define _SYSCFG_CFGNSTCALIB_SKEW_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */
#define SYSCFG_CFGNSTCALIB_SKEW_DEFAULT (_SYSCFG_CFGNSTCALIB_SKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */
#define SYSCFG_CFGNSTCALIB_NOREF (0x1UL << 25) /**< No Reference */
#define _SYSCFG_CFGNSTCALIB_NOREF_SHIFT 25 /**< Shift value for SYSCFG_NOREF */
#define _SYSCFG_CFGNSTCALIB_NOREF_MASK 0x2000000UL /**< Bit mask for SYSCFG_NOREF */
#define _SYSCFG_CFGNSTCALIB_NOREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */
#define _SYSCFG_CFGNSTCALIB_NOREF_REF 0x00000000UL /**< Mode REF for SYSCFG_CFGNSTCALIB */
#define _SYSCFG_CFGNSTCALIB_NOREF_NOREF 0x00000001UL /**< Mode NOREF for SYSCFG_CFGNSTCALIB */
#define SYSCFG_CFGNSTCALIB_NOREF_DEFAULT (_SYSCFG_CFGNSTCALIB_NOREF_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */
#define SYSCFG_CFGNSTCALIB_NOREF_REF (_SYSCFG_CFGNSTCALIB_NOREF_REF << 25) /**< Shifted mode REF for SYSCFG_CFGNSTCALIB */
#define SYSCFG_CFGNSTCALIB_NOREF_NOREF (_SYSCFG_CFGNSTCALIB_NOREF_NOREF << 25) /**< Shifted mode NOREF for SYSCFG_CFGNSTCALIB */
/* Bit fields for SYSCFG ROOTNSDATA0 */
#define _SYSCFG_ROOTNSDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA0 */
#define _SYSCFG_ROOTNSDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA0 */
#define _SYSCFG_ROOTNSDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */
#define _SYSCFG_ROOTNSDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */
#define _SYSCFG_ROOTNSDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA0 */
#define SYSCFG_ROOTNSDATA0_DATA_DEFAULT (_SYSCFG_ROOTNSDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA0 */
/* Bit fields for SYSCFG ROOTNSDATA1 */
#define _SYSCFG_ROOTNSDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA1 */
#define _SYSCFG_ROOTNSDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA1 */
#define _SYSCFG_ROOTNSDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */
#define _SYSCFG_ROOTNSDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */
#define _SYSCFG_ROOTNSDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA1 */
#define SYSCFG_ROOTNSDATA1_DATA_DEFAULT (_SYSCFG_ROOTNSDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA1 */
/** @} End of group EFR32ZG23_SYSCFG_CFGNS_BitFields */
/** @} End of group EFR32ZG23_SYSCFG_CFGNS */
/** @} End of group Parts */
#endif /* EFR32ZG23_SYSCFG_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 SYSRTC register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_SYSRTC_H
#define EFR32ZG23_SYSRTC_H
#define SYSRTC_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_SYSRTC SYSRTC
* @{
* @brief EFR32ZG23 SYSRTC Register Declaration.
*****************************************************************************/
/** SYSRTC Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP VERSION */
__IOM uint32_t EN; /**< Module Enable Register */
__IOM uint32_t SWRST; /**< Software Reset Register */
__IOM uint32_t CFG; /**< Configuration Register */
__IOM uint32_t CMD; /**< Command Register */
__IM uint32_t STATUS; /**< Status register */
__IOM uint32_t CNT; /**< Counter Value Register */
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
__IOM uint32_t LOCK; /**< Configuration Lock Register */
uint32_t RESERVED0[3U]; /**< Reserved for future use */
uint32_t RESERVED1[1U]; /**< Reserved for future use */
uint32_t RESERVED2[3U]; /**< Reserved for future use */
__IOM uint32_t GRP0_IF; /**< Group Interrupt Flags */
__IOM uint32_t GRP0_IEN; /**< Group Interrupt Enables */
__IOM uint32_t GRP0_CTRL; /**< Group Control Register */
__IOM uint32_t GRP0_CMP0VALUE; /**< Compare 0 Value Register */
__IOM uint32_t GRP0_CMP1VALUE; /**< Compare 1 Value Register */
__IM uint32_t GRP0_CAP0VALUE; /**< Capture 0 Value Register */
__IM uint32_t GRP0_SYNCBUSY; /**< Synchronization busy Register */
uint32_t RESERVED3[1U]; /**< Reserved for future use */
uint32_t RESERVED4[1U]; /**< Reserved for future use */
uint32_t RESERVED5[7U]; /**< Reserved for future use */
uint32_t RESERVED6[1U]; /**< Reserved for future use */
uint32_t RESERVED7[991U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP VERSION */
__IOM uint32_t EN_SET; /**< Module Enable Register */
__IOM uint32_t SWRST_SET; /**< Software Reset Register */
__IOM uint32_t CFG_SET; /**< Configuration Register */
__IOM uint32_t CMD_SET; /**< Command Register */
__IM uint32_t STATUS_SET; /**< Status register */
__IOM uint32_t CNT_SET; /**< Counter Value Register */
__IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */
__IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
uint32_t RESERVED8[3U]; /**< Reserved for future use */
uint32_t RESERVED9[1U]; /**< Reserved for future use */
uint32_t RESERVED10[3U]; /**< Reserved for future use */
__IOM uint32_t GRP0_IF_SET; /**< Group Interrupt Flags */
__IOM uint32_t GRP0_IEN_SET; /**< Group Interrupt Enables */
__IOM uint32_t GRP0_CTRL_SET; /**< Group Control Register */
__IOM uint32_t GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */
__IOM uint32_t GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */
__IM uint32_t GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */
__IM uint32_t GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */
uint32_t RESERVED11[1U]; /**< Reserved for future use */
uint32_t RESERVED12[1U]; /**< Reserved for future use */
uint32_t RESERVED13[7U]; /**< Reserved for future use */
uint32_t RESERVED14[1U]; /**< Reserved for future use */
uint32_t RESERVED15[991U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP VERSION */
__IOM uint32_t EN_CLR; /**< Module Enable Register */
__IOM uint32_t SWRST_CLR; /**< Software Reset Register */
__IOM uint32_t CFG_CLR; /**< Configuration Register */
__IOM uint32_t CMD_CLR; /**< Command Register */
__IM uint32_t STATUS_CLR; /**< Status register */
__IOM uint32_t CNT_CLR; /**< Counter Value Register */
__IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */
__IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
uint32_t RESERVED16[3U]; /**< Reserved for future use */
uint32_t RESERVED17[1U]; /**< Reserved for future use */
uint32_t RESERVED18[3U]; /**< Reserved for future use */
__IOM uint32_t GRP0_IF_CLR; /**< Group Interrupt Flags */
__IOM uint32_t GRP0_IEN_CLR; /**< Group Interrupt Enables */
__IOM uint32_t GRP0_CTRL_CLR; /**< Group Control Register */
__IOM uint32_t GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */
__IOM uint32_t GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */
__IM uint32_t GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */
__IM uint32_t GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */
uint32_t RESERVED19[1U]; /**< Reserved for future use */
uint32_t RESERVED20[1U]; /**< Reserved for future use */
uint32_t RESERVED21[7U]; /**< Reserved for future use */
uint32_t RESERVED22[1U]; /**< Reserved for future use */
uint32_t RESERVED23[991U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP VERSION */
__IOM uint32_t EN_TGL; /**< Module Enable Register */
__IOM uint32_t SWRST_TGL; /**< Software Reset Register */
__IOM uint32_t CFG_TGL; /**< Configuration Register */
__IOM uint32_t CMD_TGL; /**< Command Register */
__IM uint32_t STATUS_TGL; /**< Status register */
__IOM uint32_t CNT_TGL; /**< Counter Value Register */
__IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */
__IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
uint32_t RESERVED24[3U]; /**< Reserved for future use */
uint32_t RESERVED25[1U]; /**< Reserved for future use */
uint32_t RESERVED26[3U]; /**< Reserved for future use */
__IOM uint32_t GRP0_IF_TGL; /**< Group Interrupt Flags */
__IOM uint32_t GRP0_IEN_TGL; /**< Group Interrupt Enables */
__IOM uint32_t GRP0_CTRL_TGL; /**< Group Control Register */
__IOM uint32_t GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */
__IOM uint32_t GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */
__IM uint32_t GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */
__IM uint32_t GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */
uint32_t RESERVED27[1U]; /**< Reserved for future use */
uint32_t RESERVED28[1U]; /**< Reserved for future use */
uint32_t RESERVED29[7U]; /**< Reserved for future use */
uint32_t RESERVED30[1U]; /**< Reserved for future use */
} SYSRTC_TypeDef;
/** @} End of group EFR32ZG23_SYSRTC */
/**************************************************************************//**
* @addtogroup EFR32ZG23_SYSRTC
* @{
* @defgroup EFR32ZG23_SYSRTC_BitFields SYSRTC Bit Fields
* @{
*****************************************************************************/
/* Bit fields for SYSRTC IPVERSION */
#define _SYSRTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SYSRTC_IPVERSION */
#define _SYSRTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_IPVERSION */
#define _SYSRTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSRTC_IPVERSION */
#define _SYSRTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_IPVERSION */
#define _SYSRTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSRTC_IPVERSION */
#define SYSRTC_IPVERSION_IPVERSION_DEFAULT (_SYSRTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_IPVERSION */
/* Bit fields for SYSRTC EN */
#define _SYSRTC_EN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_EN */
#define _SYSRTC_EN_MASK 0x00000003UL /**< Mask for SYSRTC_EN */
#define SYSRTC_EN_EN (0x1UL << 0) /**< SYSRTC Enable */
#define _SYSRTC_EN_EN_SHIFT 0 /**< Shift value for SYSRTC_EN */
#define _SYSRTC_EN_EN_MASK 0x1UL /**< Bit mask for SYSRTC_EN */
#define _SYSRTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */
#define SYSRTC_EN_EN_DEFAULT (_SYSRTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_EN */
#define SYSRTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
#define _SYSRTC_EN_DISABLING_SHIFT 1 /**< Shift value for SYSRTC_DISABLING */
#define _SYSRTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for SYSRTC_DISABLING */
#define _SYSRTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */
#define SYSRTC_EN_DISABLING_DEFAULT (_SYSRTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_EN */
/* Bit fields for SYSRTC SWRST */
#define _SYSRTC_SWRST_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SWRST */
#define _SYSRTC_SWRST_MASK 0x00000003UL /**< Mask for SYSRTC_SWRST */
#define SYSRTC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */
#define _SYSRTC_SWRST_SWRST_SHIFT 0 /**< Shift value for SYSRTC_SWRST */
#define _SYSRTC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for SYSRTC_SWRST */
#define _SYSRTC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */
#define SYSRTC_SWRST_SWRST_DEFAULT (_SYSRTC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SWRST */
#define SYSRTC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */
#define _SYSRTC_SWRST_RESETTING_SHIFT 1 /**< Shift value for SYSRTC_RESETTING */
#define _SYSRTC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for SYSRTC_RESETTING */
#define _SYSRTC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */
#define SYSRTC_SWRST_RESETTING_DEFAULT (_SYSRTC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SWRST */
/* Bit fields for SYSRTC CFG */
#define _SYSRTC_CFG_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CFG */
#define _SYSRTC_CFG_MASK 0x00000001UL /**< Mask for SYSRTC_CFG */
#define SYSRTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */
#define _SYSRTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for SYSRTC_DEBUGRUN */
#define _SYSRTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for SYSRTC_DEBUGRUN */
#define _SYSRTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CFG */
#define _SYSRTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for SYSRTC_CFG */
#define _SYSRTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for SYSRTC_CFG */
#define SYSRTC_CFG_DEBUGRUN_DEFAULT (_SYSRTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CFG */
#define SYSRTC_CFG_DEBUGRUN_DISABLE (_SYSRTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for SYSRTC_CFG */
#define SYSRTC_CFG_DEBUGRUN_ENABLE (_SYSRTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for SYSRTC_CFG */
/* Bit fields for SYSRTC CMD */
#define _SYSRTC_CMD_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CMD */
#define _SYSRTC_CMD_MASK 0x00000003UL /**< Mask for SYSRTC_CMD */
#define SYSRTC_CMD_START (0x1UL << 0) /**< Start SYSRTC */
#define _SYSRTC_CMD_START_SHIFT 0 /**< Shift value for SYSRTC_START */
#define _SYSRTC_CMD_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */
#define _SYSRTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */
#define SYSRTC_CMD_START_DEFAULT (_SYSRTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CMD */
#define SYSRTC_CMD_STOP (0x1UL << 1) /**< Stop SYSRTC */
#define _SYSRTC_CMD_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */
#define _SYSRTC_CMD_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */
#define _SYSRTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */
#define SYSRTC_CMD_STOP_DEFAULT (_SYSRTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_CMD */
/* Bit fields for SYSRTC STATUS */
#define _SYSRTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_STATUS */
#define _SYSRTC_STATUS_MASK 0x00000007UL /**< Mask for SYSRTC_STATUS */
#define SYSRTC_STATUS_RUNNING (0x1UL << 0) /**< SYSRTC running status */
#define _SYSRTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for SYSRTC_RUNNING */
#define _SYSRTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for SYSRTC_RUNNING */
#define _SYSRTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */
#define SYSRTC_STATUS_RUNNING_DEFAULT (_SYSRTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_STATUS */
#define SYSRTC_STATUS_LOCKSTATUS (0x1UL << 1) /**< Lock Status */
#define _SYSRTC_STATUS_LOCKSTATUS_SHIFT 1 /**< Shift value for SYSRTC_LOCKSTATUS */
#define _SYSRTC_STATUS_LOCKSTATUS_MASK 0x2UL /**< Bit mask for SYSRTC_LOCKSTATUS */
#define _SYSRTC_STATUS_LOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */
#define _SYSRTC_STATUS_LOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SYSRTC_STATUS */
#define _SYSRTC_STATUS_LOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for SYSRTC_STATUS */
#define SYSRTC_STATUS_LOCKSTATUS_DEFAULT (_SYSRTC_STATUS_LOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_STATUS */
#define SYSRTC_STATUS_LOCKSTATUS_UNLOCKED (_SYSRTC_STATUS_LOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for SYSRTC_STATUS */
#define SYSRTC_STATUS_LOCKSTATUS_LOCKED (_SYSRTC_STATUS_LOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for SYSRTC_STATUS */
/* Bit fields for SYSRTC CNT */
#define _SYSRTC_CNT_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CNT */
#define _SYSRTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_CNT */
#define _SYSRTC_CNT_CNT_SHIFT 0 /**< Shift value for SYSRTC_CNT */
#define _SYSRTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CNT */
#define _SYSRTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CNT */
#define SYSRTC_CNT_CNT_DEFAULT (_SYSRTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CNT */
/* Bit fields for SYSRTC SYNCBUSY */
#define _SYSRTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SYNCBUSY */
#define _SYSRTC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for SYSRTC_SYNCBUSY */
#define SYSRTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START bitfield */
#define _SYSRTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for SYSRTC_START */
#define _SYSRTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */
#define _SYSRTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */
#define SYSRTC_SYNCBUSY_START_DEFAULT (_SYSRTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */
#define SYSRTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP bitfield */
#define _SYSRTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */
#define _SYSRTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */
#define _SYSRTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */
#define SYSRTC_SYNCBUSY_STOP_DEFAULT (_SYSRTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */
#define SYSRTC_SYNCBUSY_CNT (0x1UL << 2) /**< Sync busy for CNT bitfield */
#define _SYSRTC_SYNCBUSY_CNT_SHIFT 2 /**< Shift value for SYSRTC_CNT */
#define _SYSRTC_SYNCBUSY_CNT_MASK 0x4UL /**< Bit mask for SYSRTC_CNT */
#define _SYSRTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */
#define SYSRTC_SYNCBUSY_CNT_DEFAULT (_SYSRTC_SYNCBUSY_CNT_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */
/* Bit fields for SYSRTC LOCK */
#define _SYSRTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_LOCK */
#define _SYSRTC_LOCK_MASK 0x0000FFFFUL /**< Mask for SYSRTC_LOCK */
#define _SYSRTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for SYSRTC_LOCKKEY */
#define _SYSRTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for SYSRTC_LOCKKEY */
#define _SYSRTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_LOCK */
#define _SYSRTC_LOCK_LOCKKEY_UNLOCK 0x00004776UL /**< Mode UNLOCK for SYSRTC_LOCK */
#define SYSRTC_LOCK_LOCKKEY_DEFAULT (_SYSRTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_LOCK */
#define SYSRTC_LOCK_LOCKKEY_UNLOCK (_SYSRTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SYSRTC_LOCK */
/* Bit fields for SYSRTC GRP0_IF */
#define _SYSRTC_GRP0_IF_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IF */
#define _SYSRTC_GRP0_IF_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IF */
#define SYSRTC_GRP0_IF_OVF (0x1UL << 0) /**< Overflow Interrupt Flag */
#define _SYSRTC_GRP0_IF_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */
#define _SYSRTC_GRP0_IF_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */
#define _SYSRTC_GRP0_IF_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */
#define SYSRTC_GRP0_IF_OVF_DEFAULT (_SYSRTC_GRP0_IF_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */
#define SYSRTC_GRP0_IF_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Flag */
#define _SYSRTC_GRP0_IF_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */
#define _SYSRTC_GRP0_IF_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */
#define _SYSRTC_GRP0_IF_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */
#define SYSRTC_GRP0_IF_CMP0_DEFAULT (_SYSRTC_GRP0_IF_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */
#define SYSRTC_GRP0_IF_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Flag */
#define _SYSRTC_GRP0_IF_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */
#define _SYSRTC_GRP0_IF_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */
#define _SYSRTC_GRP0_IF_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */
#define SYSRTC_GRP0_IF_CMP1_DEFAULT (_SYSRTC_GRP0_IF_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */
#define SYSRTC_GRP0_IF_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Flag */
#define _SYSRTC_GRP0_IF_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */
#define _SYSRTC_GRP0_IF_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */
#define _SYSRTC_GRP0_IF_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */
#define SYSRTC_GRP0_IF_CAP0_DEFAULT (_SYSRTC_GRP0_IF_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */
/* Bit fields for SYSRTC GRP0_IEN */
#define _SYSRTC_GRP0_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IEN */
#define _SYSRTC_GRP0_IEN_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IEN */
#define SYSRTC_GRP0_IEN_OVF (0x1UL << 0) /**< Overflow Interrupt Enable */
#define _SYSRTC_GRP0_IEN_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */
#define _SYSRTC_GRP0_IEN_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */
#define _SYSRTC_GRP0_IEN_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */
#define SYSRTC_GRP0_IEN_OVF_DEFAULT (_SYSRTC_GRP0_IEN_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */
#define SYSRTC_GRP0_IEN_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Enable */
#define _SYSRTC_GRP0_IEN_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */
#define _SYSRTC_GRP0_IEN_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */
#define _SYSRTC_GRP0_IEN_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */
#define SYSRTC_GRP0_IEN_CMP0_DEFAULT (_SYSRTC_GRP0_IEN_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */
#define SYSRTC_GRP0_IEN_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Enable */
#define _SYSRTC_GRP0_IEN_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */
#define _SYSRTC_GRP0_IEN_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */
#define _SYSRTC_GRP0_IEN_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */
#define SYSRTC_GRP0_IEN_CMP1_DEFAULT (_SYSRTC_GRP0_IEN_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */
#define SYSRTC_GRP0_IEN_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Enable */
#define _SYSRTC_GRP0_IEN_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */
#define _SYSRTC_GRP0_IEN_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */
#define _SYSRTC_GRP0_IEN_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */
#define SYSRTC_GRP0_IEN_CAP0_DEFAULT (_SYSRTC_GRP0_IEN_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */
/* Bit fields for SYSRTC GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_MASK 0x000007FFUL /**< Mask for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP0EN (0x1UL << 0) /**< Compare 0 Enable */
#define _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT 0 /**< Shift value for SYSRTC_CMP0EN */
#define _SYSRTC_GRP0_CTRL_CMP0EN_MASK 0x1UL /**< Bit mask for SYSRTC_CMP0EN */
#define _SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP1EN (0x1UL << 1) /**< Compare 1 Enable */
#define _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT 1 /**< Shift value for SYSRTC_CMP1EN */
#define _SYSRTC_GRP0_CTRL_CMP1EN_MASK 0x2UL /**< Bit mask for SYSRTC_CMP1EN */
#define _SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CAP0EN (0x1UL << 2) /**< Capture 0 Enable */
#define _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT 2 /**< Shift value for SYSRTC_CAP0EN */
#define _SYSRTC_GRP0_CTRL_CAP0EN_MASK 0x4UL /**< Bit mask for SYSRTC_CAP0EN */
#define _SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT 3 /**< Shift value for SYSRTC_CMP0CMOA */
#define _SYSRTC_GRP0_CTRL_CMP0CMOA_MASK 0x38UL /**< Bit mask for SYSRTC_CMP0CMOA */
#define _SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR << 3) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP0CMOA_SET (_SYSRTC_GRP0_CTRL_CMP0CMOA_SET << 3) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE << 3) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE << 3) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF << 3) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT 6 /**< Shift value for SYSRTC_CMP1CMOA */
#define _SYSRTC_GRP0_CTRL_CMP1CMOA_MASK 0x1C0UL /**< Bit mask for SYSRTC_CMP1CMOA */
#define _SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR << 6) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP1CMOA_SET (_SYSRTC_GRP0_CTRL_CMP1CMOA_SET << 6) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE << 6) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE << 6) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << 6) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT 9 /**< Shift value for SYSRTC_CAP0EDGE */
#define _SYSRTC_GRP0_CTRL_CAP0EDGE_MASK 0x600UL /**< Bit mask for SYSRTC_CAP0EDGE */
#define _SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CAP0EDGE_RISING 0x00000000UL /**< Mode RISING for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING 0x00000001UL /**< Mode FALLING for SYSRTC_GRP0_CTRL */
#define _SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH 0x00000002UL /**< Mode BOTH for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CAP0EDGE_RISING (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << 9) /**< Shifted mode RISING for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING (_SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING << 9) /**< Shifted mode FALLING for SYSRTC_GRP0_CTRL */
#define SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH (_SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH << 9) /**< Shifted mode BOTH for SYSRTC_GRP0_CTRL */
/* Bit fields for SYSRTC GRP0_CMP0VALUE */
#define _SYSRTC_GRP0_CMP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP0VALUE */
#define _SYSRTC_GRP0_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP0VALUE */
#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP0VALUE */
#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP0VALUE */
#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP0VALUE */
#define SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP0VALUE*/
/* Bit fields for SYSRTC GRP0_CMP1VALUE */
#define _SYSRTC_GRP0_CMP1VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP1VALUE */
#define _SYSRTC_GRP0_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP1VALUE */
#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP1VALUE */
#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP1VALUE */
#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP1VALUE */
#define SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP1VALUE*/
/* Bit fields for SYSRTC GRP0_CAP0VALUE */
#define _SYSRTC_GRP0_CAP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CAP0VALUE */
#define _SYSRTC_GRP0_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CAP0VALUE */
#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CAP0VALUE */
#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CAP0VALUE */
#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CAP0VALUE */
#define SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT (_SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CAP0VALUE*/
/* Bit fields for SYSRTC GRP0_SYNCBUSY */
#define _SYSRTC_GRP0_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_SYNCBUSY */
#define _SYSRTC_GRP0_SYNCBUSY_MASK 0x00000007UL /**< Mask for SYSRTC_GRP0_SYNCBUSY */
#define SYSRTC_GRP0_SYNCBUSY_CTRL (0x1UL << 0) /**< Sync busy for CTRL register */
#define _SYSRTC_GRP0_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for SYSRTC_CTRL */
#define _SYSRTC_GRP0_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for SYSRTC_CTRL */
#define _SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */
#define SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/
#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE (0x1UL << 1) /**< Sync busy for CMP0VALUE register */
#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_SHIFT 1 /**< Shift value for SYSRTC_CMP0VALUE */
#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0VALUE */
#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */
#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/
#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE (0x1UL << 2) /**< Sync busy for CMP1VALUE register */
#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_SHIFT 2 /**< Shift value for SYSRTC_CMP1VALUE */
#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1VALUE */
#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */
#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/
/** @} End of group EFR32ZG23_SYSRTC_BitFields */
/** @} End of group EFR32ZG23_SYSRTC */
/** @} End of group Parts */
#endif /* EFR32ZG23_SYSRTC_H */
#ifdef __cplusplus
}
#endif

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cpu/efm32/families/efr32zg23/include/vendor/efr32zg23_ulfrco.h vendored Normal file
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/**************************************************************************//**
* @file
* @brief EFR32ZG23 ULFRCO register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_ULFRCO_H
#define EFR32ZG23_ULFRCO_H
#define ULFRCO_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_ULFRCO ULFRCO
* @{
* @brief EFR32ZG23 ULFRCO Register Declaration.
*****************************************************************************/
/** ULFRCO Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP version */
uint32_t RESERVED0[1U]; /**< Reserved for future use */
__IM uint32_t STATUS; /**< Status Register */
uint32_t RESERVED1[2U]; /**< Reserved for future use */
__IOM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
uint32_t RESERVED2[1017U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP version */
uint32_t RESERVED3[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_SET; /**< Status Register */
uint32_t RESERVED4[2U]; /**< Reserved for future use */
__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
uint32_t RESERVED5[1017U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP version */
uint32_t RESERVED6[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_CLR; /**< Status Register */
uint32_t RESERVED7[2U]; /**< Reserved for future use */
__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
uint32_t RESERVED8[1017U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP version */
uint32_t RESERVED9[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_TGL; /**< Status Register */
uint32_t RESERVED10[2U]; /**< Reserved for future use */
__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
} ULFRCO_TypeDef;
/** @} End of group EFR32ZG23_ULFRCO */
/**************************************************************************//**
* @addtogroup EFR32ZG23_ULFRCO
* @{
* @defgroup EFR32ZG23_ULFRCO_BitFields ULFRCO Bit Fields
* @{
*****************************************************************************/
/* Bit fields for ULFRCO IPVERSION */
#define _ULFRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ULFRCO_IPVERSION */
#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */
#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */
#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */
#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ULFRCO_IPVERSION */
#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */
/* Bit fields for ULFRCO STATUS */
#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */
#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */
#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */
#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */
#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */
#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */
#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */
#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */
#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */
#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */
#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */
#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */
/* Bit fields for ULFRCO IF */
#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */
#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */
#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */
#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */
#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */
#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */
#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */
#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */
#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */
#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */
#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */
#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */
#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */
#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */
#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */
#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */
#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */
/* Bit fields for ULFRCO IEN */
#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */
#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */
#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */
#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */
#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */
#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */
#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */
#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */
#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */
#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */
#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */
#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */
#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */
#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */
#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */
#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */
#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */
/** @} End of group EFR32ZG23_ULFRCO_BitFields */
/** @} End of group EFR32ZG23_ULFRCO */
/** @} End of group Parts */
#endif /* EFR32ZG23_ULFRCO_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 VDAC register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_VDAC_H
#define EFR32ZG23_VDAC_H
#define VDAC_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_VDAC VDAC
* @{
* @brief EFR32ZG23 VDAC Register Declaration.
*****************************************************************************/
/** VDAC Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IPVERSION */
__IOM uint32_t EN; /**< Module Enable */
__IOM uint32_t SWRST; /**< Software Reset Register */
__IOM uint32_t CFG; /**< Config Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t CH0CFG; /**< Channel 0 Config Register */
__IOM uint32_t CH1CFG; /**< Channel 1 Config Register */
__IOM uint32_t CMD; /**< Command Register */
__IOM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IOM uint32_t CH0F; /**< Channel 0 Data Write Fifo */
__IOM uint32_t CH1F; /**< Channel 1 Data Write Fifo */
__IOM uint32_t OUTCTRL; /**< DAC Output Control */
__IOM uint32_t OUTTIMERCFG; /**< DAC Out Timer Config Register */
uint32_t RESERVED0[50U]; /**< Reserved for future use */
uint32_t RESERVED1[1U]; /**< Reserved for future use */
uint32_t RESERVED2[63U]; /**< Reserved for future use */
uint32_t RESERVED3[1U]; /**< Reserved for future use */
uint32_t RESERVED4[895U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IPVERSION */
__IOM uint32_t EN_SET; /**< Module Enable */
__IOM uint32_t SWRST_SET; /**< Software Reset Register */
__IOM uint32_t CFG_SET; /**< Config Register */
__IM uint32_t STATUS_SET; /**< Status Register */
__IOM uint32_t CH0CFG_SET; /**< Channel 0 Config Register */
__IOM uint32_t CH1CFG_SET; /**< Channel 1 Config Register */
__IOM uint32_t CMD_SET; /**< Command Register */
__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
__IOM uint32_t CH0F_SET; /**< Channel 0 Data Write Fifo */
__IOM uint32_t CH1F_SET; /**< Channel 1 Data Write Fifo */
__IOM uint32_t OUTCTRL_SET; /**< DAC Output Control */
__IOM uint32_t OUTTIMERCFG_SET; /**< DAC Out Timer Config Register */
uint32_t RESERVED5[50U]; /**< Reserved for future use */
uint32_t RESERVED6[1U]; /**< Reserved for future use */
uint32_t RESERVED7[63U]; /**< Reserved for future use */
uint32_t RESERVED8[1U]; /**< Reserved for future use */
uint32_t RESERVED9[895U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IPVERSION */
__IOM uint32_t EN_CLR; /**< Module Enable */
__IOM uint32_t SWRST_CLR; /**< Software Reset Register */
__IOM uint32_t CFG_CLR; /**< Config Register */
__IM uint32_t STATUS_CLR; /**< Status Register */
__IOM uint32_t CH0CFG_CLR; /**< Channel 0 Config Register */
__IOM uint32_t CH1CFG_CLR; /**< Channel 1 Config Register */
__IOM uint32_t CMD_CLR; /**< Command Register */
__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
__IOM uint32_t CH0F_CLR; /**< Channel 0 Data Write Fifo */
__IOM uint32_t CH1F_CLR; /**< Channel 1 Data Write Fifo */
__IOM uint32_t OUTCTRL_CLR; /**< DAC Output Control */
__IOM uint32_t OUTTIMERCFG_CLR; /**< DAC Out Timer Config Register */
uint32_t RESERVED10[50U]; /**< Reserved for future use */
uint32_t RESERVED11[1U]; /**< Reserved for future use */
uint32_t RESERVED12[63U]; /**< Reserved for future use */
uint32_t RESERVED13[1U]; /**< Reserved for future use */
uint32_t RESERVED14[895U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IPVERSION */
__IOM uint32_t EN_TGL; /**< Module Enable */
__IOM uint32_t SWRST_TGL; /**< Software Reset Register */
__IOM uint32_t CFG_TGL; /**< Config Register */
__IM uint32_t STATUS_TGL; /**< Status Register */
__IOM uint32_t CH0CFG_TGL; /**< Channel 0 Config Register */
__IOM uint32_t CH1CFG_TGL; /**< Channel 1 Config Register */
__IOM uint32_t CMD_TGL; /**< Command Register */
__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
__IOM uint32_t CH0F_TGL; /**< Channel 0 Data Write Fifo */
__IOM uint32_t CH1F_TGL; /**< Channel 1 Data Write Fifo */
__IOM uint32_t OUTCTRL_TGL; /**< DAC Output Control */
__IOM uint32_t OUTTIMERCFG_TGL; /**< DAC Out Timer Config Register */
uint32_t RESERVED15[50U]; /**< Reserved for future use */
uint32_t RESERVED16[1U]; /**< Reserved for future use */
uint32_t RESERVED17[63U]; /**< Reserved for future use */
uint32_t RESERVED18[1U]; /**< Reserved for future use */
} VDAC_TypeDef;
/** @} End of group EFR32ZG23_VDAC */
/**************************************************************************//**
* @addtogroup EFR32ZG23_VDAC
* @{
* @defgroup EFR32ZG23_VDAC_BitFields VDAC Bit Fields
* @{
*****************************************************************************/
/* Bit fields for VDAC IPVERSION */
#define _VDAC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for VDAC_IPVERSION */
#define _VDAC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for VDAC_IPVERSION */
#define _VDAC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for VDAC_IPVERSION */
#define _VDAC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for VDAC_IPVERSION */
#define _VDAC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IPVERSION */
#define VDAC_IPVERSION_IPVERSION_DEFAULT (_VDAC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IPVERSION */
/* Bit fields for VDAC EN */
#define _VDAC_EN_RESETVALUE 0x00000000UL /**< Default value for VDAC_EN */
#define _VDAC_EN_MASK 0x00000003UL /**< Mask for VDAC_EN */
#define VDAC_EN_EN (0x1UL << 0) /**< VDAC Module Enable */
#define _VDAC_EN_EN_SHIFT 0 /**< Shift value for VDAC_EN */
#define _VDAC_EN_EN_MASK 0x1UL /**< Bit mask for VDAC_EN */
#define _VDAC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */
#define _VDAC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_EN */
#define _VDAC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for VDAC_EN */
#define VDAC_EN_EN_DEFAULT (_VDAC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_EN */
#define VDAC_EN_EN_DISABLE (_VDAC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_EN */
#define VDAC_EN_EN_ENABLE (_VDAC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for VDAC_EN */
#define VDAC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
#define _VDAC_EN_DISABLING_SHIFT 1 /**< Shift value for VDAC_DISABLING */
#define _VDAC_EN_DISABLING_MASK 0x2UL /**< Bit mask for VDAC_DISABLING */
#define _VDAC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */
#define VDAC_EN_DISABLING_DEFAULT (_VDAC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_EN */
/* Bit fields for VDAC SWRST */
#define _VDAC_SWRST_RESETVALUE 0x00000000UL /**< Default value for VDAC_SWRST */
#define _VDAC_SWRST_MASK 0x00000003UL /**< Mask for VDAC_SWRST */
#define VDAC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */
#define _VDAC_SWRST_SWRST_SHIFT 0 /**< Shift value for VDAC_SWRST */
#define _VDAC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for VDAC_SWRST */
#define _VDAC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */
#define VDAC_SWRST_SWRST_DEFAULT (_VDAC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_SWRST */
#define VDAC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */
#define _VDAC_SWRST_RESETTING_SHIFT 1 /**< Shift value for VDAC_RESETTING */
#define _VDAC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for VDAC_RESETTING */
#define _VDAC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */
#define VDAC_SWRST_RESETTING_DEFAULT (_VDAC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_SWRST */
/* Bit fields for VDAC CFG */
#define _VDAC_CFG_RESETVALUE 0x20000000UL /**< Default value for VDAC_CFG */
#define _VDAC_CFG_MASK 0x7F773FBFUL /**< Mask for VDAC_CFG */
#define VDAC_CFG_DIFF (0x1UL << 0) /**< Differential Mode */
#define _VDAC_CFG_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */
#define _VDAC_CFG_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */
#define _VDAC_CFG_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
#define _VDAC_CFG_DIFF_SINGLEENDED 0x00000000UL /**< Mode SINGLEENDED for VDAC_CFG */
#define _VDAC_CFG_DIFF_DIFFERENTIAL 0x00000001UL /**< Mode DIFFERENTIAL for VDAC_CFG */
#define VDAC_CFG_DIFF_DEFAULT (_VDAC_CFG_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_DIFF_SINGLEENDED (_VDAC_CFG_DIFF_SINGLEENDED << 0) /**< Shifted mode SINGLEENDED for VDAC_CFG */
#define VDAC_CFG_DIFF_DIFFERENTIAL (_VDAC_CFG_DIFF_DIFFERENTIAL << 0) /**< Shifted mode DIFFERENTIAL for VDAC_CFG */
#define VDAC_CFG_SINEMODE (0x1UL << 1) /**< Sine Mode */
#define _VDAC_CFG_SINEMODE_SHIFT 1 /**< Shift value for VDAC_SINEMODE */
#define _VDAC_CFG_SINEMODE_MASK 0x2UL /**< Bit mask for VDAC_SINEMODE */
#define _VDAC_CFG_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
#define _VDAC_CFG_SINEMODE_DISSINEMODE 0x00000000UL /**< Mode DISSINEMODE for VDAC_CFG */
#define _VDAC_CFG_SINEMODE_ENSINEMODE 0x00000001UL /**< Mode ENSINEMODE for VDAC_CFG */
#define VDAC_CFG_SINEMODE_DEFAULT (_VDAC_CFG_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_SINEMODE_DISSINEMODE (_VDAC_CFG_SINEMODE_DISSINEMODE << 1) /**< Shifted mode DISSINEMODE for VDAC_CFG */
#define VDAC_CFG_SINEMODE_ENSINEMODE (_VDAC_CFG_SINEMODE_ENSINEMODE << 1) /**< Shifted mode ENSINEMODE for VDAC_CFG */
#define VDAC_CFG_SINERESET (0x1UL << 2) /**< Sine Wave Reset When inactive */
#define _VDAC_CFG_SINERESET_SHIFT 2 /**< Shift value for VDAC_SINERESET */
#define _VDAC_CFG_SINERESET_MASK 0x4UL /**< Bit mask for VDAC_SINERESET */
#define _VDAC_CFG_SINERESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_SINERESET_DEFAULT (_VDAC_CFG_SINERESET_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_CH0PRESCRST (0x1UL << 3) /**< Channel 0 Start Reset Prescaler */
#define _VDAC_CFG_CH0PRESCRST_SHIFT 3 /**< Shift value for VDAC_CH0PRESCRST */
#define _VDAC_CFG_CH0PRESCRST_MASK 0x8UL /**< Bit mask for VDAC_CH0PRESCRST */
#define _VDAC_CFG_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
#define _VDAC_CFG_CH0PRESCRST_NORESETPRESC 0x00000000UL /**< Mode NORESETPRESC for VDAC_CFG */
#define _VDAC_CFG_CH0PRESCRST_RESETPRESC 0x00000001UL /**< Mode RESETPRESC for VDAC_CFG */
#define VDAC_CFG_CH0PRESCRST_DEFAULT (_VDAC_CFG_CH0PRESCRST_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_CH0PRESCRST_NORESETPRESC (_VDAC_CFG_CH0PRESCRST_NORESETPRESC << 3) /**< Shifted mode NORESETPRESC for VDAC_CFG */
#define VDAC_CFG_CH0PRESCRST_RESETPRESC (_VDAC_CFG_CH0PRESCRST_RESETPRESC << 3) /**< Shifted mode RESETPRESC for VDAC_CFG */
#define _VDAC_CFG_REFRSEL_SHIFT 4 /**< Shift value for VDAC_REFRSEL */
#define _VDAC_CFG_REFRSEL_MASK 0x30UL /**< Bit mask for VDAC_REFRSEL */
#define _VDAC_CFG_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
#define _VDAC_CFG_REFRSEL_V125 0x00000000UL /**< Mode V125 for VDAC_CFG */
#define _VDAC_CFG_REFRSEL_V25 0x00000001UL /**< Mode V25 for VDAC_CFG */
#define _VDAC_CFG_REFRSEL_VDD 0x00000002UL /**< Mode VDD for VDAC_CFG */
#define _VDAC_CFG_REFRSEL_EXT 0x00000003UL /**< Mode EXT for VDAC_CFG */
#define VDAC_CFG_REFRSEL_DEFAULT (_VDAC_CFG_REFRSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_REFRSEL_V125 (_VDAC_CFG_REFRSEL_V125 << 4) /**< Shifted mode V125 for VDAC_CFG */
#define VDAC_CFG_REFRSEL_V25 (_VDAC_CFG_REFRSEL_V25 << 4) /**< Shifted mode V25 for VDAC_CFG */
#define VDAC_CFG_REFRSEL_VDD (_VDAC_CFG_REFRSEL_VDD << 4) /**< Shifted mode VDD for VDAC_CFG */
#define VDAC_CFG_REFRSEL_EXT (_VDAC_CFG_REFRSEL_EXT << 4) /**< Shifted mode EXT for VDAC_CFG */
#define _VDAC_CFG_PRESC_SHIFT 7 /**< Shift value for VDAC_PRESC */
#define _VDAC_CFG_PRESC_MASK 0x3F80UL /**< Bit mask for VDAC_PRESC */
#define _VDAC_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_PRESC_DEFAULT (_VDAC_CFG_PRESC_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_CFG */
#define _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT 16 /**< Shift value for VDAC_TIMEROVRFLOWPERIOD */
#define _VDAC_CFG_TIMEROVRFLOWPERIOD_MASK 0x70000UL /**< Bit mask for VDAC_TIMEROVRFLOWPERIOD */
#define _VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */
#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */
#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */
#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */
#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */
#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */
#define VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT (_VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 << 16) /**< Shifted mode CYCLES2 for VDAC_CFG */
#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 << 16) /**< Shifted mode CYCLES4 for VDAC_CFG */
#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 << 16) /**< Shifted mode CYCLES8 for VDAC_CFG */
#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 << 16) /**< Shifted mode CYCLES16 for VDAC_CFG */
#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 << 16) /**< Shifted mode CYCLES32 for VDAC_CFG */
#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 << 16) /**< Shifted mode CYCLES64 for VDAC_CFG */
#define _VDAC_CFG_REFRESHPERIOD_SHIFT 20 /**< Shift value for VDAC_REFRESHPERIOD */
#define _VDAC_CFG_REFRESHPERIOD_MASK 0x700000UL /**< Bit mask for VDAC_REFRESHPERIOD */
#define _VDAC_CFG_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
#define _VDAC_CFG_REFRESHPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */
#define _VDAC_CFG_REFRESHPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */
#define _VDAC_CFG_REFRESHPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */
#define _VDAC_CFG_REFRESHPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */
#define _VDAC_CFG_REFRESHPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */
#define _VDAC_CFG_REFRESHPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */
#define _VDAC_CFG_REFRESHPERIOD_CYCLES128 0x00000006UL /**< Mode CYCLES128 for VDAC_CFG */
#define _VDAC_CFG_REFRESHPERIOD_CYCLES256 0x00000007UL /**< Mode CYCLES256 for VDAC_CFG */
#define VDAC_CFG_REFRESHPERIOD_DEFAULT (_VDAC_CFG_REFRESHPERIOD_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_REFRESHPERIOD_CYCLES2 (_VDAC_CFG_REFRESHPERIOD_CYCLES2 << 20) /**< Shifted mode CYCLES2 for VDAC_CFG */
#define VDAC_CFG_REFRESHPERIOD_CYCLES4 (_VDAC_CFG_REFRESHPERIOD_CYCLES4 << 20) /**< Shifted mode CYCLES4 for VDAC_CFG */
#define VDAC_CFG_REFRESHPERIOD_CYCLES8 (_VDAC_CFG_REFRESHPERIOD_CYCLES8 << 20) /**< Shifted mode CYCLES8 for VDAC_CFG */
#define VDAC_CFG_REFRESHPERIOD_CYCLES16 (_VDAC_CFG_REFRESHPERIOD_CYCLES16 << 20) /**< Shifted mode CYCLES16 for VDAC_CFG */
#define VDAC_CFG_REFRESHPERIOD_CYCLES32 (_VDAC_CFG_REFRESHPERIOD_CYCLES32 << 20) /**< Shifted mode CYCLES32 for VDAC_CFG */
#define VDAC_CFG_REFRESHPERIOD_CYCLES64 (_VDAC_CFG_REFRESHPERIOD_CYCLES64 << 20) /**< Shifted mode CYCLES64 for VDAC_CFG */
#define VDAC_CFG_REFRESHPERIOD_CYCLES128 (_VDAC_CFG_REFRESHPERIOD_CYCLES128 << 20) /**< Shifted mode CYCLES128 for VDAC_CFG */
#define VDAC_CFG_REFRESHPERIOD_CYCLES256 (_VDAC_CFG_REFRESHPERIOD_CYCLES256 << 20) /**< Shifted mode CYCLES256 for VDAC_CFG */
#define VDAC_CFG_BIASKEEPWARM (0x1UL << 24) /**< Bias Keepwarm Mode Enable */
#define _VDAC_CFG_BIASKEEPWARM_SHIFT 24 /**< Shift value for VDAC_BIASKEEPWARM */
#define _VDAC_CFG_BIASKEEPWARM_MASK 0x1000000UL /**< Bit mask for VDAC_BIASKEEPWARM */
#define _VDAC_CFG_BIASKEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_BIASKEEPWARM_DEFAULT (_VDAC_CFG_BIASKEEPWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_DMAWU (0x1UL << 25) /**< VDAC DMA Wakeup */
#define _VDAC_CFG_DMAWU_SHIFT 25 /**< Shift value for VDAC_DMAWU */
#define _VDAC_CFG_DMAWU_MASK 0x2000000UL /**< Bit mask for VDAC_DMAWU */
#define _VDAC_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_DMAWU_DEFAULT (_VDAC_CFG_DMAWU_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_ONDEMANDCLK (0x1UL << 26) /**< Always allow clk_dac */
#define _VDAC_CFG_ONDEMANDCLK_SHIFT 26 /**< Shift value for VDAC_ONDEMANDCLK */
#define _VDAC_CFG_ONDEMANDCLK_MASK 0x4000000UL /**< Bit mask for VDAC_ONDEMANDCLK */
#define _VDAC_CFG_ONDEMANDCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_ONDEMANDCLK_DEFAULT (_VDAC_CFG_ONDEMANDCLK_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_DBGHALT (0x1UL << 27) /**< Debug Halt */
#define _VDAC_CFG_DBGHALT_SHIFT 27 /**< Shift value for VDAC_DBGHALT */
#define _VDAC_CFG_DBGHALT_MASK 0x8000000UL /**< Bit mask for VDAC_DBGHALT */
#define _VDAC_CFG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
#define _VDAC_CFG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CFG */
#define _VDAC_CFG_DBGHALT_HALT 0x00000001UL /**< Mode HALT for VDAC_CFG */
#define VDAC_CFG_DBGHALT_DEFAULT (_VDAC_CFG_DBGHALT_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_DBGHALT_NORMAL (_VDAC_CFG_DBGHALT_NORMAL << 27) /**< Shifted mode NORMAL for VDAC_CFG */
#define VDAC_CFG_DBGHALT_HALT (_VDAC_CFG_DBGHALT_HALT << 27) /**< Shifted mode HALT for VDAC_CFG */
#define _VDAC_CFG_WARMUPTIME_SHIFT 28 /**< Shift value for VDAC_WARMUPTIME */
#define _VDAC_CFG_WARMUPTIME_MASK 0x70000000UL /**< Bit mask for VDAC_WARMUPTIME */
#define _VDAC_CFG_WARMUPTIME_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_CFG */
#define VDAC_CFG_WARMUPTIME_DEFAULT (_VDAC_CFG_WARMUPTIME_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CFG */
/* Bit fields for VDAC STATUS */
#define _VDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for VDAC_STATUS */
#define _VDAC_STATUS_MASK 0xFCDBF333UL /**< Mask for VDAC_STATUS */
#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */
#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */
#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */
#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */
#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */
#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */
#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warmed Status */
#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */
#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */
#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warmed Status */
#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */
#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */
#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH0FIFOFULL (0x1UL << 8) /**< Channel 0 FIFO Full Status */
#define _VDAC_STATUS_CH0FIFOFULL_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFULL */
#define _VDAC_STATUS_CH0FIFOFULL_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFULL */
#define _VDAC_STATUS_CH0FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH0FIFOFULL_DEFAULT (_VDAC_STATUS_CH0FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH1FIFOFULL (0x1UL << 9) /**< Channel 1 FIFO Full Status */
#define _VDAC_STATUS_CH1FIFOFULL_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFULL */
#define _VDAC_STATUS_CH1FIFOFULL_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFULL */
#define _VDAC_STATUS_CH1FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH1FIFOFULL_DEFAULT (_VDAC_STATUS_CH1FIFOFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define _VDAC_STATUS_CH0FIFOCNT_SHIFT 12 /**< Shift value for VDAC_CH0FIFOCNT */
#define _VDAC_STATUS_CH0FIFOCNT_MASK 0x7000UL /**< Bit mask for VDAC_CH0FIFOCNT */
#define _VDAC_STATUS_CH0FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH0FIFOCNT_DEFAULT (_VDAC_STATUS_CH0FIFOCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define _VDAC_STATUS_CH1FIFOCNT_SHIFT 15 /**< Shift value for VDAC_CH1FIFOCNT */
#define _VDAC_STATUS_CH1FIFOCNT_MASK 0x38000UL /**< Bit mask for VDAC_CH1FIFOCNT */
#define _VDAC_STATUS_CH1FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH1FIFOCNT_DEFAULT (_VDAC_STATUS_CH1FIFOCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH0CURRENTSTATE (0x1UL << 19) /**< Channel 0 Current Status */
#define _VDAC_STATUS_CH0CURRENTSTATE_SHIFT 19 /**< Shift value for VDAC_CH0CURRENTSTATE */
#define _VDAC_STATUS_CH0CURRENTSTATE_MASK 0x80000UL /**< Bit mask for VDAC_CH0CURRENTSTATE */
#define _VDAC_STATUS_CH0CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH0CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH0CURRENTSTATE_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH1CURRENTSTATE (0x1UL << 20) /**< Channel 1 Current Status */
#define _VDAC_STATUS_CH1CURRENTSTATE_SHIFT 20 /**< Shift value for VDAC_CH1CURRENTSTATE */
#define _VDAC_STATUS_CH1CURRENTSTATE_MASK 0x100000UL /**< Bit mask for VDAC_CH1CURRENTSTATE */
#define _VDAC_STATUS_CH1CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH1CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH1CURRENTSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH0FIFOEMPTY (0x1UL << 22) /**< Channel 0 FIFO Empty Status */
#define _VDAC_STATUS_CH0FIFOEMPTY_SHIFT 22 /**< Shift value for VDAC_CH0FIFOEMPTY */
#define _VDAC_STATUS_CH0FIFOEMPTY_MASK 0x400000UL /**< Bit mask for VDAC_CH0FIFOEMPTY */
#define _VDAC_STATUS_CH0FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH0FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH0FIFOEMPTY_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH1FIFOEMPTY (0x1UL << 23) /**< Channel 1 FIFO Empty Status */
#define _VDAC_STATUS_CH1FIFOEMPTY_SHIFT 23 /**< Shift value for VDAC_CH1FIFOEMPTY */
#define _VDAC_STATUS_CH1FIFOEMPTY_MASK 0x800000UL /**< Bit mask for VDAC_CH1FIFOEMPTY */
#define _VDAC_STATUS_CH1FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH1FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH1FIFOEMPTY_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH0FIFOFLBUSY (0x1UL << 26) /**< CH0 FIFO Flush Sync Busy */
#define _VDAC_STATUS_CH0FIFOFLBUSY_SHIFT 26 /**< Shift value for VDAC_CH0FIFOFLBUSY */
#define _VDAC_STATUS_CH0FIFOFLBUSY_MASK 0x4000000UL /**< Bit mask for VDAC_CH0FIFOFLBUSY */
#define _VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH1FIFOFLBUSY (0x1UL << 27) /**< CH1 FIFO Flush Sync Busy */
#define _VDAC_STATUS_CH1FIFOFLBUSY_SHIFT 27 /**< Shift value for VDAC_CH1FIFOFLBUSY */
#define _VDAC_STATUS_CH1FIFOFLBUSY_MASK 0x8000000UL /**< Bit mask for VDAC_CH1FIFOFLBUSY */
#define _VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_ABUSINPUTCONFLICT (0x1UL << 28) /**< ABUS Input Conflict Status */
#define _VDAC_STATUS_ABUSINPUTCONFLICT_SHIFT 28 /**< Shift value for VDAC_ABUSINPUTCONFLICT */
#define _VDAC_STATUS_ABUSINPUTCONFLICT_MASK 0x10000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */
#define _VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT (_VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_SINEACTIVE (0x1UL << 29) /**< Sine Wave Output Status on Channel */
#define _VDAC_STATUS_SINEACTIVE_SHIFT 29 /**< Shift value for VDAC_SINEACTIVE */
#define _VDAC_STATUS_SINEACTIVE_MASK 0x20000000UL /**< Bit mask for VDAC_SINEACTIVE */
#define _VDAC_STATUS_SINEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_SINEACTIVE_DEFAULT (_VDAC_STATUS_SINEACTIVE_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_ABUSALLOCERR (0x1UL << 30) /**< ABUS Allocation Error Status */
#define _VDAC_STATUS_ABUSALLOCERR_SHIFT 30 /**< Shift value for VDAC_ABUSALLOCERR */
#define _VDAC_STATUS_ABUSALLOCERR_MASK 0x40000000UL /**< Bit mask for VDAC_ABUSALLOCERR */
#define _VDAC_STATUS_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_ABUSALLOCERR_DEFAULT (_VDAC_STATUS_ABUSALLOCERR_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy Combined */
#define _VDAC_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for VDAC_SYNCBUSY */
#define _VDAC_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for VDAC_SYNCBUSY */
#define _VDAC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
#define VDAC_STATUS_SYNCBUSY_DEFAULT (_VDAC_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_STATUS */
/* Bit fields for VDAC CH0CFG */
#define _VDAC_CH0CFG_RESETVALUE 0x00000010UL /**< Default value for VDAC_CH0CFG */
#define _VDAC_CH0CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH0CFG */
#define VDAC_CH0CFG_CONVMODE (0x1UL << 0) /**< Channel 0 Conversion Mode */
#define _VDAC_CH0CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */
#define _VDAC_CH0CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */
#define _VDAC_CH0CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */
#define _VDAC_CH0CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CFG */
#define _VDAC_CH0CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CFG */
#define VDAC_CH0CFG_CONVMODE_DEFAULT (_VDAC_CH0CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CFG */
#define VDAC_CH0CFG_CONVMODE_CONTINUOUS (_VDAC_CH0CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CFG */
#define VDAC_CH0CFG_CONVMODE_SAMPLEOFF (_VDAC_CH0CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CFG */
#define VDAC_CH0CFG_POWERMODE (0x1UL << 2) /**< Channel 0 Power Mode */
#define _VDAC_CH0CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */
#define _VDAC_CH0CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */
#define _VDAC_CH0CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */
#define _VDAC_CH0CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH0CFG */
#define _VDAC_CH0CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH0CFG */
#define VDAC_CH0CFG_POWERMODE_DEFAULT (_VDAC_CH0CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH0CFG */
#define VDAC_CH0CFG_POWERMODE_HIGHPOWER (_VDAC_CH0CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH0CFG */
#define VDAC_CH0CFG_POWERMODE_LOWPOWER (_VDAC_CH0CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH0CFG */
#define _VDAC_CH0CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */
#define _VDAC_CH0CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */
#define _VDAC_CH0CFG_TRIGMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_CH0CFG */
#define _VDAC_CH0CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */
#define _VDAC_CH0CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH0CFG */
#define _VDAC_CH0CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */
#define _VDAC_CH0CFG_TRIGMODE_LESENSE 0x00000003UL /**< Mode LESENSE for VDAC_CH0CFG */
#define _VDAC_CH0CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH0CFG */
#define _VDAC_CH0CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH0CFG */
#define VDAC_CH0CFG_TRIGMODE_DEFAULT (_VDAC_CH0CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CFG */
#define VDAC_CH0CFG_TRIGMODE_NONE (_VDAC_CH0CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH0CFG */
#define VDAC_CH0CFG_TRIGMODE_SW (_VDAC_CH0CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CFG */
#define VDAC_CH0CFG_TRIGMODE_SYNCPRS (_VDAC_CH0CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */
#define VDAC_CH0CFG_TRIGMODE_LESENSE (_VDAC_CH0CFG_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH0CFG */
#define VDAC_CH0CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH0CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH0CFG */
#define VDAC_CH0CFG_TRIGMODE_ASYNCPRS (_VDAC_CH0CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */
#define _VDAC_CH0CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */
#define _VDAC_CH0CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */
#define _VDAC_CH0CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */
#define _VDAC_CH0CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */
#define _VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH0CFG */
#define _VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */
#define _VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH0CFG */
#define VDAC_CH0CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH0CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CFG */
#define VDAC_CH0CFG_REFRESHSOURCE_NONE (_VDAC_CH0CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH0CFG */
#define VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH0CFG */
#define VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */
#define VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */
#define _VDAC_CH0CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */
#define _VDAC_CH0CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */
#define _VDAC_CH0CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */
#define VDAC_CH0CFG_FIFODVL_DEFAULT (_VDAC_CH0CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH0CFG */
#define VDAC_CH0CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 0 High Cap Load Mode Enable */
#define _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */
#define _VDAC_CH0CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */
#define _VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */
#define VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH0CFG */
#define VDAC_CH0CFG_KEEPWARM (0x1UL << 16) /**< Channel 0 Keepwarm Mode Enable */
#define _VDAC_CH0CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */
#define _VDAC_CH0CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */
#define _VDAC_CH0CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */
#define VDAC_CH0CFG_KEEPWARM_DEFAULT (_VDAC_CH0CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH0CFG */
/* Bit fields for VDAC CH1CFG */
#define _VDAC_CH1CFG_RESETVALUE 0x00000010UL /**< Default value for VDAC_CH1CFG */
#define _VDAC_CH1CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH1CFG */
#define VDAC_CH1CFG_CONVMODE (0x1UL << 0) /**< Channel 1 Conversion Mode */
#define _VDAC_CH1CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */
#define _VDAC_CH1CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */
#define _VDAC_CH1CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */
#define _VDAC_CH1CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CFG */
#define _VDAC_CH1CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CFG */
#define VDAC_CH1CFG_CONVMODE_DEFAULT (_VDAC_CH1CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CFG */
#define VDAC_CH1CFG_CONVMODE_CONTINUOUS (_VDAC_CH1CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CFG */
#define VDAC_CH1CFG_CONVMODE_SAMPLEOFF (_VDAC_CH1CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CFG */
#define VDAC_CH1CFG_POWERMODE (0x1UL << 2) /**< Channel 1 Power Mode */
#define _VDAC_CH1CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */
#define _VDAC_CH1CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */
#define _VDAC_CH1CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */
#define _VDAC_CH1CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH1CFG */
#define _VDAC_CH1CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH1CFG */
#define VDAC_CH1CFG_POWERMODE_DEFAULT (_VDAC_CH1CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH1CFG */
#define VDAC_CH1CFG_POWERMODE_HIGHPOWER (_VDAC_CH1CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH1CFG */
#define VDAC_CH1CFG_POWERMODE_LOWPOWER (_VDAC_CH1CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH1CFG */
#define _VDAC_CH1CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */
#define _VDAC_CH1CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */
#define _VDAC_CH1CFG_TRIGMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_CH1CFG */
#define _VDAC_CH1CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */
#define _VDAC_CH1CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH1CFG */
#define _VDAC_CH1CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */
#define _VDAC_CH1CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH1CFG */
#define _VDAC_CH1CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH1CFG */
#define VDAC_CH1CFG_TRIGMODE_DEFAULT (_VDAC_CH1CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CFG */
#define VDAC_CH1CFG_TRIGMODE_NONE (_VDAC_CH1CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH1CFG */
#define VDAC_CH1CFG_TRIGMODE_SW (_VDAC_CH1CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CFG */
#define VDAC_CH1CFG_TRIGMODE_SYNCPRS (_VDAC_CH1CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */
#define VDAC_CH1CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH1CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH1CFG */
#define VDAC_CH1CFG_TRIGMODE_ASYNCPRS (_VDAC_CH1CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */
#define _VDAC_CH1CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */
#define _VDAC_CH1CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */
#define _VDAC_CH1CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */
#define _VDAC_CH1CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */
#define _VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH1CFG */
#define _VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */
#define _VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH1CFG */
#define VDAC_CH1CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH1CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CFG */
#define VDAC_CH1CFG_REFRESHSOURCE_NONE (_VDAC_CH1CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH1CFG */
#define VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH1CFG */
#define VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */
#define VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */
#define _VDAC_CH1CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */
#define _VDAC_CH1CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */
#define _VDAC_CH1CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */
#define VDAC_CH1CFG_FIFODVL_DEFAULT (_VDAC_CH1CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH1CFG */
#define VDAC_CH1CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 1 High Cap Load Mode Enable */
#define _VDAC_CH1CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */
#define _VDAC_CH1CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */
#define _VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */
#define VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH1CFG */
#define VDAC_CH1CFG_KEEPWARM (0x1UL << 16) /**< Channel 1 Keepwarm Mode Enable */
#define _VDAC_CH1CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */
#define _VDAC_CH1CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */
#define _VDAC_CH1CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */
#define VDAC_CH1CFG_KEEPWARM_DEFAULT (_VDAC_CH1CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH1CFG */
/* Bit fields for VDAC CMD */
#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */
#define _VDAC_CMD_MASK 0x00000F33UL /**< Mask for VDAC_CMD */
#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */
#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */
#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */
#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */
#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */
#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */
#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_CH1EN (0x1UL << 4) /**< DAC Channel 1 Enable */
#define _VDAC_CMD_CH1EN_SHIFT 4 /**< Shift value for VDAC_CH1EN */
#define _VDAC_CMD_CH1EN_MASK 0x10UL /**< Bit mask for VDAC_CH1EN */
#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_CH1DIS (0x1UL << 5) /**< DAC Channel 1 Disable */
#define _VDAC_CMD_CH1DIS_SHIFT 5 /**< Shift value for VDAC_CH1DIS */
#define _VDAC_CMD_CH1DIS_MASK 0x20UL /**< Bit mask for VDAC_CH1DIS */
#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_CH0FIFOFLUSH (0x1UL << 8) /**< CH0 WFIFO Flush */
#define _VDAC_CMD_CH0FIFOFLUSH_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFLUSH */
#define _VDAC_CMD_CH0FIFOFLUSH_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFLUSH */
#define _VDAC_CMD_CH0FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_CH0FIFOFLUSH_DEFAULT (_VDAC_CMD_CH0FIFOFLUSH_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_CH1FIFOFLUSH (0x1UL << 9) /**< CH1 WFIFO Flush */
#define _VDAC_CMD_CH1FIFOFLUSH_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFLUSH */
#define _VDAC_CMD_CH1FIFOFLUSH_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFLUSH */
#define _VDAC_CMD_CH1FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_CH1FIFOFLUSH_DEFAULT (_VDAC_CMD_CH1FIFOFLUSH_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_SINEMODESTART (0x1UL << 10) /**< Start Sine Wave Generation */
#define _VDAC_CMD_SINEMODESTART_SHIFT 10 /**< Shift value for VDAC_SINEMODESTART */
#define _VDAC_CMD_SINEMODESTART_MASK 0x400UL /**< Bit mask for VDAC_SINEMODESTART */
#define _VDAC_CMD_SINEMODESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_SINEMODESTART_DEFAULT (_VDAC_CMD_SINEMODESTART_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_SINEMODESTOP (0x1UL << 11) /**< Stop Sine Wave Generation */
#define _VDAC_CMD_SINEMODESTOP_SHIFT 11 /**< Shift value for VDAC_SINEMODESTOP */
#define _VDAC_CMD_SINEMODESTOP_MASK 0x800UL /**< Bit mask for VDAC_SINEMODESTOP */
#define _VDAC_CMD_SINEMODESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
#define VDAC_CMD_SINEMODESTOP_DEFAULT (_VDAC_CMD_SINEMODESTOP_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CMD */
/* Bit fields for VDAC IF */
#define _VDAC_IF_RESETVALUE 0x00000000UL /**< Default value for VDAC_IF */
#define _VDAC_IF_MASK 0x04340333UL /**< Mask for VDAC_IF */
#define VDAC_IF_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */
#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */
#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */
#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */
#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */
#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */
#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */
#define _VDAC_IF_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */
#define _VDAC_IF_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */
#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */
#define _VDAC_IF_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */
#define _VDAC_IF_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */
#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */
#define _VDAC_IF_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */
#define _VDAC_IF_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */
#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */
#define _VDAC_IF_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */
#define _VDAC_IF_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */
#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IF */
#define VDAC_IF_ABUSALLOCERR (0x1UL << 18) /**< ABUS Port Allocation Error Flag */
#define _VDAC_IF_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */
#define _VDAC_IF_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */
#define _VDAC_IF_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
#define VDAC_IF_ABUSALLOCERR_DEFAULT (_VDAC_IF_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */
#define _VDAC_IF_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */
#define _VDAC_IF_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */
#define _VDAC_IF_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH0DVL_DEFAULT (_VDAC_IF_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */
#define _VDAC_IF_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */
#define _VDAC_IF_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */
#define _VDAC_IF_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
#define VDAC_IF_CH1DVL_DEFAULT (_VDAC_IF_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */
#define VDAC_IF_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Error Flag */
#define _VDAC_IF_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */
#define _VDAC_IF_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */
#define _VDAC_IF_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
#define VDAC_IF_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IF_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IF */
/* Bit fields for VDAC IEN */
#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */
#define _VDAC_IEN_MASK 0x04340333UL /**< Mask for VDAC_IEN */
#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */
#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */
#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */
#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */
#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */
#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */
#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */
#define _VDAC_IEN_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */
#define _VDAC_IEN_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */
#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */
#define _VDAC_IEN_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */
#define _VDAC_IEN_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */
#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */
#define _VDAC_IEN_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */
#define _VDAC_IEN_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */
#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */
#define _VDAC_IEN_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */
#define _VDAC_IEN_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */
#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_ABUSALLOCERR (0x1UL << 18) /**< ABUS Allocation Error Interrupt Flag */
#define _VDAC_IEN_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */
#define _VDAC_IEN_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */
#define _VDAC_IEN_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_ABUSALLOCERR_DEFAULT (_VDAC_IEN_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */
#define _VDAC_IEN_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */
#define _VDAC_IEN_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */
#define _VDAC_IEN_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH0DVL_DEFAULT (_VDAC_IEN_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */
#define _VDAC_IEN_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */
#define _VDAC_IEN_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */
#define _VDAC_IEN_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_CH1DVL_DEFAULT (_VDAC_IEN_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Interrupt Flag */
#define _VDAC_IEN_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */
#define _VDAC_IEN_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */
#define _VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
#define VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IEN */
/* Bit fields for VDAC CH0F */
#define _VDAC_CH0F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0F */
#define _VDAC_CH0F_MASK 0x00000FFFUL /**< Mask for VDAC_CH0F */
#define _VDAC_CH0F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */
#define _VDAC_CH0F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */
#define _VDAC_CH0F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0F */
#define VDAC_CH0F_DATA_DEFAULT (_VDAC_CH0F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0F */
/* Bit fields for VDAC CH1F */
#define _VDAC_CH1F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1F */
#define _VDAC_CH1F_MASK 0x00000FFFUL /**< Mask for VDAC_CH1F */
#define _VDAC_CH1F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */
#define _VDAC_CH1F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */
#define _VDAC_CH1F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1F */
#define VDAC_CH1F_DATA_DEFAULT (_VDAC_CH1F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1F */
/* Bit fields for VDAC OUTCTRL */
#define _VDAC_OUTCTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_MASK 0x7FDFF333UL /**< Mask for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_MAINOUTENCH0 (0x1UL << 0) /**< CH0 Main Output Enable */
#define _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT 0 /**< Shift value for VDAC_MAINOUTENCH0 */
#define _VDAC_OUTCTRL_MAINOUTENCH0_MASK 0x1UL /**< Bit mask for VDAC_MAINOUTENCH0 */
#define _VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_MAINOUTENCH1 (0x1UL << 1) /**< CH1 Main Output Enable */
#define _VDAC_OUTCTRL_MAINOUTENCH1_SHIFT 1 /**< Shift value for VDAC_MAINOUTENCH1 */
#define _VDAC_OUTCTRL_MAINOUTENCH1_MASK 0x2UL /**< Bit mask for VDAC_MAINOUTENCH1 */
#define _VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_AUXOUTENCH0 (0x1UL << 4) /**< CH0 Alternative Output Enable */
#define _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT 4 /**< Shift value for VDAC_AUXOUTENCH0 */
#define _VDAC_OUTCTRL_AUXOUTENCH0_MASK 0x10UL /**< Bit mask for VDAC_AUXOUTENCH0 */
#define _VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_AUXOUTENCH1 (0x1UL << 5) /**< CH1 Alternative Output Enable */
#define _VDAC_OUTCTRL_AUXOUTENCH1_SHIFT 5 /**< Shift value for VDAC_AUXOUTENCH1 */
#define _VDAC_OUTCTRL_AUXOUTENCH1_MASK 0x20UL /**< Bit mask for VDAC_AUXOUTENCH1 */
#define _VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_SHORTCH0 (0x1UL << 8) /**< CH1 Main and Alternative Output Short */
#define _VDAC_OUTCTRL_SHORTCH0_SHIFT 8 /**< Shift value for VDAC_SHORTCH0 */
#define _VDAC_OUTCTRL_SHORTCH0_MASK 0x100UL /**< Bit mask for VDAC_SHORTCH0 */
#define _VDAC_OUTCTRL_SHORTCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_SHORTCH0_DEFAULT (_VDAC_OUTCTRL_SHORTCH0_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_SHORTCH1 (0x1UL << 9) /**< CH0 Main and Alternative Output Short */
#define _VDAC_OUTCTRL_SHORTCH1_SHIFT 9 /**< Shift value for VDAC_SHORTCH1 */
#define _VDAC_OUTCTRL_SHORTCH1_MASK 0x200UL /**< Bit mask for VDAC_SHORTCH1 */
#define _VDAC_OUTCTRL_SHORTCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_SHORTCH1_DEFAULT (_VDAC_OUTCTRL_SHORTCH1_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT 12 /**< Shift value for VDAC_ABUSPORTSELCH0 */
#define _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK 0x7000UL /**< Bit mask for VDAC_ABUSPORTSELCH0 */
#define _VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_ABUSPORTSELCH0_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_ABUSPORTSELCH0_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH0_NONE << 12) /**< Shifted mode NONE for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA << 12) /**< Shifted mode PORTA for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB << 12) /**< Shifted mode PORTB for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC << 12) /**< Shifted mode PORTC for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD << 12) /**< Shifted mode PORTD for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT 15 /**< Shift value for VDAC_ABUSPINSELCH0 */
#define _VDAC_OUTCTRL_ABUSPINSELCH0_MASK 0x1F8000UL /**< Bit mask for VDAC_ABUSPINSELCH0 */
#define _VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_ABUSPORTSELCH1_SHIFT 22 /**< Shift value for VDAC_ABUSPORTSELCH1 */
#define _VDAC_OUTCTRL_ABUSPORTSELCH1_MASK 0x1C00000UL /**< Bit mask for VDAC_ABUSPORTSELCH1 */
#define _VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_ABUSPORTSELCH1_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_ABUSPORTSELCH1_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH1_NONE << 22) /**< Shifted mode NONE for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA << 22) /**< Shifted mode PORTA for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB << 22) /**< Shifted mode PORTB for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC << 22) /**< Shifted mode PORTC for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD << 22) /**< Shifted mode PORTD for VDAC_OUTCTRL */
#define _VDAC_OUTCTRL_ABUSPINSELCH1_SHIFT 25 /**< Shift value for VDAC_ABUSPINSELCH1 */
#define _VDAC_OUTCTRL_ABUSPINSELCH1_MASK 0x7E000000UL /**< Bit mask for VDAC_ABUSPINSELCH1 */
#define _VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
#define VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
/* Bit fields for VDAC OUTTIMERCFG */
#define _VDAC_OUTTIMERCFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTTIMERCFG */
#define _VDAC_OUTTIMERCFG_MASK 0x01FF83FFUL /**< Mask for VDAC_OUTTIMERCFG */
#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT 0 /**< Shift value for VDAC_CH0OUTHOLDTIME */
#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK 0x3FFUL /**< Bit mask for VDAC_CH0OUTHOLDTIME */
#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */
#define VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */
#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_SHIFT 15 /**< Shift value for VDAC_CH1OUTHOLDTIME */
#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK 0x1FF8000UL /**< Bit mask for VDAC_CH1OUTHOLDTIME */
#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */
#define VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */
/** @} End of group EFR32ZG23_VDAC_BitFields */
/** @} End of group EFR32ZG23_VDAC */
/** @} End of group Parts */
#endif /* EFR32ZG23_VDAC_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief EFR32ZG23 WDOG register and bit field definitions
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EFR32ZG23_WDOG_H
#define EFR32ZG23_WDOG_H
#define WDOG_HAS_SET_CLEAR
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFR32ZG23_WDOG WDOG
* @{
* @brief EFR32ZG23 WDOG Register Declaration.
*****************************************************************************/
/** WDOG Register Declaration. */
typedef struct {
__IM uint32_t IPVERSION; /**< IP Version Register */
__IOM uint32_t EN; /**< Enable Register */
__IOM uint32_t CFG; /**< Configuration Register */
__IOM uint32_t CMD; /**< Command Register */
uint32_t RESERVED0[1U]; /**< Reserved for future use */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IOM uint32_t LOCK; /**< Lock Register */
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
uint32_t RESERVED1[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_SET; /**< IP Version Register */
__IOM uint32_t EN_SET; /**< Enable Register */
__IOM uint32_t CFG_SET; /**< Configuration Register */
__IOM uint32_t CMD_SET; /**< Command Register */
uint32_t RESERVED2[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_SET; /**< Status Register */
__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
__IOM uint32_t LOCK_SET; /**< Lock Register */
__IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */
uint32_t RESERVED3[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_CLR; /**< IP Version Register */
__IOM uint32_t EN_CLR; /**< Enable Register */
__IOM uint32_t CFG_CLR; /**< Configuration Register */
__IOM uint32_t CMD_CLR; /**< Command Register */
uint32_t RESERVED4[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_CLR; /**< Status Register */
__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
__IOM uint32_t LOCK_CLR; /**< Lock Register */
__IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */
uint32_t RESERVED5[1014U]; /**< Reserved for future use */
__IM uint32_t IPVERSION_TGL; /**< IP Version Register */
__IOM uint32_t EN_TGL; /**< Enable Register */
__IOM uint32_t CFG_TGL; /**< Configuration Register */
__IOM uint32_t CMD_TGL; /**< Command Register */
uint32_t RESERVED6[1U]; /**< Reserved for future use */
__IM uint32_t STATUS_TGL; /**< Status Register */
__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
__IOM uint32_t LOCK_TGL; /**< Lock Register */
__IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */
} WDOG_TypeDef;
/** @} End of group EFR32ZG23_WDOG */
/**************************************************************************//**
* @addtogroup EFR32ZG23_WDOG
* @{
* @defgroup EFR32ZG23_WDOG_BitFields WDOG Bit Fields
* @{
*****************************************************************************/
/* Bit fields for WDOG IPVERSION */
#define _WDOG_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for WDOG_IPVERSION */
#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */
#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */
#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */
#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for WDOG_IPVERSION */
#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */
/* Bit fields for WDOG EN */
#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */
#define _WDOG_EN_MASK 0x00000003UL /**< Mask for WDOG_EN */
#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */
#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */
#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */
#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */
#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */
#define WDOG_EN_DISABLING (0x1UL << 1) /**< Disabling busy status */
#define _WDOG_EN_DISABLING_SHIFT 1 /**< Shift value for WDOG_DISABLING */
#define _WDOG_EN_DISABLING_MASK 0x2UL /**< Bit mask for WDOG_DISABLING */
#define _WDOG_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */
#define WDOG_EN_DISABLING_DEFAULT (_WDOG_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_EN */
/* Bit fields for WDOG CFG */
#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */
#define _WDOG_CFG_MASK 0x730F073FUL /**< Mask for WDOG_CFG */
#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */
#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */
#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */
#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */
#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */
#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */
#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */
#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */
#define WDOG_CFG_EM1RUN (0x1UL << 1) /**< EM1 Run */
#define _WDOG_CFG_EM1RUN_SHIFT 1 /**< Shift value for WDOG_EM1RUN */
#define _WDOG_CFG_EM1RUN_MASK 0x2UL /**< Bit mask for WDOG_EM1RUN */
#define _WDOG_CFG_EM1RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
#define _WDOG_CFG_EM1RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */
#define _WDOG_CFG_EM1RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */
#define WDOG_CFG_EM1RUN_DEFAULT (_WDOG_CFG_EM1RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */
#define WDOG_CFG_EM1RUN_DISABLE (_WDOG_CFG_EM1RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */
#define WDOG_CFG_EM1RUN_ENABLE (_WDOG_CFG_EM1RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */
#define WDOG_CFG_EM2RUN (0x1UL << 2) /**< EM2 Run */
#define _WDOG_CFG_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */
#define _WDOG_CFG_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */
#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */
#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */
#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */
#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */
#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */
#define WDOG_CFG_EM3RUN (0x1UL << 3) /**< EM3 Run */
#define _WDOG_CFG_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */
#define _WDOG_CFG_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */
#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */
#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */
#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */
#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */
#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */
#define WDOG_CFG_EM4BLOCK (0x1UL << 4) /**< EM4 Block */
#define _WDOG_CFG_EM4BLOCK_SHIFT 4 /**< Shift value for WDOG_EM4BLOCK */
#define _WDOG_CFG_EM4BLOCK_MASK 0x10UL /**< Bit mask for WDOG_EM4BLOCK */
#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */
#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */
#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */
#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */
#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */
#define WDOG_CFG_DEBUGRUN (0x1UL << 5) /**< Debug Mode Run */
#define _WDOG_CFG_DEBUGRUN_SHIFT 5 /**< Shift value for WDOG_DEBUGRUN */
#define _WDOG_CFG_DEBUGRUN_MASK 0x20UL /**< Bit mask for WDOG_DEBUGRUN */
#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */
#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */
#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CFG */
#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 5) /**< Shifted mode DISABLE for WDOG_CFG */
#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 5) /**< Shifted mode ENABLE for WDOG_CFG */
#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */
#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */
#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */
#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */
#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */
#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */
#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */
#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */
#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */
#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */
#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */
#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */
#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */
#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */
#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */
#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */
#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */
#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */
#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */
#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */
#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */
#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */
#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */
#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */
#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */
#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */
#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */
#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */
#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */
#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */
#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */
#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */
#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */
#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */
#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */
#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */
#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */
#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */
#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */
#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */
#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */
#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */
#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */
#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */
#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */
#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */
#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */
#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */
#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */
#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */
#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */
/* Bit fields for WDOG CMD */
#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */
#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */
#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */
#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */
#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */
#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */
#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */
#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */
#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */
#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */
#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */
/* Bit fields for WDOG STATUS */
#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */
#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */
#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */
#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */
#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */
#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */
#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */
#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */
#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */
#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */
#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */
/* Bit fields for WDOG IF */
#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */
#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */
#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */
#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */
#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */
#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */
#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */
#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */
#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */
#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */
#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */
#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */
/* Bit fields for WDOG IEN */
#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */
#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */
#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */
#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */
#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */
#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */
#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */
#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */
/* Bit fields for WDOG LOCK */
#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */
#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */
#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */
#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */
#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */
#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */
#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */
#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */
#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */
#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */
/* Bit fields for WDOG SYNCBUSY */
#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */
#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */
#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */
#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */
#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
/** @} End of group EFR32ZG23_WDOG_BitFields */
/** @} End of group EFR32ZG23_WDOG */
/** @} End of group Parts */
#endif /* EFR32ZG23_WDOG_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories
* microcontroller devices
*
* This is a convenience header file for defining the part number on the
* build command line, instead of specifying the part specific header file.
*
* @verbatim
* Example: Add "-DEFM32G890F128" to your build options, to define part
* Add "#include "em_device.h" to your source files
*
* @endverbatim
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EM_DEVICE_H
#define EM_DEVICE_H
#if defined(EFR32ZG23A010F512GM40)
#include "efr32zg23a010f512gm40.h"
#elif defined(EFR32ZG23A010F512GM48)
#include "efr32zg23a010f512gm48.h"
#elif defined(EFR32ZG23A020F512GM40)
#include "efr32zg23a020f512gm40.h"
#elif defined(EFR32ZG23A020F512GM48)
#include "efr32zg23a020f512gm48.h"
#elif defined(EFR32ZG23B010F512IM40)
#include "efr32zg23b010f512im40.h"
#elif defined(EFR32ZG23B010F512IM48)
#include "efr32zg23b010f512im48.h"
#elif defined(EFR32ZG23B011F512IM40)
#include "efr32zg23b011f512im40.h"
#elif defined(EFR32ZG23B020F512IM40)
#include "efr32zg23b020f512im40.h"
#elif defined(EFR32ZG23B020F512IM48)
#include "efr32zg23b020f512im48.h"
#elif defined(EFR32ZG23B021F512IM40)
#include "efr32zg23b021f512im40.h"
#else
#error "em_device.h: PART NUMBER undefined"
#endif
#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) && defined(SL_TRUSTZONE_NONSECURE)
#error "Can't define SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT and SL_TRUSTZONE_NONSECURE MACRO at the same time."
#endif
#if defined(SL_TRUSTZONE_SECURE) && defined(SL_TRUSTZONE_NONSECURE)
#error "Can't define SL_TRUSTZONE_SECURE and SL_TRUSTZONE_NONSECURE MACRO at the same time."
#endif
#endif /* EM_DEVICE_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file
* @brief CMSIS system header file for EFR32ZG23
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#ifndef SYSTEM_EFR32ZG23_H
#define SYSTEM_EFR32ZG23_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/***************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup EFR32ZG23 EFR32ZG23
* @{
******************************************************************************/
/*******************************************************************************
****************************** TYPEDEFS ***********************************
******************************************************************************/
/* Interrupt vectortable entry */
typedef union {
void (*VECTOR_TABLE_Type)(void);
void *topOfStack;
} tVectorEntry;
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
#if !defined(SYSTEM_NO_STATIC_MEMORY)
extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
#endif
/*Re-direction of IRQn.*/
#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
#if defined (SL_TRUSTZONE_SECURE)
#define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn
#else
#define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn
#endif /* SL_TRUSTZONE_SECURE */
#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG */
/*Re-direction of IRQHandler.*/
#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
#if defined (SL_TRUSTZONE_SECURE)
#define SMU_PRIVILEGED_IRQHandler SMU_S_PRIVILEGED_IRQHandler
#else
#define SMU_PRIVILEGED_IRQHandler SMU_NS_PRIVILEGED_IRQHandler
#endif /* SL_TRUSTZONE_SECURE */
#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG */
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
void Reset_Handler(void); /**< Reset Handler */
void NMI_Handler(void); /**< NMI Handler */
void HardFault_Handler(void); /**< Hard Fault Handler */
void MemManage_Handler(void); /**< MPU Fault Handler */
void BusFault_Handler(void); /**< Bus Fault Handler */
void UsageFault_Handler(void); /**< Usage Fault Handler */
void SecureFault_Handler(void); /**< Secure Fault Handler */
void SVC_Handler(void); /**< SVCall Handler */
void DebugMon_Handler(void); /**< Debug Monitor Handler */
void PendSV_Handler(void); /**< PendSV Handler */
void SysTick_Handler(void); /**< SysTick Handler */
/* Part Specific Interrupts */
void SMU_SECURE_IRQHandler(void); /**< SMU_SECURE IRQ Handler */
void SMU_S_PRIVILEGED_IRQHandler(void); /**< SMU_S_PRIVILEGED IRQ Handler */
void SMU_NS_PRIVILEGED_IRQHandler(void); /**< SMU_NS_PRIVILEGED IRQ Handler */
void EMU_IRQHandler(void); /**< EMU IRQ Handler */
void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */
void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */
void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */
void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */
void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */
void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */
void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */
void EUSART0_RX_IRQHandler(void); /**< EUSART0_RX IRQ Handler */
void EUSART0_TX_IRQHandler(void); /**< EUSART0_TX IRQ Handler */
void EUSART1_RX_IRQHandler(void); /**< EUSART1_RX IRQ Handler */
void EUSART1_TX_IRQHandler(void); /**< EUSART1_TX IRQ Handler */
void EUSART2_RX_IRQHandler(void); /**< EUSART2_RX IRQ Handler */
void EUSART2_TX_IRQHandler(void); /**< EUSART2_TX IRQ Handler */
void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */
void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */
void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */
void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */
void MPAHBRAM_IRQHandler(void); /**< MPAHBRAM IRQ Handler */
void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */
void LFXO_IRQHandler(void); /**< LFXO IRQ Handler */
void LFRCO_IRQHandler(void); /**< LFRCO IRQ Handler */
void ULFRCO_IRQHandler(void); /**< ULFRCO IRQ Handler */
void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */
void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */
void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */
void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */
void EMUDG_IRQHandler(void); /**< EMUDG IRQ Handler */
void AGC_IRQHandler(void); /**< AGC IRQ Handler */
void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */
void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */
void FRC_IRQHandler(void); /**< FRC IRQ Handler */
void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */
void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */
void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */
void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */
void HOSTMAILBOX_IRQHandler(void); /**< HOSTMAILBOX IRQ Handler */
void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */
void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */
void ACMP1_IRQHandler(void); /**< ACMP1 IRQ Handler */
void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */
void WDOG1_IRQHandler(void); /**< WDOG1 IRQ Handler */
void HFXO0_IRQHandler(void); /**< HFXO0 IRQ Handler */
void HFRCO0_IRQHandler(void); /**< HFRCO0 IRQ Handler */
void HFRCOEM23_IRQHandler(void); /**< HFRCOEM23 IRQ Handler */
void CMU_IRQHandler(void); /**< CMU IRQ Handler */
void AES_IRQHandler(void); /**< AES IRQ Handler */
void IADC_IRQHandler(void); /**< IADC IRQ Handler */
void MSC_IRQHandler(void); /**< MSC IRQ Handler */
void DPLL0_IRQHandler(void); /**< DPLL0 IRQ Handler */
void EMUEFP_IRQHandler(void); /**< EMUEFP IRQ Handler */
void DCDC_IRQHandler(void); /**< DCDC IRQ Handler */
void VDAC_IRQHandler(void); /**< VDAC IRQ Handler */
void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */
void SW0_IRQHandler(void); /**< SW0 IRQ Handler */
void SW1_IRQHandler(void); /**< SW1 IRQ Handler */
void SW2_IRQHandler(void); /**< SW2 IRQ Handler */
void SW3_IRQHandler(void); /**< SW3 IRQ Handler */
void KERNEL0_IRQHandler(void); /**< KERNEL0 IRQ Handler */
void KERNEL1_IRQHandler(void); /**< KERNEL1 IRQ Handler */
void M33CTI0_IRQHandler(void); /**< M33CTI0 IRQ Handler */
void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */
void FPUEXH_IRQHandler(void); /**< FPUEXH IRQ Handler */
void SETAMPERHOST_IRQHandler(void); /**< SETAMPERHOST IRQ Handler */
void SEMBRX_IRQHandler(void); /**< SEMBRX IRQ Handler */
void SEMBTX_IRQHandler(void); /**< SEMBTX IRQ Handler */
void LESENSE_IRQHandler(void); /**< LESENSE IRQ Handler */
void SYSRTC_APP_IRQHandler(void); /**< SYSRTC_APP IRQ Handler */
void SYSRTC_SEQ_IRQHandler(void); /**< SYSRTC_SEQ IRQ Handler */
void LCD_IRQHandler(void); /**< LCD IRQ Handler */
void KEYSCAN_IRQHandler(void); /**< KEYSCAN IRQ Handler */
void RFECA0_IRQHandler(void); /**< RFECA0 IRQ Handler */
void RFECA1_IRQHandler(void); /**< RFECA1 IRQ Handler */
#if (__FPU_PRESENT == 1)
void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */
#endif
uint32_t SystemHCLKGet(void);
/**************************************************************************//**
* @brief
* Update CMSIS SystemCoreClock variable.
*
* @details
* CMSIS defines a global variable SystemCoreClock that shall hold the
* core frequency in Hz. If the core frequency is dynamically changed, the
* variable must be kept updated in order to be CMSIS compliant.
*
* Notice that only if changing the core clock frequency through the EMLIB
* CMU API, this variable will be kept updated. This function is only
* provided for CMSIS compliance and if a user modifies the the core clock
* outside the EMLIB CMU API.
*****************************************************************************/
static __INLINE uint32_t SystemCoreClockGet(void)
{
return SystemHCLKGet();
}
/**************************************************************************//**
* @brief
* Update CMSIS SystemCoreClock variable.
*
* @details
* CMSIS defines a global variable SystemCoreClock that shall hold the
* core frequency in Hz. If the core frequency is dynamically changed, the
* variable must be kept updated in order to be CMSIS compliant.
*
* Notice that only if changing the core clock frequency through the EMLIB
* CMU API, this variable will be kept updated. This function is only
* provided for CMSIS compliance and if a user modifies the the core clock
* outside the EMLIB CMU API.
*****************************************************************************/
static __INLINE void SystemCoreClockUpdate(void)
{
SystemHCLKGet();
}
void SystemInit(void);
uint32_t SystemHFRCODPLLClockGet(void);
void SystemHFRCODPLLClockSet(uint32_t freq);
uint32_t SystemSYSCLKGet(void);
uint32_t SystemMaxCoreClockGet(void);
uint32_t SystemFSRCOClockGet(void);
uint32_t SystemHFXOClockGet(void);
void SystemHFXOClockSet(uint32_t freq);
uint32_t SystemCLKIN0Get(void);
uint32_t SystemHFRCOEM23ClockGet(void);
uint32_t SystemLFXOClockGet(void);
void SystemLFXOClockSet(uint32_t freq);
uint32_t SystemLFRCOClockGet(void);
uint32_t SystemULFRCOClockGet(void);
/** @} End of group */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_EFR32ZG23_H */

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/***************************************************************************//**
* @file
* @brief CMSIS Cortex-M33 system support for EFR32ZG23 devices.
******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
*****************************************************************************/
#include <stdint.h>
#include "em_device.h"
/*******************************************************************************
****************************** DEFINES ************************************
******************************************************************************/
/* System oscillator frequencies. These frequencies are normally constant */
/* for a target, but they are made configurable in order to allow run-time */
/* handling of different boards. The crystal oscillator clocks can be set */
/* compile time to a non-default value by defining respective nFXO_FREQ */
/* values according to board design. By defining the nFXO_FREQ to 0, */
/* one indicates that the oscillator is not present, in order to save some */
/* SW footprint. */
#if !defined(FSRCO_FREQ)
/* FSRCO frequency */
#define FSRCO_FREQ (20000000UL)
#endif
#if !defined(HFXO_FREQ)
/* HFXO frequency */
#define HFXO_FREQ (39000000UL)
#endif
#if !defined(HFRCODPLL_STARTUP_FREQ)
/* HFRCODPLL startup frequency */
#define HFRCODPLL_STARTUP_FREQ (19000000UL)
#endif
#if !defined(HFRCODPLL_MAX_FREQ)
/* Maximum HFRCODPLL frequency */
#define HFRCODPLL_MAX_FREQ (80000000UL)
#endif
/* CLKIN0 input */
#if !defined(CLKIN0_FREQ)
#define CLKIN0_FREQ (0UL)
#endif
#if !defined(LFRCO_MAX_FREQ)
/* LFRCO frequency, tuned to below frequency during manufacturing. */
#define LFRCO_FREQ (32768UL)
#endif
#if !defined(ULFRCO_FREQ)
/* ULFRCO frequency */
#define ULFRCO_FREQ (1000UL)
#endif
#if !defined(LFXO_FREQ)
/* LFXO frequency */
#define LFXO_FREQ (LFRCO_FREQ)
#endif
/*******************************************************************************
************************** LOCAL VARIABLES ********************************
******************************************************************************/
#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY)
/* NOTE: Gecko bootloaders can't have static variable allocation. */
/* System HFXO clock frequency */
static uint32_t SystemHFXOClock = HFXO_FREQ;
#endif
#if (LFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY)
/* System LFXO clock frequency */
static uint32_t SystemLFXOClock = LFXO_FREQ;
#endif
#if !defined(SYSTEM_NO_STATIC_MEMORY)
/* System HFRCODPLL clock frequency */
static uint32_t SystemHFRCODPLLClock = HFRCODPLL_STARTUP_FREQ;
#endif
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
#if !defined(SYSTEM_NO_STATIC_MEMORY)
/**
* @brief
* System System Clock Frequency (Core Clock).
*
* @details
* Required CMSIS global variable that must be kept up-to-date.
*/
uint32_t SystemCoreClock = HFRCODPLL_STARTUP_FREQ;
#endif
/*---------------------------------------------------------------------------
* Exception / Interrupt Vector table
*---------------------------------------------------------------------------*/
extern const tVectorEntry __VECTOR_TABLE[16 + EXT_IRQ_COUNT];
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
/**************************************************************************//**
* @brief
* Initialize the system.
*
* @details
* Do required generic HW system init.
*
* @note
* This function is invoked during system init, before the main() routine
* and any data has been initialized. For this reason, it cannot do any
* initialization of variables etc.
*****************************************************************************/
void SystemInit(void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) (&__VECTOR_TABLE[0]);
#endif
#if defined(UNALIGNED_SUPPORT_DISABLE)
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
#if (__FPU_PRESENT == 1)
SCB->CPACR |= ((3U << 10U * 2U) /* set CP10 Full Access */
| (3U << 11U * 2U)); /* set CP11 Full Access */
#endif
/* Secure app takes care of moving between the security states.
* SL_TRUSTZONE_SECURE MACRO is for secure access.
* SL_TRUSTZONE_NONSECURE MACRO is for non-secure access.
* When both the MACROS are not defined, during start-up below code makes sure
* that all the peripherals are accessed from non-secure address except SMU,
* as SMU is used to configure the trustzone state of the system. */
#if !defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_NONSECURE) \
&& defined(__TZ_PRESENT)
#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
CMU->CLKEN1_SET = CMU_CLKEN1_SMU;
#endif
/* config SMU to Secure and other peripherals to Non-Secure. */
SMU->PPUSATD0_CLR = _SMU_PPUSATD0_MASK;
#if defined (SEMAILBOX_PRESENT)
SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & (~SMU_PPUSATD1_SMU & ~SMU_PPUSATD1_SEMAILBOX));
#else
SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & ~SMU_PPUSATD1_SMU);
#endif
/* SAU treats all accesses as non-secure */
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
SAU->CTRL = SAU_CTRL_ALLNS_Msk;
__DSB();
__ISB();
#else
#error "The startup code requires access to the CMSE toolchain extension to set proper SAU settings."
#endif /* __ARM_FEATURE_CMSE */
/* Clear and Enable the SMU PPUSEC and BMPUSEC interrupt. */
NVIC_ClearPendingIRQ(SMU_SECURE_IRQn);
SMU->IF_CLR = SMU_IF_PPUSEC | SMU_IF_BMPUSEC;
NVIC_EnableIRQ(SMU_SECURE_IRQn);
SMU->IEN = SMU_IEN_PPUSEC | SMU_IEN_BMPUSEC;
#endif /*SL_TRUSTZONE_SECURE */
}
/**************************************************************************//**
* @brief
* Get current HFRCODPLL frequency.
*
* @note
* This is a EFR32ZG23 specific function, not part of the
* CMSIS definition.
*
* @return
* HFRCODPLL frequency in Hz.
*****************************************************************************/
uint32_t SystemHFRCODPLLClockGet(void)
{
#if !defined(SYSTEM_NO_STATIC_MEMORY)
return SystemHFRCODPLLClock;
#else
uint32_t ret = 0UL;
/* Get oscillator frequency band */
switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK)
>> _HFRCO_CAL_FREQRANGE_SHIFT) {
case 0:
switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) {
case HFRCO_CAL_CLKDIV_DIV1:
ret = 4000000UL;
break;
case HFRCO_CAL_CLKDIV_DIV2:
ret = 2000000UL;
break;
case HFRCO_CAL_CLKDIV_DIV4:
ret = 1000000UL;
break;
default:
ret = 0UL;
break;
}
break;
case 3:
ret = 7000000UL;
break;
case 6:
ret = 13000000UL;
break;
case 7:
ret = 16000000UL;
break;
case 8:
ret = 19000000UL;
break;
case 10:
ret = 26000000UL;
break;
case 11:
ret = 32000000UL;
break;
case 12:
ret = 38000000UL;
break;
case 13:
ret = 48000000UL;
break;
case 14:
ret = 56000000UL;
break;
case 15:
ret = 64000000UL;
break;
case 16:
ret = 80000000UL;
break;
default:
break;
}
return ret;
#endif
}
/**************************************************************************//**
* @brief
* Set HFRCODPLL frequency value.
*
* @note
* This is a EFR32ZG23 specific function, not part of the
* CMSIS definition.
*
* @param[in] freq
* HFRCODPLL frequency in Hz.
*****************************************************************************/
void SystemHFRCODPLLClockSet(uint32_t freq)
{
#if !defined(SYSTEM_NO_STATIC_MEMORY)
SystemHFRCODPLLClock = freq;
#else
(void) freq; /* Unused parameter */
#endif
}
/***************************************************************************//**
* @brief
* Get the current system clock frequency (SYSCLK).
*
* @details
* Calculate and get the current core clock frequency based on the current
* hardware configuration.
*
* @note
* This is an EFR32ZG23 specific function, not part of the
* CMSIS definition.
*
* @return
* Current system clock (SYSCLK) frequency in Hz.
******************************************************************************/
uint32_t SystemSYSCLKGet(void)
{
uint32_t ret = 0U;
/* Find clock source */
switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) {
case _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL:
ret = SystemHFRCODPLLClockGet();
break;
#if (HFXO_FREQ > 0U)
case _CMU_SYSCLKCTRL_CLKSEL_HFXO:
#if defined(SYSTEM_NO_STATIC_MEMORY)
ret = HFXO_FREQ;
#else
ret = SystemHFXOClock;
#endif
break;
#endif
#if (CLKIN0_FREQ > 0U)
case _CMU_SYSCLKCTRL_CLKSEL_CLKIN0:
ret = CLKIN0_FREQ;
break;
#endif
case _CMU_SYSCLKCTRL_CLKSEL_FSRCO:
ret = FSRCO_FREQ;
break;
default:
/* Unknown clock source. */
while (1) {
}
}
return ret;
}
/***************************************************************************//**
* @brief
* Get the current system core clock frequency (HCLK).
*
* @details
* Calculate and get the current core clock frequency based on the current
* configuration. Assuming that the SystemCoreClock global variable is
* maintained, the core clock frequency is stored in that variable as well.
* This function will however calculate the core clock based on actual HW
* configuration. It will also update the SystemCoreClock global variable.
*
* @note
* This is a EFR32ZG23 specific function, not part of the
* CMSIS definition.
*
* @return
* The current core clock (HCLK) frequency in Hz.
******************************************************************************/
uint32_t SystemHCLKGet(void)
{
uint32_t presc, ret;
ret = SystemSYSCLKGet();
presc = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK)
>> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT;
ret /= presc + 1U;
#if !defined(SYSTEM_NO_STATIC_MEMORY)
/* Keep CMSIS system clock variable up-to-date */
SystemCoreClock = ret;
#endif
return ret;
}
/***************************************************************************//**
* @brief
* Get the maximum core clock frequency.
*
* @note
* This is a EFR32ZG23 specific function, not part of the
* CMSIS definition.
*
* @return
* The maximum core clock frequency in Hz.
******************************************************************************/
uint32_t SystemMaxCoreClockGet(void)
{
return(HFRCODPLL_MAX_FREQ > HFXO_FREQ \
? HFRCODPLL_MAX_FREQ : HFXO_FREQ);
}
/**************************************************************************//**
* @brief
* Get high frequency crystal oscillator clock frequency for target system.
*
* @note
* This is a EFR32ZG23 specific function, not part of the
* CMSIS definition.
*
* @return
* HFXO frequency in Hz. 0 if the external crystal oscillator is not present.
*****************************************************************************/
uint32_t SystemHFXOClockGet(void)
{
/* The external crystal oscillator is not present if HFXO_FREQ==0 */
#if (HFXO_FREQ > 0U)
#if defined(SYSTEM_NO_STATIC_MEMORY)
return HFXO_FREQ;
#else
return SystemHFXOClock;
#endif
#else
return 0U;
#endif
}
/**************************************************************************//**
* @brief
* Set high frequency crystal oscillator clock frequency for target system.
*
* @note
* This function is mainly provided for being able to handle target systems
* with different HF crystal oscillator frequencies run-time. If used, it
* should probably only be used once during system startup.
*
* @note
* This is a EFR32ZG23 specific function, not part of the
* CMSIS definition.
*
* @param[in] freq
* HFXO frequency in Hz used for target.
*****************************************************************************/
void SystemHFXOClockSet(uint32_t freq)
{
/* External crystal oscillator present? */
#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY)
SystemHFXOClock = freq;
/* Update core clock frequency if HFXO is used to clock core */
if ((CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK)
== _CMU_SYSCLKCTRL_CLKSEL_HFXO) {
/* This function will update the global variable */
SystemHCLKGet();
}
#else
(void) freq; /* Unused parameter */
#endif
}
/**************************************************************************//**
* @brief
* Get current CLKIN0 frequency.
*
* @note
* This is a EFR32ZG23 specific function, not part of the
* CMSIS definition.
*
* @return
* CLKIN0 frequency in Hz.
*****************************************************************************/
uint32_t SystemCLKIN0Get(void)
{
return CLKIN0_FREQ;
}
/**************************************************************************//**
* @brief
* Get FSRCO frequency.
*
* @note
* This is a EFR32ZG23 specific function, not part of the
* CMSIS definition.
*
* @return
* FSRCO frequency in Hz.
*****************************************************************************/
uint32_t SystemFSRCOClockGet(void)
{
return FSRCO_FREQ;
}
/**************************************************************************//**
* @brief
* Get current HFRCOEM23 frequency.
*
* @note
* This is a EFR32ZG23 specific function, not part of the
* CMSIS definition.
*
* @return
* HFRCOEM23 frequency in Hz.
*****************************************************************************/
uint32_t SystemHFRCOEM23ClockGet(void)
{
uint32_t ret = 0UL;
/* Get oscillator frequency band */
switch ((HFRCOEM23->CAL & _HFRCO_CAL_FREQRANGE_MASK)
>> _HFRCO_CAL_FREQRANGE_SHIFT) {
case 0:
switch (HFRCOEM23->CAL & _HFRCO_CAL_CLKDIV_MASK) {
case HFRCO_CAL_CLKDIV_DIV1:
ret = 4000000UL;
break;
case HFRCO_CAL_CLKDIV_DIV2:
ret = 2000000UL;
break;
case HFRCO_CAL_CLKDIV_DIV4:
ret = 1000000UL;
break;
default:
ret = 0UL;
break;
}
break;
case 6:
ret = 13000000UL;
break;
case 7:
ret = 16000000UL;
break;
case 8:
ret = 19000000UL;
break;
case 10:
ret = 26000000UL;
break;
case 11:
ret = 32000000UL;
break;
case 12:
ret = 40000000UL;
break;
default:
break;
}
return ret;
}
/**************************************************************************//**
* @brief
* Get low frequency RC oscillator clock frequency for target system.
*
* @note
* This is a EFR32ZG23 specific function, not part of the
* CMSIS definition.
*
* @return
* LFRCO frequency in Hz.
*****************************************************************************/
uint32_t SystemLFRCOClockGet(void)
{
return LFRCO_FREQ;
}
/**************************************************************************//**
* @brief
* Get ultra low frequency RC oscillator clock frequency for target system.
*
* @note
* This is a EFR32ZG23 specific function, not part of the
* CMSIS definition.
*
* @return
* ULFRCO frequency in Hz.
*****************************************************************************/
uint32_t SystemULFRCOClockGet(void)
{
/* The ULFRCO frequency is not tuned, and can be very inaccurate */
return ULFRCO_FREQ;
}
/**************************************************************************//**
* @brief
* Get low frequency crystal oscillator clock frequency for target system.
*
* @note
* This is a EFR32ZG23 specific function, not part of the
* CMSIS definition.
*
* @return
* LFXO frequency in Hz.
*****************************************************************************/
uint32_t SystemLFXOClockGet(void)
{
/* External crystal present? */
#if (LFXO_FREQ > 0U)
#if defined(SYSTEM_NO_STATIC_MEMORY)
return LFXO_FREQ;
#else
return SystemLFXOClock;
#endif
#else
return 0U;
#endif
}
/**************************************************************************//**
* @brief
* Set low frequency crystal oscillator clock frequency for target system.
*
* @note
* This function is mainly provided for being able to handle target systems
* with different HF crystal oscillator frequencies run-time. If used, it
* should probably only be used once during system startup.
*
* @note
* This is a EFR32ZG23 specific function, not part of the
* CMSIS definition.
*
* @param[in] freq
* LFXO frequency in Hz used for target.
*****************************************************************************/
void SystemLFXOClockSet(uint32_t freq)
{
/* External crystal oscillator present? */
#if (LFXO_FREQ > 0U) && !defined(SYSTEM_NO_STATIC_MEMORY)
SystemLFXOClock = freq;
#else
(void) freq; /* Unused parameter */
#endif
}

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/*
* Copyright (C) 2015-2018 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_efr32zg23
* @{
*
* @file
* @brief Startup code and interrupt vector definition
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Bas Stottelaar <basstottelaar@gmail.com>
*
* @}
*/
#include "vectors_cortexm.h"
/* define a local dummy handler as it needs to be in the same compilation unit
* as the alias definition */
void dummy_handler(void)
{
dummy_handler_default();
}
/* Silicon Labs specific interrupt vector */
WEAK_DEFAULT void isr_smu_secure(void);
WEAK_DEFAULT void isr_smu_s_privileged(void);
WEAK_DEFAULT void isr_smu_ns_privileged(void);
WEAK_DEFAULT void isr_emu(void);
WEAK_DEFAULT void isr_timer0(void);
WEAK_DEFAULT void isr_timer1(void);
WEAK_DEFAULT void isr_timer2(void);
WEAK_DEFAULT void isr_timer3(void);
WEAK_DEFAULT void isr_timer4(void);
WEAK_DEFAULT void isr_usart0_rx(void);
WEAK_DEFAULT void isr_usart0_tx(void);
WEAK_DEFAULT void isr_eusart0_rx(void);
WEAK_DEFAULT void isr_eusart0_tx(void);
WEAK_DEFAULT void isr_eusart1_rx(void);
WEAK_DEFAULT void isr_eusart1_tx(void);
WEAK_DEFAULT void isr_eusart2_rx(void);
WEAK_DEFAULT void isr_eusart2_tx(void);
WEAK_DEFAULT void isr_icache0(void);
WEAK_DEFAULT void isr_burtc(void);
WEAK_DEFAULT void isr_letimer0(void);
WEAK_DEFAULT void isr_syscfg(void);
WEAK_DEFAULT void isr_mpahbram(void);
WEAK_DEFAULT void isr_ldma(void);
WEAK_DEFAULT void isr_lfxo(void);
WEAK_DEFAULT void isr_lfrco(void);
WEAK_DEFAULT void isr_ulfrco(void);
WEAK_DEFAULT void isr_gpio_odd(void);
WEAK_DEFAULT void isr_gpio_even(void);
WEAK_DEFAULT void isr_i2c0(void);
WEAK_DEFAULT void isr_i2c1(void);
WEAK_DEFAULT void isr_emudg(void);
WEAK_DEFAULT void isr_agc(void);
WEAK_DEFAULT void isr_bufc(void);
WEAK_DEFAULT void isr_frc_pri(void);
WEAK_DEFAULT void isr_frc(void);
WEAK_DEFAULT void isr_modem(void);
WEAK_DEFAULT void isr_protimer(void);
WEAK_DEFAULT void isr_rac_rsm(void);
WEAK_DEFAULT void isr_rac_seq(void);
WEAK_DEFAULT void isr_hostmailbox(void);
WEAK_DEFAULT void isr_synth(void);
WEAK_DEFAULT void isr_acmp0(void);
WEAK_DEFAULT void isr_acmp1(void);
WEAK_DEFAULT void isr_wdog0(void);
WEAK_DEFAULT void isr_wdog1(void);
WEAK_DEFAULT void isr_hfxo0(void);
WEAK_DEFAULT void isr_hfrco0(void);
WEAK_DEFAULT void isr_hfrcoem23(void);
WEAK_DEFAULT void isr_cmu(void);
WEAK_DEFAULT void isr_aes(void);
WEAK_DEFAULT void isr_iadc(void);
WEAK_DEFAULT void isr_msc(void);
WEAK_DEFAULT void isr_dpll0(void);
WEAK_DEFAULT void isr_emuefp(void);
WEAK_DEFAULT void isr_dcdc(void);
WEAK_DEFAULT void isr_vdac(void);
WEAK_DEFAULT void isr_pcnt0(void);
WEAK_DEFAULT void isr_sw0(void);
WEAK_DEFAULT void isr_sw1(void);
WEAK_DEFAULT void isr_sw2(void);
WEAK_DEFAULT void isr_sw3(void);
WEAK_DEFAULT void isr_kernel0(void);
WEAK_DEFAULT void isr_kernel1(void);
WEAK_DEFAULT void isr_m33cti0(void);
WEAK_DEFAULT void isr_m33cti1(void);
WEAK_DEFAULT void isr_fpuexh(void);
WEAK_DEFAULT void isr_setamperhost(void);
WEAK_DEFAULT void isr_sembrx(void);
WEAK_DEFAULT void isr_sembtx(void);
WEAK_DEFAULT void isr_lesense(void);
WEAK_DEFAULT void isr_sysrtc_app(void);
WEAK_DEFAULT void isr_sysrtc_seq(void);
WEAK_DEFAULT void isr_lcd(void);
WEAK_DEFAULT void isr_keyscan(void);
WEAK_DEFAULT void isr_rfeca0(void);
WEAK_DEFAULT void isr_rfeca1(void);
/* interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[ 0] = isr_smu_secure, /* SMU_SECURE */
[ 1] = isr_smu_s_privileged, /* SMU_S_PRIVILEGED */
[ 2] = isr_smu_ns_privileged, /* SMU_NS_PRIVILEGED */
[ 3] = isr_emu, /* EMU */
[ 4] = isr_timer0, /* TIMER0 */
[ 5] = isr_timer1, /* TIMER1 */
[ 6] = isr_timer2, /* TIMER2 */
[ 7] = isr_timer3, /* TIMER3 */
[ 8] = isr_timer4, /* TIMER4 */
[ 9] = isr_usart0_rx, /* USART0_RX */
[10] = isr_usart0_tx, /* USART0_TX */
[11] = isr_eusart0_rx, /* EUSART0_RX */
[12] = isr_eusart0_tx, /* EUSART0_TX */
[13] = isr_eusart1_rx, /* EUSART1_RX */
[14] = isr_eusart1_tx, /* EUSART1_TX */
[15] = isr_eusart2_rx, /* EUSART2_RX */
[16] = isr_eusart2_tx, /* EUSART2_TX */
[17] = isr_icache0, /* ICACHE0 */
[18] = isr_burtc, /* BURTC */
[19] = isr_letimer0, /* LETIMER0 */
[20] = isr_syscfg, /* SYSCFG */
[21] = isr_mpahbram, /* MPAHBRAM */
[22] = isr_ldma, /* LDMA */
[23] = isr_lfxo, /* LFXO */
[24] = isr_lfrco, /* LFRCO */
[25] = isr_ulfrco, /* ULFRCO */
[26] = isr_gpio_odd, /* GPIO_ODD */
[27] = isr_gpio_even, /* GPIO_EVEN */
[28] = isr_i2c0, /* I2C0 */
[29] = isr_i2c1, /* I2C1 */
[30] = isr_emudg, /* EMUDG */
[31] = isr_agc, /* AGC */
[32] = isr_bufc, /* BUFC */
[33] = isr_frc_pri, /* FRC_PRI */
[34] = isr_frc, /* FRC */
[35] = isr_modem, /* MODEM */
[36] = isr_protimer, /* PROTIMER */
[37] = isr_rac_rsm, /* RAC_RSM */
[38] = isr_rac_seq, /* RAC_SEQ */
[39] = isr_hostmailbox, /* HOSTMAILBOX */
[40] = isr_synth, /* SYNTH */
[41] = isr_acmp0, /* ACMP0 */
[42] = isr_acmp1, /* ACMP1 */
[43] = isr_wdog0, /* WDOG0 */
[44] = isr_wdog1, /* WDOG1 */
[45] = isr_hfxo0, /* HFXO0 */
[46] = isr_hfrco0, /* HFRCO0 */
[47] = isr_hfrcoem23, /* HFRCOEM23 */
[48] = isr_cmu, /* CMU */
[49] = isr_aes, /* AES */
[50] = isr_iadc, /* IADC */
[51] = isr_msc, /* MSC */
[52] = isr_dpll0, /* DPLL0 */
[53] = isr_emuefp, /* EMUEFP */
[54] = isr_dcdc, /* DCDC */
[55] = isr_vdac, /* VDAC */
[56] = isr_pcnt0, /* PCNT0 */
[57] = isr_sw0, /* SW0 */
[58] = isr_sw1, /* SW1 */
[59] = isr_sw2, /* SW2 */
[60] = isr_sw3, /* SW3 */
[61] = isr_kernel0, /* KERNEL0 */
[62] = isr_kernel1, /* KERNEL1 */
[63] = isr_m33cti0, /* M33CTI0 */
[64] = isr_m33cti1, /* M33CTI1 */
[65] = isr_fpuexh, /* FPUEXH */
[66] = isr_setamperhost, /* SETAMPERHOST */
[67] = isr_sembrx, /* SEMBRX */
[68] = isr_sembtx, /* SEMBTX */
[69] = isr_lesense, /* LESENSE */
[70] = isr_sysrtc_app, /* SYSRTC_APP */
[71] = isr_sysrtc_seq, /* SYSRTC_SEQ */
[72] = isr_lcd, /* LCD */
[73] = isr_keyscan, /* KEYSCAN */
[74] = isr_rfeca0, /* RFECA0 */
[75] = isr_rfeca1, /* RFECA1 */
};