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242 lines
23 KiB
C
242 lines
23 KiB
C
/**************************************************************************//**
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* @file
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* @brief EFR32ZG23 DPLL register and bit field definitions
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******************************************************************************
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* # License
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* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
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******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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*****************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef EFR32ZG23_DPLL_H
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#define EFR32ZG23_DPLL_H
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#define DPLL_HAS_SET_CLEAR
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/**************************************************************************//**
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* @addtogroup Parts
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* @{
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******************************************************************************/
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/**************************************************************************//**
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* @defgroup EFR32ZG23_DPLL DPLL
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* @{
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* @brief EFR32ZG23 DPLL Register Declaration.
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*****************************************************************************/
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/** DPLL Register Declaration. */
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typedef struct {
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__IM uint32_t IPVERSION; /**< IP Version */
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__IOM uint32_t EN; /**< Enable */
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__IOM uint32_t CFG; /**< Config */
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__IOM uint32_t CFG1; /**< Config1 */
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__IOM uint32_t IF; /**< Interrupt Flag */
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__IOM uint32_t IEN; /**< Interrupt Enable */
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__IM uint32_t STATUS; /**< Status */
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uint32_t RESERVED0[2U]; /**< Reserved for future use */
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__IOM uint32_t LOCK; /**< Lock */
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uint32_t RESERVED1[1014U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_SET; /**< IP Version */
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__IOM uint32_t EN_SET; /**< Enable */
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__IOM uint32_t CFG_SET; /**< Config */
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__IOM uint32_t CFG1_SET; /**< Config1 */
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__IOM uint32_t IF_SET; /**< Interrupt Flag */
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__IOM uint32_t IEN_SET; /**< Interrupt Enable */
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__IM uint32_t STATUS_SET; /**< Status */
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uint32_t RESERVED2[2U]; /**< Reserved for future use */
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__IOM uint32_t LOCK_SET; /**< Lock */
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uint32_t RESERVED3[1014U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_CLR; /**< IP Version */
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__IOM uint32_t EN_CLR; /**< Enable */
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__IOM uint32_t CFG_CLR; /**< Config */
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__IOM uint32_t CFG1_CLR; /**< Config1 */
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__IOM uint32_t IF_CLR; /**< Interrupt Flag */
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__IOM uint32_t IEN_CLR; /**< Interrupt Enable */
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__IM uint32_t STATUS_CLR; /**< Status */
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uint32_t RESERVED4[2U]; /**< Reserved for future use */
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__IOM uint32_t LOCK_CLR; /**< Lock */
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uint32_t RESERVED5[1014U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_TGL; /**< IP Version */
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__IOM uint32_t EN_TGL; /**< Enable */
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__IOM uint32_t CFG_TGL; /**< Config */
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__IOM uint32_t CFG1_TGL; /**< Config1 */
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__IOM uint32_t IF_TGL; /**< Interrupt Flag */
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__IOM uint32_t IEN_TGL; /**< Interrupt Enable */
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__IM uint32_t STATUS_TGL; /**< Status */
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uint32_t RESERVED6[2U]; /**< Reserved for future use */
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__IOM uint32_t LOCK_TGL; /**< Lock */
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} DPLL_TypeDef;
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/** @} End of group EFR32ZG23_DPLL */
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/**************************************************************************//**
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* @addtogroup EFR32ZG23_DPLL
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* @{
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* @defgroup EFR32ZG23_DPLL_BitFields DPLL Bit Fields
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* @{
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*****************************************************************************/
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/* Bit fields for DPLL IPVERSION */
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#define _DPLL_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DPLL_IPVERSION */
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#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */
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#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */
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#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */
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#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DPLL_IPVERSION */
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#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */
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/* Bit fields for DPLL EN */
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#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */
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#define _DPLL_EN_MASK 0x00000003UL /**< Mask for DPLL_EN */
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#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */
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#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */
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#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */
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#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */
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#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */
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#define DPLL_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */
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#define _DPLL_EN_DISABLING_SHIFT 1 /**< Shift value for DPLL_DISABLING */
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#define _DPLL_EN_DISABLING_MASK 0x2UL /**< Bit mask for DPLL_DISABLING */
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#define _DPLL_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */
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#define DPLL_EN_DISABLING_DEFAULT (_DPLL_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_EN */
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/* Bit fields for DPLL CFG */
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#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */
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#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */
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#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */
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#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */
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#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */
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#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */
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#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */
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#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */
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#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */
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#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */
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#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */
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#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */
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#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */
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#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */
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#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */
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#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */
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#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */
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#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */
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#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */
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#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */
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#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */
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#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */
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#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */
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#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */
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#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */
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#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */
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/* Bit fields for DPLL CFG1 */
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#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */
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#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */
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#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */
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#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */
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#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */
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#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */
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#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */
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#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */
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#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */
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#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */
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/* Bit fields for DPLL IF */
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#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */
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#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */
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#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */
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#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */
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#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */
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#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */
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#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */
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#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */
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#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */
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#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */
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#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */
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#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */
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#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */
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#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */
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#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */
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#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */
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#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */
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/* Bit fields for DPLL IEN */
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#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */
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#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */
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#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */
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#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */
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#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */
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#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */
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#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */
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#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */
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#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */
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#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */
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#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */
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#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */
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#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */
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#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */
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#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */
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#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */
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#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */
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/* Bit fields for DPLL STATUS */
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#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */
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#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */
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#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */
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#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */
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#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */
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#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */
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#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */
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#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */
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#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */
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#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */
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#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */
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#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */
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#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */
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#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */
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#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */
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#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */
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#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */
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#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */
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#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */
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#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */
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#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */
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/* Bit fields for DPLL LOCK */
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#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */
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#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */
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#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */
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#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */
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#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */
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#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */
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#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */
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#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */
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/** @} End of group EFR32ZG23_DPLL_BitFields */
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/** @} End of group EFR32ZG23_DPLL */
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/** @} End of group Parts */
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#endif /* EFR32ZG23_DPLL_H */
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#ifdef __cplusplus
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}
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#endif
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