mirror of
https://github.com/RIOT-OS/RIOT.git
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190 lines
5.9 KiB
C
190 lines
5.9 KiB
C
/*
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* Copyright (C) 2015 Hamburg University of Applied Sciences
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_limifrog-v1
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the limifrog-v1 board
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*
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* @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
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*/
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#ifndef PERIPH_CONF_H_
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#define PERIPH_CONF_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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**/
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#define CLOCK_HSI (16000000U) /* internal oscillator */
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#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
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#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
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#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (1U)
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#define TIMER_0_EN 1
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#define TIMER_IRQ_PRIO 1
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/* Timer 0 configuration */
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#define TIMER_0_DEV_0 TIM2
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#define TIMER_0_DEV_1 TIM3
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#define TIMER_0_CHANNELS 4
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#define TIMER_0_PRESCALER (32U)
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#define TIMER_0_MAX_VALUE (0xffff)
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#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
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#define TIMER_0_ISR_0 isr_tim2
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#define TIMER_0_ISR_1 isr_tim3
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#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
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#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
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#define TIMER_0_IRQ_PRIO 1
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#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0
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/** @} */
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/**
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* @brief UART configuration
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* @{
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*/
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#define UART_NUMOF (2U)
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#define UART_0_EN 1
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#define UART_1_EN 1
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV USART3
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#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART3EN)
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#define UART_0_CLK (CLOCK_CORECLOCK)
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#define UART_0_IRQ USART3_IRQn
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#define UART_0_ISR isr_usart3
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/* UART 0 pin configuration */
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#define UART_0_PORT GPIOC
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#define UART_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
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#define UART_0_RX_PIN 11
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#define UART_0_TX_PIN 10
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#define UART_0_AF 7
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/* UART 1 device configuration */
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#define UART_1_DEV USART3 /* Panasonic PAN1740 BLE module */
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#define UART_1_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
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#define UART_1_CLK (CLOCK_CORECLOCK)
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#define UART_1_IRQ USART1_IRQn
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#define UART_1_ISR isr_usart1
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/* UART 1 pin configuration */
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#define UART_1_PORT GPIOA
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#define UART_1_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define UART_1_RX_PIN 10
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#define UART_1_TX_PIN 9
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#define UART_1_AF 7
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/** @} */
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/**
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* @brief SPI configuration
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* @{
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*/
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#define SPI_NUMOF (2U)
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#define SPI_0_EN 1
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#define SPI_1_EN 1
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/* SPI 0 device configuration */
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#define SPI_0_DEV SPI1 /* Densitron DD-160128FC-1a OLED display; external pins */
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#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
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#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
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#define SPI_0_IRQ SPI1_IRQn
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#define SPI_0_ISR isr_spi1
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/* SPI 0 pin configuration */
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#define SPI_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define SPI_0_PORT GPIOA
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#define SPI_0_PIN_SCK 5
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#define SPI_0_PIN_MOSI 7
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#define SPI_0_PIN_MISO 6
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#define SPI_0_PIN_AF 5
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/* SPI 1 device configuration */
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#define SPI_1_DEV SPI3 /* Adesto AT45DB641E data flash */
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#define SPI_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_SPI3EN)
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#define SPI_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
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#define SPI_1_IRQ SPI3_IRQn
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#define SPI_1_ISR isr_spi3
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/* SPI 1 pin configuration */
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#define SPI_1_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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#define SPI_1_PORT GPIOB
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#define SPI_1_PIN_SCK 3
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#define SPI_1_PIN_MOSI 5
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#define SPI_1_PIN_MISO 4
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#define SPI_1_PIN_AF 6
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (2U)
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#define I2C_0_EN 1
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#define I2C_1_EN 1
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#define I2C_IRQ_PRIO 1
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#define I2C_APBCLK (36000000U)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C1
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#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
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#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
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#define I2C_0_EVT_IRQ I2C1_EV_IRQn
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#define I2C_0_EVT_ISR isr_i2c1_ev
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#define I2C_0_ERR_IRQ I2C1_ER_IRQn
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#define I2C_0_ERR_ISR isr_i2c1_er
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/* I2C 0 pin configuration */
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#define I2C_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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#define I2C_0_PORT GPIOB
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#define I2C_0_SCL_PIN 8
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#define I2C_0_SCL_AF 4
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#define I2C_0_SDA_PIN 9
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#define I2C_0_SDA_AF 4
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/* I2C 1 device configuration */
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#define I2C_1_DEV I2C2 /* ST VL6180X, ST LSM6DS3, ST LIS3MDL, ST SLPS25H */
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#define I2C_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C2EN)
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#define I2C_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
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#define I2C_1_EVT_IRQ I2C2_EV_IRQn
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#define I2C_1_EVT_ISR isr_i2c2_ev
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#define I2C_1_ERR_IRQ I2C2_ER_IRQn
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#define I2C_1_ERR_ISR isr_i2c2_er
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/* I2C 1 pin configuration */
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#define I2C_1_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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#define I2C_1_PORT GPIOB
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#define I2C_1_SCL_PIN 10
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#define I2C_1_SCL_AF 4
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#define I2C_1_SDA_PIN 11
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#define I2C_1_SDA_AF 4
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PERIPH_CONF_H */
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/** @} */
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