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cpu: Add clock source selection based on CLOCK_HSE or CLOCK_HSI for STM32L1 family

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This commit is contained in:
DipSwitch 2015-08-25 10:12:48 +02:00
parent ded2659dc8
commit 148acc684b
3 changed files with 32 additions and 18 deletions
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8
boards/limifrog-v1/include/periph_conf.h
View File

@ -27,13 +27,13 @@ extern "C" {
* @name Clock system configuration
* @{
**/
#define CLOCK_HSE (16000000U) /* external oscillator */
#define CLOCK_HSI (16000000U) /* internal oscillator */
#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSI / PLL_HSI_DIV * PLL_HSI_MUL */
#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLDIV2
#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMUL4
/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */

8
boards/nucleo-l1/include/periph_conf.h
View File

@ -27,12 +27,12 @@ extern "C" {
* @name Clock system configuration
* @{
**/
#define CLOCK_HSI (16000000U) /* frequency of external oscillator */
#define CLOCK_HSI (16000000U) /* frequency of internal oscillator */
#define CLOCK_CORECLOCK (32000000U) /* targeted core clock frequency */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSI / PLL_HSI_DIV * PLL_HSI_MUL */
#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLDIV2
#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMUL4
/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */

34
cpu/stm32l1/cpu.c
View File

@ -14,6 +14,7 @@
* @brief Implementation of the kernel cpu functions
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
*
* @}
*/
@ -22,6 +23,21 @@
#include "board.h"
#include "periph_conf.h"
/* Check the source to be used for the PLL */
#if defined(CLOCK_HSI) && defined(CLOCK_HSE)
#error "Only provide one of two CLOCK_HSI/CLOCK_HSE"
#elif CLOCK_HSI
#define CLOCK_CR_SOURCE RCC_CR_HSION
#define CLOCK_CR_SOURCE_RDY RCC_CR_HSIRDY
#define CLOCK_PLL_SOURCE RCC_CFGR_PLLSRC_HSI
#elif CLOCK_HSE
#define CLOCK_CR_SOURCE RCC_CR_HSEON
#define CLOCK_CR_SOURCE_RDY RCC_CR_HSERDY
#define CLOCK_PLL_SOURCE RCC_CFGR_PLLSRC_HSE
#else
#error "Please provide CLOCK_HSI or CLOCK_HSE in boards/NAME/includes/perhip_cpu.h"
#endif
static void clk_init(void);
void cpu_init(void)
@ -34,7 +50,6 @@ void cpu_init(void)
/**
* @brief Configure the clock system of the stm32f1
*
*/
static void clk_init(void)
{
@ -45,15 +60,15 @@ static void clk_init(void)
RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL);
/* Reset HSION, HSEON, CSSON and PLLON bits */
RCC->CR &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON);
/* Disable all interruptss */
/* Disable all interrupts */
RCC->CIR = 0x0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */
/* Enable HSE */
RCC->CR |= RCC_CR_HSION;
/* Wait till HSE is ready,
* NOTE: the MCU will stay here forever if no HSE clock is connected */
while (!(RCC->CR & RCC_CR_HSIRDY));
/* Enable high speed clock source */
RCC->CR |= CLOCK_CR_SOURCE;
/* Wait till the high speed clock source is ready
* NOTE: the MCU will stay here forever if you use an external clock source and it's not connected */
while (!(RCC->CR & CLOCK_CR_SOURCE_RDY));
FLASH->ACR |= FLASH_ACR_ACC64;
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTEN;
@ -67,14 +82,13 @@ static void clk_init(void)
while((PWR->CSR & PWR_CSR_VOSF) != 0);
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)CLOCK_AHB_DIV;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)CLOCK_APB2_DIV;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)CLOCK_APB1_DIV;
/* PLL configuration: PLLCLK = HSE / HSE_DIV * HSE_MUL */
/* PLL configuration: PLLCLK = CLOCK_SOURCE / PLL_DIV * PLL_MUL */
RCC->CFGR &= ~((uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI | CLOCK_PLL_HSE_DIV | CLOCK_PLL_HSE_MUL);
RCC->CFGR |= (uint32_t)(CLOCK_PLL_SOURCE | CLOCK_PLL_DIV | CLOCK_PLL_MUL);
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */