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139 lines
4.7 KiB
C
139 lines
4.7 KiB
C
/*
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* Copyright (C) 2017 Ken Rabold, JP Bonn
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_hifive1
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* @{
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*
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* @file
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* @brief Support for the SiFive HiFive1 RISC-V board
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*
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* @author Ken Rabold, JP Bonn
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*
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* @}
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*/
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#include <stdio.h>
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#include <errno.h>
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#include "cpu.h"
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#include "board.h"
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#include "periph/gpio.h"
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#include "vendor/encoding.h"
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#include "vendor/platform.h"
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#include "vendor/prci_driver.h"
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/*
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* Configure the memory mapped flash for faster throughput
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* to minimize interrupt latency on an I-Cache miss and refill
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* from flash. Alternatively (and faster) the interrupt
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* routine could be put in SRAM. The linker script supports
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* code in SRAM using the ".hotcode" section.
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* The flash chip on the HiFive1 is the ISSI 25LP128
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* http://www.issi.com/WW/pdf/25LP128.pdf
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* The maximum frequency it can run at is 133MHz in
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* "Fast Read Dual I/O" mode.
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* Note the updated data sheet:
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* https://static.dev.sifive.com/SiFive-FE310-G000-datasheet-v1.0.4.pdf
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* states "Address and write data using DQ[3] for transmission will not
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* function properly." This rules out QPI for the XIP memory mapped flash.
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* #define MAX_FLASH_FREQ 133000000
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* On forum SiFive says "safe" operation would be 40MHz. 50MHz seems to work
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* fine.
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*/
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#define MAX_FLASH_FREQ 50000000
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/*
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* CPU max is 320MHz+ according to datasheet but
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* the relationship between cpu clock and spi clock is determined
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* by SCKDIV. Given we're trying to achieve maximum I-cache refill
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* for the flash we let MAX_FLASH_FREQ dictate the CPU clock.
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*/
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#define CPU_DESIRED_FREQ 200000000
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/*
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* The relationship between the input clock and SCK is given
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* by the following formula (Fin is processor/tile-link clock):
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* Fsck = Fin/(2(div + 1))
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* FYI - For 320MHZ it seems to be tolerating a faster SPI clock (56MHz)
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*/
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#define SCKDIV ((CPU_DESIRED_FREQ - 1) / (MAX_FLASH_FREQ * 2))
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/* This should work for any reasonable cpu clock value. */
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#define SCKDIV_SAFE 3
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/*
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* By default the SPI initialized as:
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* https://github.com/sifive/sifive-blocks/blob/master/src/main/scala/devices/spi/SPIFlash.scala
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* insn.cmd.en := Bool(true)
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* insn.cmd.code := Bits(0x03)
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* insn.cmd.proto := SPIProtocol.Single
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* insn.addr.len := UInt(3)
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* insn.addr.proto := SPIProtocol.Single
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* insn.pad.cnt := UInt(0)
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* insn.pad.code := Bits(0)
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* insn.data.proto := SPIProtocol.Single
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*
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* 25LP128 appears to left in post-reset default state. Boot code
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* does not modify it. We change the SPI configuration here.
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*/
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void board_init_clock(void)
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{
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/* In case we are executing from QSPI, (which is quite likely) we need to
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* set the QSPI clock divider appropriately before boosting the clock
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* frequency. PRCI_set_hfrosctrim_for_f_cpu() tries multiple clocks
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* so choose a safe value that should work for all frequencies.
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*/
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SPI0_REG(SPI_REG_SCKDIV) = SCKDIV_SAFE;
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/* Note: The range is limited to ~100MHz and depends on PLL settings */
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PRCI_set_hfrosctrim_for_f_cpu(CPU_DESIRED_FREQ, PRCI_FREQ_UNDERSHOOT);
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/* begin{code-style-ignore} */
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SPI0_REG(SPI_REG_FFMT) = /* setup "Fast Read Dual I/O" 1-1-2 */
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SPI_INSN_CMD_EN | /* Enable memory-mapped flash */
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SPI_INSN_ADDR_LEN(3) | /* 25LP128 read commands have 3 address bytes */
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SPI_INSN_PAD_CNT(4) | /* 25LP128 Table 6.9 Read Dummy Cycles P4,P3=0,0 */
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SPI_INSN_CMD_PROTO(SPI_PROTO_S) | /* 25LP128 Table 8.1 "Instruction */
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SPI_INSN_ADDR_PROTO(SPI_PROTO_D) | /* Set" shows mode for cmd, addr, and */
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SPI_INSN_DATA_PROTO(SPI_PROTO_D) | /* data protocol for given instruction */
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SPI_INSN_CMD_CODE(0xbb) | /* Set the instruction to "Fast Read Dual I/O" */
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SPI_INSN_PAD_CODE(0x00); /* Dummy cycle sends 0 value bits */
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/* end{code-style-ignore} */
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SPI0_REG(SPI_REG_SCKDIV) = SCKDIV;
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}
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void board_init(void)
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{
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/* Initialize CPU and clocks */
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cpu_init();
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board_init_clock();
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/* Configure pin muxing for UART0 */
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GPIO_REG(GPIO_OUTPUT_VAL) |= IOF0_UART0_MASK;
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GPIO_REG(GPIO_OUTPUT_EN) |= IOF0_UART0_MASK;
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GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
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GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
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/* Configure GPIOs for LEDs */
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gpio_init(LED0_PIN, GPIO_OUT);
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gpio_init(LED1_PIN, GPIO_OUT);
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gpio_init(LED2_PIN, GPIO_OUT);
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/* Turn all the LEDs off */
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LED0_OFF;
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LED1_OFF;
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LED2_OFF;
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/* Initialize newlib-nano library stubs */
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nanostubs_init();
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}
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