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https://github.com/RIOT-OS/RIOT.git
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125 lines
4.2 KiB
C
125 lines
4.2 KiB
C
/*
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* Copyright (C) 2019 Koen Zandberg
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* 2022 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup drivers_periph_usbdev
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* @{
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*
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* @file
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* @brief Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core
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*
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* @author Koen Zandberg <koen@bergzand.net>
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* @author Gunar Schorcht <gunar@schorcht.net>
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*/
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#ifndef USBDEV_SYNOPSYS_DWC2_H
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#define USBDEV_SYNOPSYS_DWC2_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief USB OTG peripheral requirement for setting the device address
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*
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* The address in the USB device has to be directly after the SETUP
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* stage on receipt of the `SET ADDRESS Request`.
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*/
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#define USBDEV_CPU_SET_ADDR_AFTER_STATUS 0
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/**
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* @brief USB OTG peripheral type.
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*
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* High speed peripheral is assumed to have DMA support available.
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*
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* @warning Only one of each type is supported at the moment, it is not
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* supported to have two FS type or two HS type peripherals enabled on a
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* single MCU.
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*/
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typedef enum {
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DWC2_USB_OTG_FS = 0, /**< Full speed peripheral */
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DWC2_USB_OTG_HS = 1, /**< High speed peripheral */
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} dwc2_usb_otg_fshs_type_t;
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/**
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* @brief Device speed used
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*/
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enum {
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DWC2_USB_OTG_DSPD_HS = 0, /**< High speed */
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DWC2_USB_OTG_DSPD_FS_PHY_HS = 1, /**< Full speed on HS PHY */
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DWC2_USB_OTG_DSPD_LS = 2, /**< Low speed */
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DWC2_USB_OTG_DSPD_FS = 3, /**< Full speed */
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};
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/**
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* @brief Type of USB OTG peripheral PHY.
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*
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* The FS type only supports the built-in PHY, the HS type can have enabled
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* either
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* - the on-chip FS PHY,
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* - the external ULPI HS PHY interface, or
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* - the internal UTMI HS PHY.
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*/
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typedef enum {
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DWC2_USB_OTG_PHY_BUILTIN, /**< on-chip FS PHY */
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DWC2_USB_OTG_PHY_ULPI, /**< ULPI for external HS PHY */
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DWC2_USB_OTG_PHY_UTMI, /**< UTMI for internal HS PHY */
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} dwc2_usb_otg_fshs_phy_t;
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/**
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* @brief USB OTG configuration
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*/
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typedef struct {
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uintptr_t periph; /**< USB peripheral base address */
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dwc2_usb_otg_fshs_type_t type; /**< FS or HS type */
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dwc2_usb_otg_fshs_phy_t phy; /**< on-chip FS, ULPI HS or UTMI HS PHY */
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#if defined(MODULE_PERIPH_USBDEV_HS_ULPI) || DOXYGEN
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gpio_t ulpi_clk; /**< ULPI CLK gpio */
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gpio_t ulpi_d0; /**< ULPI D0 gpio */
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gpio_t ulpi_d1; /**< ULPI D1 gpio */
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gpio_t ulpi_d2; /**< ULPI D2 gpio */
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gpio_t ulpi_d3; /**< ULPI D3 gpio */
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gpio_t ulpi_d4; /**< ULPI D4 gpio */
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gpio_t ulpi_d5; /**< ULPI D5 gpio */
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gpio_t ulpi_d6; /**< ULPI D6 gpio */
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gpio_t ulpi_d7; /**< ULPI D7 gpio */
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gpio_t ulpi_dir; /**< ULPI DIR gpio */
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gpio_t ulpi_stp; /**< ULPI STP gpio */
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gpio_t ulpi_nxt; /**< ULPI NXT gpio */
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gpio_af_t ulpi_af; /**< Alternative function for ULPI */
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#endif
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#if defined(CPU_STM32) || DOXYGEN
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uint32_t rcc_mask; /**< bit in clock enable register */
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uint8_t irqn; /**< IRQ channel */
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uint8_t ahb; /**< AHB bus */
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gpio_t dm; /**< Data- gpio */
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gpio_t dp; /**< Data+ gpio */
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gpio_af_t af; /**< Alternative function */
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#if defined(MODULE_PERIPH_USBDEV_HS_UTMI) || DOXYGEN
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uint32_t phy_tune; /**< USB HS PHY controller tuning register
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* value (STM32-specific), see USBPHYC_TUNE
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* register in STM32 Reference Manual */
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#endif /* defined(MODULE_PERIPH_USBDEV_HS_UTMI) */
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#endif /* defined(CPU_STM32) || DOXYGEN */
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#if defined(CPU_GD32V)
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uint32_t rcu_mask; /**< bit in clock enable register */
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uint8_t irqn; /**< IRQ channel */
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uint8_t bus; /**< Peripheral bus */
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#endif
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} dwc2_usb_otg_fshs_config_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* USBDEV_SYNOPSYS_DWC2_H */
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/** @} */
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