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cde8ac6093
The NXP QN908x CPU family is a Cortex-M4F CPU with integrated USB, Bluetooth Low Energy and in some variants NFC. This patch implements the first steps for having support for this CPU. While the QN908x can be considered the successor of similar chips from NXP like the KW41Z when looking at the feature set, the internal architecture, boot image format and CPU peripherals don't match those in the Kinetis line. Therefore, this patch creates a new directory for just the QN908x chip under cpu/qn908x. The minimal set of peripherals are implemented in this patch to allow the device to boot and enable a GPIO: the gpio and wdt peripheral modules only. The wdt driver is required to boot and disable the wdt. On reset, the wdt is disabled by the chip, however the QN908x bootloader stored in the internal ROM enables the wdt and sets a timer to reboot after 10 seconds, therefore it is needed to disable the wdt in RIOT OS soon after booting. This patch sets it up such that when no periph_wdt module is used the Watchdog is disabled, but if the periph_wdt is used it must be configured (initialized) within the first 10 seconds. Tests performed: Defined a custom board for this CPU and compiled a simple application that blinks some LEDs. Manually tested with periph_wdt and with periph_wdt_cb as well.
121 lines
4.0 KiB
Plaintext
121 lines
4.0 KiB
Plaintext
# Copyright (c) 2020 iosabi
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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#
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menu "QN908x clock configuration"
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depends on CPU_FAM_QN908X
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config BOARD_HAS_XTAL32K
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bool
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help
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Indicates that the board has an external low frequency 32.786 KHz
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crystal oscillator connected to the XTAL32_IN / XTAL32_OUT pins.
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This should only be set from board definition.
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choice
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prompt "32K low frequency clock selector"
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default CPU_CLK_32K_XTAL if BOARD_HAS_XTAL32K
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default CPU_CLK_32K_RCO
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help
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The "32K" clock bus runs at either 32 KHz from the internal RCO or
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32.768 KHz from an external crystal oscillator. This clock can be used
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to drive the "System clock" for a very low power operation, but it can
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independently also be used for the watchdog timer (WDT) and other low
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frequency system timers like a real time clock.
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config CPU_CLK_32K_XTAL
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bool "External 32.768 KHz crystal"
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depends on BOARD_HAS_XTAL32K
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config CPU_CLK_32K_RCO
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bool "Internal 32 KHz oscillator"
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endchoice
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config BOARD_HAS_XTAL
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bool
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help
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Indicates that the board has an external high frequency crystal
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oscillator connected to the XTAL_IN / XTAL_OUT pins.
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This should only be set from board definition.
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config BOARD_HAS_XTAL_16M
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bool
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imply BOARD_HAS_XTAL
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depends on !BOARD_HAS_XTAL_32M
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help
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Indicates that the external high frequency crystal oscillator is a
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16 MHz crystal. This should only be set from board definition.
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config BOARD_HAS_XTAL_32M
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bool
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imply BOARD_HAS_XTAL
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help
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Indicates that the external high frequency crystal oscillator is a
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32 MHz crystal. This should only be set from board definition.
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config CPU_CLK_OSC32M_DIV
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bool "Internal OSC32M clock input /2 divider"
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help
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Selecting this option will set the high-speed internal oscillator
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divider to /2, making it a 16 MHz clock source. See "System clock
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configuration selector" for selecting this source.
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config CPU_CLK_XTAL_DIV
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bool "External XTAL 32 MHz clock input /2 divider"
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depends on BOARD_HAS_XTAL_32M
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help
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Selecting this option will set the high-speed external crystal
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oscillator divider to /2. This option is only available when the
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external oscillator is a 32 MHz one. See "System clock
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configuration selector" for selecting this source.
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choice
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prompt "System clock configuration selector"
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default CPU_CLK_SYS_XTAL if BOARD_HAS_XTAL
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default CPU_CLK_SYS_OSC32M
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help
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The System clock is used to derive the AHB clock, which drives the ARM
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core and most peripherals.
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config CPU_CLK_SYS_XTAL
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bool "External 16/32 MHz crystal source (with optional divider)"
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depends on BOARD_HAS_XTAL
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config CPU_CLK_SYS_OSC32M
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bool "Internal 32 MHz oscillator source (with optional divider)"
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config CPU_CLK_SYS_32K
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bool "Low frequency clock source (32 or 32.768 KHz)"
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endchoice
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config CPU_CLK_AHB_DIV
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int "AHB clock divider"
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default 1
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range 1 8192
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help
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The AHB clock is derived from the System clock using this divider value,
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between 1 and 8192, and serves as a clock source for ARM core, FSP, SCT,
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Quad-SPI, Flexcomm (UART, SPI, I2C), GPIO, BLE_AHB and DMA.
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Note: When BLE is enabled, the AHB clock must be at least the BLE clock
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(either 8 or 16 MHz) limiting the range of allowed values for this
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divider so that the AHB clock is 8, 16 or 32 MHz.
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config CPU_CLK_APB_DIV
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int "APB clock divider"
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default 1
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range 1 16
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help
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The APB clock is derived from the AHB clock using this divide value,
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between 1 and 16, and serves as the clock source for several
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peripherals, such as the RTC, ADC, DAC, Capacitive Sense (CS) and
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optionally the WDT.
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# TODO: Add USB PLL and BLE clock selectors.
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endmenu
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