mirror of
https://github.com/RIOT-OS/RIOT.git
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187 lines
7.5 KiB
C
187 lines
7.5 KiB
C
/*
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* Copyright (C) 2016 Leon George
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc26xx_cc13xx_definitions
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* @{
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*
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* @file
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* @brief CC26xx/CC13xx MCU I/O register definitions
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*
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* @author Leon George <leon@georgemail.eu>
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*/
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#ifndef CC26XX_CC13XX_IOC_H
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#define CC26XX_CC13XX_IOC_H
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#include "cc26xx_cc13xx.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define MCU_IOC_BASE (0x40081000) /**< IOC (MCU) base address */
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/** @} */
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/**
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* @brief obtain IOCFG-register for a DIO
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*
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* @param[in] dio_num DIO number (0-31)
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*/
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typedef struct {
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reg32_t CFG[32]; /**< Config */
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} cc26x0_ioc_regs_t;
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#define IOC ((cc26x0_ioc_regs_t *)(MCU_IOC_BASE)) /**< IOC register banks */
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/**
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* @name values for IOCFG
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* @{
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*/
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#define IOCFG_PORTID_GPIO 0x00000000 /**< GPIO */
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#ifdef CPU_VARIANT_X0
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#define IOCFG_PORTID_AON_SCS 0x00000001 /**< AON SPI-S SCS */
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#define IOCFG_PORTID_AON_SCK 0x00000002 /**< AON SPI-S SCK */
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#define IOCFG_PORTID_AON_SDI 0x00000003 /**< AON SPI-S SDI */
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#define IOCFG_PORTID_AON_SDO 0x00000004 /**< AON SPI-S SDO */
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#endif /* CPU_VARIANT_X0 */
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#define IOCFG_PORTID_AON_CLK32K 0x00000007 /**< AON external 32kHz clock */
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#define IOCFG_PORTID_AUX_IO 0x00000008 /**< AUX IO */
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#define IOCFG_PORTID_SSI0_RX 0x00000009 /**< SSI0 receive */
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#define IOCFG_PORTID_SSI0_TX 0x0000000A /**< SSI0 transmit */
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#define IOCFG_PORTID_SSI0_FSS 0x0000000B /**< SSI0 FSS */
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#define IOCFG_PORTID_SSI0_CLK 0x0000000C /**< SSI0 clock */
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#define IOCFG_PORTID_I2C_MSSDA 0x0000000D /**< I2C data */
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#define IOCFG_PORTID_I2C_MSSCL 0x0000000E /**< I2C clock */
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#define IOCFG_PORTID_UART0_RX 0x0000000F /**< UART0 receive */
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#define IOCFG_PORTID_UART0_TX 0x00000010 /**< UART0 transmit */
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#define IOCFG_PORTID_UART0_CTS 0x00000011 /**< UART0 clear to send */
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#define IOCFG_PORTID_UART0_RTS 0x00000012 /**< UART0 request to send */
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#ifdef CPU_VARIANT_X2
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#define IOCFG_PORTID_UART1_RX 0x00000013 /**< UART1 receive */
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#define IOCFG_PORTID_UART1_TX 0x00000014 /**< UART1 transmit */
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#define IOCFG_PORTID_UART1_CTS 0x00000015 /**< UART1 clear to send */
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#define IOCFG_PORTID_UART1_RTS 0x00000016 /**< UART1 request to send */
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#endif // CPU_VARIANT_X2
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#define IOCFG_PORTID_PORT_EVT0 0x00000017 /**< PORT EVENT 0 */
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#define IOCFG_PORTID_PORT_EVT1 0x00000018 /**< PORT EVENT 1 */
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#define IOCFG_PORTID_PORT_EVT2 0x00000019 /**< PORT EVENT 2 */
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#define IOCFG_PORTID_PORT_EVT3 0x0000001A /**< PORT EVENT 3 */
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#define IOCFG_PORTID_PORT_EVT4 0x0000001B /**< PORT EVENT 4 */
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#define IOCFG_PORTID_PORT_EVT5 0x0000001C /**< PORT EVENT 5 */
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#define IOCFG_PORTID_PORT_EVT6 0x0000001D /**< PORT EVENT 6 */
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#define IOCFG_PORTID_PORT_EVT7 0x0000001E /**< PORT EVENT 7 */
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#define IOCFG_PORTID_SWV 0x00000020 /**< serial wire viewer */
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#define IOCFG_PORTID_SSI1_RX 0x00000021 /**< SSI1 receive */
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#define IOCFG_PORTID_SSI1_TX 0x00000022 /**< SSI1 transmit */
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#define IOCFG_PORTID_SSI1_FSS 0x00000023 /**< SSI1 FSS */
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#define IOCFG_PORTID_SSI1_CLK 0x00000024 /**< SSI1 clock */
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#define IOCFG_PORTID_I2S_AD0 0x00000025 /**< I2S data 0 */
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#define IOCFG_PORTID_I2S_AD1 0x00000026 /**< I2S data 1 */
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#define IOCFG_PORTID_I2S_WCLK 0x00000027 /**< I2S frame/word clock */
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#define IOCFG_PORTID_I2S_BCLK 0x00000028 /**< I2S bit clock */
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#define IOCFG_PORTID_I2S_MCLK 0x00000029 /**< I2S master clock 2 */
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#define IOCFG_PORTID_RFC_TRC 0x0000002E /**< RF core trace */
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#define IOCFG_PORTID_RFC_GPO0 0x0000002F /**< RC core data out 0 */
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#define IOCFG_PORTID_RFC_GPO1 0x00000030 /**< RC core data out 1 */
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#define IOCFG_PORTID_RFC_GPO2 0x00000031 /**< RC core data out 2 */
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#define IOCFG_PORTID_RFC_GPO3 0x00000032 /**< RC core data out 3 */
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#define IOCFG_PORTID_RFC_GPI0 0x00000033 /**< RC core data in 0 */
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#define IOCFG_PORTID_RFC_GPI1 0x00000034 /**< RC core data in 1 */
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#define IOCFG_PORTID_RFC_SMI_DL_OUT 0x00000035 /**< RF core SMI data link out */
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#define IOCFG_PORTID_RFC_SMI_DL_IN 0x00000036 /**< RF core SMI data link in */
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#define IOCFG_PORTID_RFC_SMI_CMD_OUT 0x00000037 /**< RF core SMI command link out */
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#define IOCFG_PORTID_RFC_SMI_CMD_IN 0x00000038 /**< RF core SMI command link in */
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#define IOCFG_IOSTR_AUTO 0x00000000 /**< automatic drive strength (2/4/8 mA @ VVDS) */
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#define IOCFG_IOSTR_MAX 0x00000300 /**< maximum drive strength (2/4/8 mA @ 1.8V) */
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#define IOCFG_IOSTR_MED 0x00000200 /**< medium drive strength (2/4/8 mA @ 2.5V) */
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#define IOCFG_IOSTR_MIN 0x00000100 /**< minimum drive strength (2/4/8 mA @ 3.3V) */
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#define IOCFG_IOCURR_2MA 0x00000000 /**< 2mA drive strength */
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#define IOCFG_IOCURR_4MA 0x00000400 /**< 4mA drive strength */
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#define IOCFG_IOCURR_8MA 0x00000800 /**< 4 or 8mA drive strength */
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#define IOCFG_IOCURR_16MA 0x00000C00 /**< Up to 16mA drive strength */
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#define IOCFG_SLEW_RED 0x00001000 /**< reduced slew rate */
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#define IOCFG_PULLCTL_OFF 0x00006000 /**< no IO pull */
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#define IOCFG_PULLCTL_UP 0x00004000 /**< pull up */
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#define IOCFG_PULLCTL_DOWN 0x00002000 /**< pull down */
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#define IOCFG_EDGEDET_FALLING 0x00010000 /**< edge detection on falling edge */
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#define IOCFG_EDGEDET_RISING 0x00020000 /**< edge detection on rising edge */
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#define IOCFG_EDGEDET_BOTH 0x00030000 /**< edge detection on both edges */
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#define IOCFG_EDGEIRQ_ENABLE 0x00040000 /**< enable interrupt on edge detect */
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/* n/a when port_id is AON or AUX */
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#define IOCFG_IOMODE_INV 0x01000000 /**< inverted I/O */
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#define IOCFG_IOMODE_OPEN_DRAIN 0x04000000 /**< open drain */
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#define IOCFG_IOMODE_OPEN_SRC 0x06000000 /**< open source */
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/* both enable waking up when port_id is AON or AUX */
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#define IOCFG_WUCFG_LOW 0x10000000
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#define IOCFG_WUCFG_HIGH 0x18000000
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/* ignored if port_id is AUX */
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#define IOCFG_INPUT_ENABLE 0x20000000
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#define IOCFG_HYST_ENABLE 0x40000000
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/** @} */
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/**
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* @brief AON_IOC registers
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*/
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typedef struct {
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reg32_t IOSTRMIN; /**< IO Drive Strength Minimum */
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reg32_t IOSTRMED; /**< IO Drive Strength Medium */
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reg32_t IOSTRMAX; /**< IO Drive Strength Maximum */
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reg32_t IOCLATCH; /**< IO Latch Control */
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reg32_t CLK32KCTL; /**< SCLK_LF External Output Control */
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#ifdef CPU_VARIANT_X2
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reg32_t TCKCTL; /**< TCK IO Pin Control */
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#endif
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} aon_ioc_regs_t;
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/**
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* @brief AON_IOC register values
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* @{
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*/
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#define AON_IOC_IOCLATCH_EN 0x00000001
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#define AON_IOC_CLK32KCTL_OEN 0x00000001
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/** @} */
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief AON_IOC base address
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*/
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#define AON_IOC_BASE (PERIPH_BASE + 0x94000)
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/** @} */
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/**
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* @brief AON_IOC register bank
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*/
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#define AON_IOC ((aon_ioc_regs_t *) (AON_IOC_BASE))
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#ifdef __cplusplus
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}
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#endif
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#endif /* CC26XX_CC13XX_IOC_H */
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/** @} */
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