mirror of
https://github.com/RIOT-OS/RIOT.git
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182 lines
6.9 KiB
C
182 lines
6.9 KiB
C
/*
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* Copyright (C) 2016 Leon George
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc26xx_cc13xx_definitions
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* @{
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*
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* @file
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* @brief CC26xx, CC13xx definitions
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*
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* @author Leon M. George <leon@georgemail.eu>
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* @author Anton Gerasimov <tossel@gmail.com>
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*/
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#ifndef CC26XX_CC13XX_H
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#define CC26XX_CC13XX_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Unsigned 8-bit register type.
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*/
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typedef volatile uint8_t reg8_t;
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/**
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* @brief Unsigned 16-bit register type.
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*/
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typedef volatile uint16_t reg16_t;
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/**
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* @brief Unsigned 32-bit register type.
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*/
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typedef volatile uint32_t reg32_t;
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/**
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* @brief Masked 8-bit register
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*/
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typedef struct {
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reg8_t LOW; /**< Low 4-bit half */
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reg8_t HIGH; /**< High 4-bit half */
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} reg8_m4_t;
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/**
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* @brief Masked 8-bit register
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*/
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typedef reg16_t reg8_m8_t;
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/**
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* @brief Masked 32-bit register
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*/
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typedef struct {
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reg32_t LOW; /**< Low 16-bit half */
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reg32_t HIGH; /**< High 16-bit half */
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} reg32_m16_t;
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/**
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* @addtogroup CC13x2_cmsis CMSIS Definitions
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* @{
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*/
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/**
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* @brief Interrupt number definition
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*/
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typedef enum IRQn {
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/****** Cortex-M4 Processor Exceptions Numbers ****************************/
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ResetHandler_IRQn = -15, /**< 1 Reset Handler */
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NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /**< 3 Cortex-M4 Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */
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BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */
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SVCall_IRQn = - 5, /**< 11 Cortex-M4 SV Call Interrupt */
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DebugMonitor_IRQn = - 4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
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PendSV_IRQn = - 2, /**< 14 Cortex-M4 Pend SV Interrupt */
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SysTick_IRQn = - 1, /**< 15 Cortex-M4 System Tick Interrupt */
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/****** CC13x2 specific Interrupt Numbers *********************************/
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EDGE_DETECT_IRQN = 0, /**< 16 AON edge detect */
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I2C_IRQN = 1, /**< 17 I2C */
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RF_CPE1_IRQN = 2, /**< 18 RF Command and Packet Engine 1 */
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PKA_IRQN = 3, /**< 19 PKA interrupt */
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AON_RTC_IRQN = 4, /**< 20 AON RTC */
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UART0_IRQN = 5, /**< 21 UART0 Rx and Tx */
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AON_AUX_SWEV0_IRQN = 6, /**< 22 Sensor Controller software event 0, through AON domain*/
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SSI0_IRQN = 7, /**< 23 SSI0 Rx and Tx */
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SSI1_IRQN = 8, /**< 24 SSI1 Rx and Tx */
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RF_CPE0_IRQN = 9, /**< 25 RF Command and Packet Engine 0 */
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RF_HW_IRQN = 10, /**< 26 RF Core Hardware */
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RF_CMD_ACK_IRQN = 11, /**< 27 RF Core Command Acknowledge */
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I2S_IRQN = 12, /**< 28 I2S */
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AON_AUX_SWEV1_IRQN = 13, /**< 29 Sensor Controller software event 1, through AON domain*/
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WATCHDOG_IRQN = 14, /**< 30 Watchdog timer */
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GPTIMER_0A_IRQN = 15, /**< 31 Timer 0 subtimer A */
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GPTIMER_0B_IRQN = 16, /**< 32 Timer 0 subtimer B */
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GPTIMER_1A_IRQN = 17, /**< 33 Timer 1 subtimer A */
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GPTIMER_1B_IRQN = 18, /**< 34 Timer 1 subtimer B */
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GPTIMER_2A_IRQN = 19, /**< 35 Timer 2 subtimer A */
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GPTIMER_2B_IRQN = 20, /**< 36 Timer 2 subtimer B */
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GPTIMER_3A_IRQN = 21, /**< 37 Timer 3 subtimer A */
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GPTIMER_3B_IRQN = 22, /**< 38 Timer 3 subtimer B */
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CRYPTO_IRQN = 23, /**< 39 Crypto Core Result available */
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UDMA_IRQN = 24, /**< 40 uDMA Software */
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UDMA_ERR_IRQN = 25, /**< 41 uDMA Error */
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FLASH_CTRL_IRQN = 26, /**< 42 Flash controller */
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SW0_IRQN = 27, /**< 43 Software Event 0 */
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AUX_COMBO_IRQN = 28, /**< 44 AUX combined event, directly to MCU domain*/
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AON_PRG0_IRQN = 29, /**< 45 AON programmable 0 */
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PROG_IRQN = 30, /**< 46 Dynamic Programmable interrupt (default source: PRCM)*/
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AUX_COMPA_IRQN = 31, /**< 47 AUX Comparator A */
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AUX_ADC_IRQN = 32, /**< 48 AUX ADC IRQ */
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TRNG_IRQN = 33, /**< 49 TRNG event */
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#ifdef CPU_VARIANT_X2
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OSC_IRQN = 34, /**< 50 Combined event from oscillator control */
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AUX_TIMER2_IRQN = 35, /**< 51 AUX Timer 2 event 0 */
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UART1_IRQN = 36, /**< 52 UART1 combined interrupt */
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BATMON_IRQN = 37, /**< 53 UART1 combined interrupt */
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IRQN_COUNT = (BATMON_IRQN + 1) /**< Number of peripheral IDs */
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#else
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IRQN_COUNT = (TRNG_IRQN + 1) /**< Number of peripheral IDs */
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#endif
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} IRQn_Type;
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/**
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* @brief Configuration of the Cortex-M4 processor and core peripherals
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* @{
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*/
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#define __MPU_PRESENT 1 /**< CC13x2 does provide a MPU */
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#define __NVIC_PRIO_BITS 3 /**< CC13x2 offers priority levels from 0..7 */
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#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick config is used */
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/** @} */
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#define RCOSC48M_FREQ 48000000 /**< 48 MHz */
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#define RCOSC24M_FREQ 24000000 /**< 24 MHz */
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/**
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* @brief CMSIS includes
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*/
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#ifdef CPU_VARIANT_X2
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#include <core_cm4.h>
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#else
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#include <core_cm3.h>
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#endif
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/** @} */
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define FLASH_BASE 0x00000000 /**< FLASH base address */
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#define PERIPH_BASE 0x40000000 /**< Peripheral base address */
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#define PERIPH_BASE_NONBUF 0x60000000 /**< Peripheral base address (nonbuf) */
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#define ROM_HARD_API_BASE 0x10000048 /**< ROM Hard-API base address */
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#define ROM_API_TABLE ((uint32_t *) 0x10000180) /**< ROM API table */
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/** @} */
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/**
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* @brief ADI master instruction offsets
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* @{
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*/
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#define ADI_DIR 0x00000000
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#define ADI_SET 0x00000010
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#define ADI_CLR 0x00000020
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#define ADI_MASK4B 0x00000040
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#define ADI_MASK8B 0x00000060
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#define ADI_MASK16B 0x00000080
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CC26XX_CC13XX_H */
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/** @} */
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