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https://github.com/RIOT-OS/RIOT.git
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367 lines
12 KiB
C
367 lines
12 KiB
C
/*
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* Copyright (C) 2015 Eistec AB
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* 2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_mulle
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the Eistec Mulle
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/* The crystal on the Mulle is designed for 12.5 pF load capacitance. According
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* to the data sheet, the K60 will have a 5 pF parasitic capacitance on the
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* XTAL32/EXTAL32 connection. The board traces might give some minor parasitic
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* capacitance as well. */
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/* Use the equation
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* CL = (C1 * C2) / (C1 + C2) + Cstray
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* with C1 == C2:
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* C1 = 2 * (CL - Cstray)
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*/
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/* enable 14pF load capacitor which will yield a crystal load capacitance of 12 pF */
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#define RTC_LOAD_CAP_BITS (RTC_CR_SC8P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC2P_MASK)
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static const clock_config_t clock_config = {
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/*
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* This configuration results in the system running from the FLL output with
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* the following clock frequencies:
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* Core: 48 MHz
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* Bus: 48 MHz
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* Flex: 24 MHz
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* Flash: 24 MHz
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*/
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/* The board has a 16 MHz crystal, though it is not used in this configuration */
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/* This configuration uses the RTC crystal to provide the base clock, it
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* should have better accuracy than the internal slow clock, and lower power
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* consumption than using the 16 MHz crystal and the OSC0 module */
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.clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
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SIM_CLKDIV1_OUTDIV3(1) | SIM_CLKDIV1_OUTDIV4(1),
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.rtc_clc = RTC_LOAD_CAP_BITS,
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.osc32ksel = SIM_SOPT1_OSC32KSEL(2),
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.clock_flags =
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/* no OSC0_EN, the RTC module provides the clock input signal for the FLL */
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KINETIS_CLOCK_RTCOSC_EN |
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KINETIS_CLOCK_USE_FAST_IRC |
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0,
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.default_mode = KINETIS_MCG_MODE_FEE,
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.erc_range = KINETIS_MCG_ERC_RANGE_LOW, /* Input clock is 32768 Hz */
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/* 16 pF capacitors yield ca 10 pF load capacitance as required by the
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* onboard xtal, not used when OSC0 is disabled */
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.osc_clc = OSC_CR_SC16P_MASK,
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.oscsel = MCG_C7_OSCSEL(1), /* Use RTC for external clock */
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.fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
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.fll_frdiv = MCG_C1_FRDIV(0b000), /* Divide by 1 => FLL input 32768 Hz */
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.fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
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.fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
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/* PLL is unavailable when using a 32768 Hz source clock, so the
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* configuration below can only be used if the above config is modified to
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* use the 16 MHz crystal instead of the RTC. */
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.pll_prdiv = MCG_C5_PRDIV0(0b00111), /* Divide by 8 */
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.pll_vdiv = MCG_C6_VDIV0(0b01100), /* Multiply by 36 => PLL freq = 72 MHz */
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};
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#define CLOCK_CORECLOCK (48000000ul)
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#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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#define PIT_NUMOF (2U)
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#define PIT_CONFIG { \
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{ \
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.prescaler_ch = 0, \
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.count_ch = 1, \
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}, \
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{ \
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.prescaler_ch = 2, \
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.count_ch = 3, \
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}, \
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}
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#define LPTMR_NUMOF (1U)
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#define LPTMR_CONFIG { \
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{ \
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.dev = LPTMR0, \
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.irqn = LPTMR0_IRQn, \
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.src = 2, \
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.base_freq = 32768u, \
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} \
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}
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#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
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#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
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#define PIT_ISR_0 isr_pit1
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#define PIT_ISR_1 isr_pit3
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#define LPTMR_ISR_0 isr_lptmr0
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = UART0,
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.freq = CLOCK_CORECLOCK,
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.pin_rx = GPIO_PIN(PORT_A, 15),
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.pin_tx = GPIO_PIN(PORT_A, 14),
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.pcr_rx = PORT_PCR_MUX(3),
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.pcr_tx = PORT_PCR_MUX(3),
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.irqn = UART0_RX_TX_IRQn,
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.scgc_addr = &SIM->SCGC4,
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.scgc_bit = SIM_SCGC4_UART0_SHIFT,
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.mode = UART_MODE_8N1,
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.type = KINETIS_UART,
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},
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{
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.dev = UART1,
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.freq = CLOCK_CORECLOCK,
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.pin_rx = GPIO_PIN(PORT_C, 3),
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.pin_tx = GPIO_PIN(PORT_C, 4),
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.pcr_rx = PORT_PCR_MUX(3),
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.pcr_tx = PORT_PCR_MUX(3),
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.irqn = UART1_RX_TX_IRQn,
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.scgc_addr = &SIM->SCGC4,
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.scgc_bit = SIM_SCGC4_UART1_SHIFT,
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.mode = UART_MODE_8N1,
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.type = KINETIS_UART,
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},
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};
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#define UART_0_ISR (isr_uart0_rx_tx)
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#define UART_1_ISR (isr_uart1_rx_tx)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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static const adc_conf_t adc_config[] = {
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/* internal: temperature sensor */
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/* The temperature sensor has a very high output impedance, it must not be
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* sampled using hardware averaging, or the sampled values will be garbage */
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[ 0] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 26, .avg = ADC_AVG_NONE },
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/* internal: band gap */
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[ 1] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 27, .avg = ADC_AVG_MAX },
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/* internal: V_REFSH */
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[ 2] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 29, .avg = ADC_AVG_MAX },
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/* internal: V_REFSL */
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[ 3] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 30, .avg = ADC_AVG_MAX },
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/* internal: DAC0 module output level */
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[ 4] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 23, .avg = ADC_AVG_MAX },
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/* internal: VREF module output level */
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[ 5] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 18, .avg = ADC_AVG_MAX },
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/* on board connection to Mulle Vbat/2 on PGA1_DP pin */
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[ 6] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 0, .avg = ADC_AVG_MAX },
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/* on board connection to Mulle Vchr/2 on PGA1_DM pin */
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[ 7] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 19, .avg = ADC_AVG_MAX },
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/* expansion port PGA0_DP pin */
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[ 8] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 0, .avg = ADC_AVG_MAX },
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/* expansion port PGA0_DM pin */
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[ 9] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 19, .avg = ADC_AVG_MAX },
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/* expansion port PTA17 */
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[10] = { .dev = ADC1, .pin = GPIO_PIN(PORT_A, 17), .chan = 17, .avg = ADC_AVG_MAX },
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/* expansion port PTB0 */
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[11] = { .dev = ADC1, .pin = GPIO_PIN(PORT_B, 0), .chan = 8, .avg = ADC_AVG_MAX },
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/* expansion port PTC0 */
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[12] = { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 0), .chan = 14, .avg = ADC_AVG_MAX },
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/* expansion port PTC8 */
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[13] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 8), .chan = 4, .avg = ADC_AVG_MAX },
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/* expansion port PTC9 */
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[14] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 9), .chan = 5, .avg = ADC_AVG_MAX },
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/* expansion port PTC10 */
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[15] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 10), .chan = 6, .avg = ADC_AVG_MAX },
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/* expansion port PTC11 */
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[16] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 11), .chan = 7, .avg = ADC_AVG_MAX },
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};
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#define ADC_NUMOF ARRAY_SIZE(adc_config)
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/*
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* K60D ADC reference settings:
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* 0: VREFH/VREFL external pin pair
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* 1: VREF_OUT internal 1.2 V reference (VREF module must be enabled)
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* 2-3: reserved
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*/
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#define ADC_REF_SETTING 0
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/** @} */
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/**
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* @name DAC configuration
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* @{
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*/
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static const dac_conf_t dac_config[] = {
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{
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.dev = DAC0,
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.scgc_addr = &SIM->SCGC2,
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.scgc_bit = SIM_SCGC2_DAC0_SHIFT
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}
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};
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#define DAC_NUMOF ARRAY_SIZE(dac_config)
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.ftm = FTM0,
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.chan = {
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{ .pin = GPIO_PIN(PORT_C, 1), .af = 4, .ftm_chan = 0 },
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{ .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
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{ .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
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{ .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
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},
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.chan_numof = 2,
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.ftm_num = 0
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},
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{
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.ftm = FTM1,
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.chan = {
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{ .pin = GPIO_PIN(PORT_A, 12), .af = 3, .ftm_chan = 0 },
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{ .pin = GPIO_PIN(PORT_A, 13), .af = 3, .ftm_chan = 1 },
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{ .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
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{ .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
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},
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.chan_numof = 2,
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.ftm_num = 1
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}
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};
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#define PWM_NUMOF ARRAY_SIZE(pwm_config)
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/** @} */
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/**
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* @name SPI configuration
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*
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* Clock configuration values based on the configured 47988736Hz module clock.
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*
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* Auto-generated by:
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* cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
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*
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* @{
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*/
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static const uint32_t spi_clk_config[] = {
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(
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93728Hz */
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SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
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SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
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SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
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),
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(
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 374912Hz */
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SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
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SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
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SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
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),
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(
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SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 999765Hz */
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SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
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SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
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SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
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),
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(
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4798873Hz */
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SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
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SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
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SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
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),
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(
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SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 7998122Hz */
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SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
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SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
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SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
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)
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI0,
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.pin_miso = GPIO_PIN(PORT_D, 3),
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.pin_mosi = GPIO_PIN(PORT_D, 2),
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.pin_clk = GPIO_PIN(PORT_D, 1),
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.pin_cs = {
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GPIO_PIN(PORT_D, 0),
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GPIO_PIN(PORT_D, 4),
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GPIO_PIN(PORT_D, 5),
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GPIO_PIN(PORT_D, 6),
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SPI_CS_UNDEF,
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},
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.pcr = GPIO_AF_2,
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.simmask = SIM_SCGC6_SPI0_MASK
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},
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{
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.dev = SPI1,
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.pin_miso = GPIO_PIN(PORT_E, 3),
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.pin_mosi = GPIO_PIN(PORT_E, 1),
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.pin_clk = GPIO_PIN(PORT_E, 2),
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.pin_cs = {
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GPIO_PIN(PORT_E, 4),
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SPI_CS_UNDEF,
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SPI_CS_UNDEF,
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SPI_CS_UNDEF,
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SPI_CS_UNDEF,
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},
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.pcr = GPIO_AF_2,
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.simmask = SIM_SCGC6_SPI1_MASK
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}
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.i2c = I2C0,
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.scl_pin = GPIO_PIN(PORT_B, 2),
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.sda_pin = GPIO_PIN(PORT_B, 1),
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.freq = CLOCK_BUSCLOCK,
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.speed = I2C_SPEED_FAST,
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.irqn = I2C0_IRQn,
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.scl_pcr = (PORT_PCR_MUX(2) | PORT_PCR_ODE_MASK),
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.sda_pcr = (PORT_PCR_MUX(2) | PORT_PCR_ODE_MASK),
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},
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};
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#define I2C_NUMOF ARRAY_SIZE(i2c_config)
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#define I2C_0_ISR (isr_i2c0)
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#define I2C_1_ISR (isr_i2c1)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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