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165 lines
14 KiB
C
165 lines
14 KiB
C
/***************************************************************************//**
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* @file
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* @brief EFM32HG_IDAC register and bit field definitions
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*******************************************************************************
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* # License
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* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
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*******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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******************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(__ICCARM__)
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#pragma system_include /* Treat file as system include file. */
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang system_header /* Treat file as system include file. */
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#endif
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/***************************************************************************//**
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* @addtogroup Parts
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @defgroup EFM32HG_IDAC
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* @{
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* @brief EFM32HG_IDAC Register Declaration
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******************************************************************************/
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typedef struct {
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__IOM uint32_t CTRL; /**< Control Register */
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__IOM uint32_t CURPROG; /**< Current Programming Register */
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__IOM uint32_t CAL; /**< Calibration Register */
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__IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configauration Register */
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} IDAC_TypeDef; /**< IDAC Register Declaration *//** @} */
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/***************************************************************************//**
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* @defgroup EFM32HG_IDAC_BitFields
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* @{
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******************************************************************************/
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/* Bit fields for IDAC CTRL */
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#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */
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#define _IDAC_CTRL_MASK 0x0074001FUL /**< Mask for IDAC_CTRL */
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#define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */
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#define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */
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#define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */
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#define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
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#define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */
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#define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */
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#define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */
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#define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */
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#define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
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#define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */
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#define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */
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#define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */
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#define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */
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#define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
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#define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */
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#define IDAC_CTRL_OUTEN (0x1UL << 3) /**< Output Enable */
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#define _IDAC_CTRL_OUTEN_SHIFT 3 /**< Shift value for IDAC_OUTEN */
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#define _IDAC_CTRL_OUTEN_MASK 0x8UL /**< Bit mask for IDAC_OUTEN */
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#define _IDAC_CTRL_OUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
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#define IDAC_CTRL_OUTEN_DEFAULT (_IDAC_CTRL_OUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */
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#define IDAC_CTRL_OUTMODE (0x1UL << 4) /**< Output Modes */
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#define _IDAC_CTRL_OUTMODE_SHIFT 4 /**< Shift value for IDAC_OUTMODE */
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#define _IDAC_CTRL_OUTMODE_MASK 0x10UL /**< Bit mask for IDAC_OUTMODE */
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#define _IDAC_CTRL_OUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
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#define _IDAC_CTRL_OUTMODE_PIN 0x00000000UL /**< Mode PIN for IDAC_CTRL */
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#define _IDAC_CTRL_OUTMODE_ADC 0x00000001UL /**< Mode ADC for IDAC_CTRL */
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#define IDAC_CTRL_OUTMODE_DEFAULT (_IDAC_CTRL_OUTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */
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#define IDAC_CTRL_OUTMODE_PIN (_IDAC_CTRL_OUTMODE_PIN << 4) /**< Shifted mode PIN for IDAC_CTRL */
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#define IDAC_CTRL_OUTMODE_ADC (_IDAC_CTRL_OUTMODE_ADC << 4) /**< Shifted mode ADC for IDAC_CTRL */
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#define IDAC_CTRL_OUTENPRS (0x1UL << 18) /**< PRS Controlled Output Enable */
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#define _IDAC_CTRL_OUTENPRS_SHIFT 18 /**< Shift value for IDAC_OUTENPRS */
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#define _IDAC_CTRL_OUTENPRS_MASK 0x40000UL /**< Bit mask for IDAC_OUTENPRS */
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#define _IDAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
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#define IDAC_CTRL_OUTENPRS_DEFAULT (_IDAC_CTRL_OUTENPRS_DEFAULT << 18) /**< Shifted mode DEFAULT for IDAC_CTRL */
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#define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */
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#define _IDAC_CTRL_PRSSEL_MASK 0x700000UL /**< Bit mask for IDAC_PRSSEL */
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#define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
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#define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */
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#define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */
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#define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */
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#define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */
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#define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */
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#define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */
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#define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */
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#define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */
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#define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */
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#define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */
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#define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */
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#define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */
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#define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */
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/* Bit fields for IDAC CURPROG */
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#define _IDAC_CURPROG_RESETVALUE 0x00000000UL /**< Default value for IDAC_CURPROG */
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#define _IDAC_CURPROG_MASK 0x00001F03UL /**< Mask for IDAC_CURPROG */
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#define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */
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#define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */
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#define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
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#define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */
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#define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */
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#define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */
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#define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */
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#define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */
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#define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */
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#define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */
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#define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */
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#define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */
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#define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */
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#define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */
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#define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
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#define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */
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/* Bit fields for IDAC CAL */
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#define _IDAC_CAL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CAL */
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#define _IDAC_CAL_MASK 0x0000007FUL /**< Mask for IDAC_CAL */
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#define _IDAC_CAL_TUNING_SHIFT 0 /**< Shift value for IDAC_TUNING */
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#define _IDAC_CAL_TUNING_MASK 0x7FUL /**< Bit mask for IDAC_TUNING */
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#define _IDAC_CAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CAL */
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#define IDAC_CAL_TUNING_DEFAULT (_IDAC_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CAL */
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/* Bit fields for IDAC DUTYCONFIG */
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#define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */
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#define _IDAC_DUTYCONFIG_MASK 0x00000003UL /**< Mask for IDAC_DUTYCONFIG */
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#define IDAC_DUTYCONFIG_DUTYCYCLEEN (0x1UL << 0) /**< Duty Cycle Enable. */
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#define _IDAC_DUTYCONFIG_DUTYCYCLEEN_SHIFT 0 /**< Shift value for IDAC_DUTYCYCLEEN */
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#define _IDAC_DUTYCONFIG_DUTYCYCLEEN_MASK 0x1UL /**< Bit mask for IDAC_DUTYCYCLEEN */
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#define _IDAC_DUTYCONFIG_DUTYCYCLEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */
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#define IDAC_DUTYCONFIG_DUTYCYCLEEN_DEFAULT (_IDAC_DUTYCONFIG_DUTYCYCLEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
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#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< EM2/EM3 Duty Cycle Disable. */
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#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */
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#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */
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#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */
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#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
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/** @} End of group EFM32HG_IDAC */
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/** @} End of group Parts */
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#ifdef __cplusplus
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}
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#endif
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