mirror of
https://github.com/RIOT-OS/RIOT.git
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211 lines
6.4 KiB
C
211 lines
6.4 KiB
C
/*
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* Copyright (C) 2022 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_esp32
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* @{
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*
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* @file
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* @brief SDK configuration used by ESP-IDF for all ESP32x SoC variants (families)
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*
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* The SDK configuration can be partially overridden by application-specific
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* board configuration.
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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*/
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#ifndef SDKCONFIG_H
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#define SDKCONFIG_H
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/*
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* The SoC capability definitions are often included indirectly in the
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* ESP-IDF files, although all ESP-IDF files require them. Since not all
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* ESP-IDF header files are included in RIOT, the SoC capability definitions
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* are unknown if they are only indirectly included. Therefore, the SoC
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* capabilities are included in this file and are thus available to all
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* ESP-IDF files. This avoids to update vendor code.
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*/
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#include "soc/soc_caps.h"
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/**
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* @brief SDK version number
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*
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* Determined with `git describe --tags` in `$ESP32_SDK_DIR`
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*/
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#if !defined(IDF_VER)
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#include "esp_idf_ver.h"
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#endif
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#ifndef DOXYGEN
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/**
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* Default console configuration
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*
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* STDIO_UART_BAUDRATE is used as CONFIG_CONSOLE_UART_BAUDRATE and
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* can be overridden by an application specific configuration.
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*/
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#define CONFIG_CONSOLE_UART_NUM 0
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#define CONFIG_ESP_CONSOLE_UART_NUM CONFIG_CONSOLE_UART_NUM
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#ifndef CONFIG_CONSOLE_UART_BAUDRATE
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#define CONFIG_CONSOLE_UART_BAUDRATE STDIO_UART_BAUDRATE
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#endif
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/**
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* Log output configuration (DO NOT CHANGE)
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*/
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#ifndef CONFIG_LOG_DEFAULT_LEVEL
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#define CONFIG_LOG_DEFAULT_LEVEL LOG_LEVEL
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#endif
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#define CONFIG_LOG_MAXIMUM_LEVEL LOG_LEVEL
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/**
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* System specific configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_NEWLIB_NANO
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#define CONFIG_NEWLIB_NANO_FORMAT 1
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#endif
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#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1
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#define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32
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#define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2560
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#define CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER 1
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#define CONFIG_ESP_TIMER_TASK_STACK_SIZE 3584
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#define CONFIG_ESP_TIMER_INTERRUPT_LEVEL 1
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#define CONFIG_TIMER_TASK_STACK_SIZE CONFIG_ESP_TIMER_TASK_STACK_SIZE
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#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1
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#define CONFIG_APP_BUILD_GENERATE_BINARIES 1
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#define CONFIG_APP_BUILD_BOOTLOADER 1
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#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1
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#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv"
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#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv"
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#define CONFIG_PARTITION_TABLE_SINGLE_APP 1
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#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
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/**
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* Bluetooth configuration (DO NOT CHANGE)
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*/
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#define CONFIG_BT_ENABLED 0
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#define CONFIG_BT_RESERVE_DRAM 0
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/**
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* SPI RAM configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_ESP_SPI_RAM
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#define CONFIG_SPIRAM_TYPE_AUTO 1
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#define CONFIG_SPIRAM_SIZE -1
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#define CONFIG_SPIRAM_SPEED_40M 1
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#define CONFIG_SPIRAM 1
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#define CONFIG_SPIRAM_BOOT_INIT 1
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#define CONFIG_SPIRAM_USE_MALLOC 0 /* using malloc requires QStaticQueue */
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#define CONFIG_SPIRAM_MEMTEST 1
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#define CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL 16384
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#define CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL 32768
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#endif
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/**
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* SPI Flash driver configuration (DO NOT CHANGE)
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*/
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#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
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#define CONFIG_SPI_FLASH_USE_LEGACY_IMPL 1
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#define CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS 1
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#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1
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#define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20
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#define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1
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#define CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE 8192
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#define CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP 1
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#define CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP 1
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#define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1
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#define CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP 1
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/**
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* Ethernet driver configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_ESP_ETH
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#define CONFIG_ETH_ENABLED 1
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#endif
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/**
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* Serial flasher config (defined by CFLAGS, only sanity check here)
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*/
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#if !defined(CONFIG_FLASHMODE_DOUT) && \
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!defined(CONFIG_FLASHMODE_DIO) && \
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!defined(CONFIG_FLASHMODE_QOUT) && \
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!defined(CONFIG_FLASHMODE_QIO)
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#error "Flash mode not configured"
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#endif
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/**
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* Wi-Fi driver configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_ESP_WIFI_ANY
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#define CONFIG_ESP32_WIFI_ENABLED 1
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#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10
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#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32
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#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER 1
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#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 1
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#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32
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#define CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM 32 /* required when CONFIG_SPIRAM_USE_MALLOC=0 */
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#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1
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#define CONFIG_ESP32_WIFI_TX_BA_WIN 6
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#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1
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#define CONFIG_ESP32_WIFI_RX_BA_WIN 6
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#ifdef MODULE_ESP_IDF_NVS_ENABLED
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#define CONFIG_ESP32_WIFI_NVS_ENABLED 1
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#endif
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#define CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0 1
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#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN 752
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#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM 32
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#define CONFIG_ESP32_WIFI_IRAM_OPT 1
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#define CONFIG_ESP32_WIFI_RX_IRAM_OPT 1
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#define CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE 1
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#if defined(MODULE_ESP_WIFI_AP) || defined(MODULE_ESP_NOW)
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#define CONFIG_ESP_WIFI_SOFTAP_SUPPORT 1
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#endif
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#endif
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/**
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* PHY configuration
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*/
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#if MODULE_ESP_IDF_NVS_ENABLED
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#define CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE 1
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#endif
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#define CONFIG_ESP_PHY_MAX_TX_POWER 20
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#define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20
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#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE
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#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER CONFIG_ESP_PHY_MAX_WIFI_TX_POWER
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#endif /* DOXYGEN */
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/**
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* @brief Include ESP32x family specific SDK configuration
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*/
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#if defined(CPU_FAM_ESP32)
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#include "sdkconfig_esp32.h"
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#elif defined(CPU_FAM_ESP32C3)
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#include "sdkconfig_esp32c3.h"
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#else
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#error "ESP32x family implementation missing"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* SDKCONFIG_H */
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/** @} */
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