RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Code Releases Activity

cpu/esp32: move common ESP-IDF configurations to common file

Browse Source
This commit is contained in:
Gunar Schorcht 2022-08-01 17:42:14 +02:00
parent 8af4c9eb56
commit 70d427da0b
3 changed files with 236 additions and 276 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

150
cpu/esp32/include/sdkconfig.h
View File

@ -11,7 +11,7 @@
* @{
*
* @file
* @brief SDK configuration used by ESP-IDF for ESP32x SoCs
* @brief SDK configuration used by ESP-IDF for all ESP32x SoC variants (families)
*
* The SDK configuration can be partially overridden by application-specific
* board configuration.
@ -37,10 +37,156 @@
*
* Determined with `git describe --tags` in `$ESP32_SDK_DIR`
*/
#if !defined(IDF_VER) || DOXYGEN
#if !defined(IDF_VER)
#include "esp_idf_ver.h"
#endif
#ifndef DOXYGEN
/**
* Default console configuration
*
* STDIO_UART_BAUDRATE is used as CONFIG_CONSOLE_UART_BAUDRATE and
* can be overridden by an application specific configuration.
*/
#define CONFIG_CONSOLE_UART_NUM 0
#define CONFIG_ESP_CONSOLE_UART_NUM CONFIG_CONSOLE_UART_NUM
#ifndef CONFIG_CONSOLE_UART_BAUDRATE
#define CONFIG_CONSOLE_UART_BAUDRATE STDIO_UART_BAUDRATE
#endif
/**
* Log output configuration (DO NOT CHANGE)
*/
#ifndef CONFIG_LOG_DEFAULT_LEVEL
#define CONFIG_LOG_DEFAULT_LEVEL LOG_LEVEL
#endif
#define CONFIG_LOG_MAXIMUM_LEVEL LOG_LEVEL
/**
* System specific configuration (DO NOT CHANGE)
*/
#ifdef MODULE_NEWLIB_NANO
#define CONFIG_NEWLIB_NANO_FORMAT 1
#endif
#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1
#define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32
#define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2560
#define CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER 1
#define CONFIG_ESP_TIMER_TASK_STACK_SIZE 3584
#define CONFIG_ESP_TIMER_INTERRUPT_LEVEL 1
#define CONFIG_TIMER_TASK_STACK_SIZE CONFIG_ESP_TIMER_TASK_STACK_SIZE
#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1
#define CONFIG_APP_BUILD_GENERATE_BINARIES 1
#define CONFIG_APP_BUILD_BOOTLOADER 1
#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1
#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv"
#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv"
#define CONFIG_PARTITION_TABLE_SINGLE_APP 1
#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
/**
* Bluetooth configuration (DO NOT CHANGE)
*/
#define CONFIG_BT_ENABLED 0
#define CONFIG_BT_RESERVE_DRAM 0
/**
* SPI RAM configuration (DO NOT CHANGE)
*/
#ifdef MODULE_ESP_SPI_RAM
#define CONFIG_SPIRAM_TYPE_AUTO 1
#define CONFIG_SPIRAM_SIZE -1
#define CONFIG_SPIRAM_SPEED_40M 1
#define CONFIG_SPIRAM 1
#define CONFIG_SPIRAM_BOOT_INIT 1
#define CONFIG_SPIRAM_USE_MALLOC 0 /* using malloc requires QStaticQueue */
#define CONFIG_SPIRAM_MEMTEST 1
#define CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL 16384
#define CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL 32768
#endif
/**
* SPI Flash driver configuration (DO NOT CHANGE)
*/
#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
#define CONFIG_SPI_FLASH_USE_LEGACY_IMPL 1
#define CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS 1
#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1
#define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20
#define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1
#define CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE 8192
#define CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP 1
/**
* Ethernet driver configuration (DO NOT CHANGE)
*/
#ifdef MODULE_ESP_ETH
#define CONFIG_ETH_ENABLED 1
#endif
/**
* Serial flasher config (defined by CFLAGS, only sanity check here)
*/
#if !defined(CONFIG_FLASHMODE_DOUT) && \
!defined(CONFIG_FLASHMODE_DIO) && \
!defined(CONFIG_FLASHMODE_QOUT) && \
!defined(CONFIG_FLASHMODE_QIO)
#error "Flash mode not configured"
#endif
/**
* Wi-Fi driver configuration (DO NOT CHANGE)
*/
#ifdef MODULE_ESP_WIFI_ANY
#define CONFIG_ESP32_WIFI_ENABLED 1
#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10
#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32
#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER 1
#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 1
#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32
#define CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM 32 /* required when CONFIG_SPIRAM_USE_MALLOC=0 */
#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1
#define CONFIG_ESP32_WIFI_TX_BA_WIN 6
#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1
#define CONFIG_ESP32_WIFI_RX_BA_WIN 6
#ifdef MODULE_ESP_IDF_NVS_ENABLED
#define CONFIG_ESP32_WIFI_NVS_ENABLED 1
#endif
#define CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0 1
#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN 752
#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM 32
#define CONFIG_ESP32_WIFI_IRAM_OPT 1
#define CONFIG_ESP32_WIFI_RX_IRAM_OPT 1
#define CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE 1
#if defined(MODULE_ESP_WIFI_AP) || defined(MODULE_ESP_NOW)
#define CONFIG_ESP_WIFI_SOFTAP_SUPPORT 1
#endif
#endif
/**
* PHY configuration
*/
#if MODULE_ESP_IDF_NVS_ENABLED
#define CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE 1
#endif
#define CONFIG_ESP_PHY_MAX_TX_POWER 20
#define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20
#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE
#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER CONFIG_ESP_PHY_MAX_WIFI_TX_POWER
#endif /* DOXYGEN */
/**
* @brief Include ESP32x family specific SDK configuration
*/

207
cpu/esp32/include/sdkconfig_esp32.h
View File

@ -11,7 +11,7 @@
* @{
*
* @file
* @brief SDK configuration used by the ESP-IDF for ESP32
* @brief SDK configuration used by the ESP-IDF for ESP32 SoC variant (family)
*
* The SDK configuration can be partially overridden by application-specific
* board configuration.
@ -29,64 +29,95 @@ extern "C" {
#endif
/**
* @name Clock configuration
* @name ESP32 specific clock configuration
* @{
*/
/* Mapping of Kconfig defines to the respective enumeration values */
#if CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_2
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 2
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 2
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_5
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 5
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 5
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_10
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 10
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 10
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_20
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 20
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 20
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_40
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 40
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 40
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_80
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 80
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 80
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_160
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 160
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 160
#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_240
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 240
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 240
#endif
/**
* @brief Defines the CPU frequency [values = 2, 40, 80, 160 and 240]
* @brief Defines the CPU frequency [values = 2, 5, 10, 20, 40, 80, 160, 240]
*/
#ifndef CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 80
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 80
#endif
/**
* @brief Mapping configured ESP32 default clock to CLOCK_CORECLOCK define
* @brief Mapping configured ESP32 default clock to CLOCK_CORECLOCK define
*/
#define CLOCK_CORECLOCK (1000000UL * CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
/** @} */
/**
* Default console configuration
*
* STDIO_UART_BAUDRATE is used as CONFIG_CONSOLE_UART_BAUDRATE and
* can be overridden by an application specific configuration.
* ESP32 specific RTC clock configuration
*/
#define CONFIG_CONSOLE_UART_NUM 0
#define CONFIG_ESP_CONSOLE_UART_NUM CONFIG_CONSOLE_UART_NUM
#ifndef CONFIG_CONSOLE_UART_BAUDRATE
#define CONFIG_CONSOLE_UART_BAUDRATE STDIO_UART_BAUDRATE
#endif
#define CONFIG_ESP32_RTC_CLK_CAL_CYCLES (8 * 1024)
/**
* Log output configuration (DO NOT CHANGE)
* ESP32 specific EFUSE configuration
*/
#ifndef CONFIG_LOG_DEFAULT_LEVEL
#define CONFIG_LOG_DEFAULT_LEVEL LOG_LEVEL
#endif
#define CONFIG_LOG_MAXIMUM_LEVEL LOG_LEVEL
#define CONFIG_EFUSE_MAX_BLK_LEN 192
#define CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4 1
/**
* ESP32 specific configuration
* ESP32 specific MAC configuration
*/
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1
#define CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES 4
/**
* ESP32 specific system configuration (DO NOT CHANGE)
*/
#define CONFIG_ESP_TIMER_IMPL_FRC2 1
#define CONFIG_ESP_CONSOLE_MULTIPLE_UART 1
#define CONFIG_ESP32_DEBUG_OCDAWARE 1
#define CONFIG_ESP32_REV_MIN 0
#define CONFIG_ESP32_BROWNOUT_DET 1
#define CONFIG_ESP32_BROWNOUT_DET_LVL 0
#define CONFIG_BROWNOUT_DET CONFIG_ESP32_BROWNOUT_DET
#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000
#define CONFIG_ESP32_TRACEMEM_RESERVE_DRAM 0
#define CONFIG_ESP32_ULP_COPROC_RESERVE_MEM 0
/**
* ESP32 specific ADC calibration
*/
#define CONFIG_ADC_CAL_EFUSE_TP_ENABLE 1
#define CONFIG_ADC_CAL_EFUSE_VREF_ENABLE 1
#define CONFIG_ADC_CAL_LUT_ENABLE 1
/**
* ESP32 specific PHY configuration
*/
#define CONFIG_ESP_PHY_REDUCE_TX_POWER 1
#define CONFIG_ESP32_REDUCE_PHY_TX_POWER CONFIG_ESP_PHY_REDUCE_TX_POWER
#define CONFIG_REDUCE_PHY_TX_POWER CONFIG_ESP_PHY_REDUCE_TX_POWER
/**
* ESP32 specific XTAL configuration
*
* Main clock crystal frequency (MHz). Zero means to auto-configure.
* This is configured at the board level, defaulting to 40.
@ -99,81 +130,29 @@ extern "C" {
#define CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS 1
#endif
#define CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES 100
#define CONFIG_ESP32_RTC_CLK_CAL_CYCLES (8 * 1024)
/**
* System specific configuration (DO NOT CHANGE)
*/
#ifdef MODULE_NEWLIB_NANO
#define CONFIG_NEWLIB_NANO_FORMAT 1
#endif
#define CONFIG_TRACEMEM_RESERVE_DRAM 0
#define CONFIG_ULP_COPROC_RESERVE_MEM 0
#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1
#define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32
#define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2560
#define CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS 4
#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000
#define CONFIG_ESP_TIMER_INTERRUPT_LEVEL 1
#define CONFIG_ESP_TIMER_TASK_STACK_SIZE 3584
#define CONFIG_ESP_TIMER_IMPL_FRC2 1
#define CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER 1
#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1
#define CONFIG_EFUSE_MAX_BLK_LEN 192
#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
/**
* Bluetooth configuration (DO NOT CHANGE)
*/
#define CONFIG_BT_ENABLED 0
#define CONFIG_BT_RESERVE_DRAM 0
/**
* SPI RAM configuration (DO NOT CHANGE)
* ESP32 specific SPI RAM configuration
*/
#ifdef MODULE_ESP_SPI_RAM
#define CONFIG_SOC_SPIRAM_SUPPORTED 1
#define CONFIG_ESP32_SPIRAM_SUPPORT 1
#define CONFIG_D0WD_PSRAM_CLK_IO 17
#define CONFIG_D0WD_PSRAM_CS_IO 16
#define CONFIG_D2WD_PSRAM_CLK_IO 9
#define CONFIG_D2WD_PSRAM_CS_IO 10
#define CONFIG_PICO_PSRAM_CS_IO 10
#define CONFIG_SPIRAM_SUPPORT CONFIG_ESP32_SPIRAM_SUPPORT
#define CONFIG_SPIRAM 1
#define CONFIG_SPIRAM_BANKSWITCH_ENABLE 1
#define CONFIG_SPIRAM_BANKSWITCH_RESERVE 8
#define CONFIG_SPIRAM_BOOT_INIT 1
#define CONFIG_SPIRAM_CACHE_WORKAROUND 1
#define CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW 1
#define CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL 16384
#define CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL 32768
#define CONFIG_SPIRAM_MEMTEST 1
#define CONFIG_SPIRAM_SIZE -1
#define CONFIG_SPIRAM_SPEED_40M 1
#define CONFIG_SPIRAM_SPIWP_SD3_PIN 7
#define CONFIG_SPIRAM_TYPE_AUTO 1
#define CONFIG_SPIRAM_USE_MALLOC 0 /* using malloc requires QStaticQueue */
#define CONFIG_SPIRAM_SUPPORT CONFIG_ESP32_SPIRAM_SUPPORT
#endif
/**
* SPI Flash driver configuration (DO NOT CHANGE)
*/
#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
#define CONFIG_SPI_FLASH_USE_LEGACY_IMPL 1
/**
* Ethernet driver configuration (DO NOT CHANGE)
* ESP32 specific ETH configuration
*/
#ifdef MODULE_ESP_ETH
#define CONFIG_ETH_ENABLED 1
#endif
#define CONFIG_ETH_USE_ESP32_EMAC 1
#define CONFIG_ETH_PHY_INTERFACE_RMII 1
#define CONFIG_ETH_RMII_CLK_INPUT 1
@ -181,68 +160,8 @@ extern "C" {
#define CONFIG_ETH_DMA_BUFFER_SIZE 512
#define CONFIG_ETH_DMA_RX_BUFFER_NUM 10
#define CONFIG_ETH_DMA_TX_BUFFER_NUM 10
/**
* Serial flasher config (defined by CFLAGS, only sanity check here)
*/
#if !defined(CONFIG_FLASHMODE_DOUT) && \
!defined(CONFIG_FLASHMODE_DIO) && \
!defined(CONFIG_FLASHMODE_QOUT) && \
!defined(CONFIG_FLASHMODE_QIO)
#error "Flash mode not configured"
#endif
/**
* Wi-Fi driver configuration (DO NOT CHANGE)
*/
#ifdef MODULE_ESP_WIFI_ANY
#define CONFIG_ESP32_WIFI_ENABLED 1
#endif
#if defined(MODULE_ESP_WIFI_AP) || defined(MODULE_ESP_NOW)
#define CONFIG_ESP_WIFI_SOFTAP_SUPPORT 1
#endif
#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10
#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32
#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER 1
#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 1
#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32
#define CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM 32 /* required when CONFIG_SPIRAM_USE_MALLOC=0 */
#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1
#define CONFIG_ESP32_WIFI_TX_BA_WIN 6
#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1
#define CONFIG_ESP32_WIFI_RX_BA_WIN 6
#if MODULE_ESP_IDF_NVS_ENABLED
#define CONFIG_ESP32_WIFI_NVS_ENABLED 1
#endif
#define CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0 1
#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN 752
#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM 32
#define CONFIG_ESP32_WIFI_IRAM_OPT 1
#define CONFIG_ESP32_WIFI_RX_IRAM_OPT 1
#define CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE 1
/**
* PHY configuration
*/
#if MODULE_ESP_IDF_NVS_ENABLED
#define CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE 1
#endif
#define CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION 0
#define CONFIG_ESP_PHY_MAX_TX_POWER 20
#define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20
#define CONFIG_ESP_PHY_REDUCE_TX_POWER 1
#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE
#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER CONFIG_ESP_PHY_MAX_WIFI_TX_POWER
#define CONFIG_ESP32_REDUCE_PHY_TX_POWER CONFIG_ESP_PHY_REDUCE_TX_POWER
#define CONFIG_REDUCE_PHY_TX_POWER CONFIG_ESP_PHY_REDUCE_TX_POWER
/**
* EMAC driver configuration (DO NOT CHANGE)
*/
#define CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE 1
#ifdef __cplusplus
}
#endif

155
cpu/esp32/include/sdkconfig_esp32c3.h
View File

@ -11,7 +11,7 @@
* @{
*
* @file
* @brief SDK configuration used by the ESP-IDF for ESP32C3
* @brief SDK configuration used by the ESP-IDF for ESP32-C3 SoC variant (family)
*
* The SDK configuration can be partially overridden by application-specific
* board configuration.
@ -29,7 +29,7 @@ extern "C" {
#endif
/**
* @name Clock configuration
* @name ESP32-C3 specific clock configuration
* @{
*/
@ -51,158 +51,53 @@ extern "C" {
#endif
/**
* @brief Defines the CPU frequency [values = 2, 5, 10, 10, 40, 80, 160]
* @brief Defines the CPU frequency [values = 2, 5, 10, 20, 40, 80, 160]
*/
#ifndef CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ
#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 80
#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ 80
#endif
/**
* @brief Mapping configured ESP32 default clock to CLOCK_CORECLOCK define
* @brief Mapping configured ESP32-C3 default clock to CLOCK_CORECLOCK define
*/
#define CLOCK_CORECLOCK (1000000UL * CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ)
/** @} */
/**
* Default console configuration
*
* STDIO_UART_BAUDRATE is used as CONFIG_CONSOLE_UART_BAUDRATE and
* can be overridden by an application specific configuration.
* ESP32-C3 specific RTC clock configuration
*/
#define CONFIG_CONSOLE_UART_NUM 0
#define CONFIG_ESP_CONSOLE_UART_NUM CONFIG_CONSOLE_UART_NUM
#ifndef CONFIG_CONSOLE_UART_BAUDRATE
#define CONFIG_CONSOLE_UART_BAUDRATE STDIO_UART_BAUDRATE
#endif
/**
* Log output configuration (DO NOT CHANGE)
*/
#ifndef CONFIG_LOG_DEFAULT_LEVEL
#define CONFIG_LOG_DEFAULT_LEVEL LOG_LEVEL
#endif
#define CONFIG_LOG_MAXIMUM_LEVEL LOG_LEVEL
/**
* RTC clock configuration
*/
#ifdef MODULE_ESP_RTC_TIMER_32K
#define CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS 1
#endif
#define CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES (8 * 1024)
/**
* System specific configuration (DO NOT CHANGE)
* ESP32-C3 specific EFUSE configuration
*/
#ifdef MODULE_NEWLIB_NANO
#define CONFIG_NEWLIB_NANO_FORMAT 1
#endif
#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1
#define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32
#define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2560
#define CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER 1
#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1
#define CONFIG_ESP_TIMER_INTERRUPT_LEVEL 1
#define CONFIG_ESP_TIMER_TASK_STACK_SIZE 3584
#define CONFIG_TIMER_TASK_STACK_SIZE CONFIG_ESP_TIMER_TASK_STACK_SIZE
#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1
#define CONFIG_APP_BUILD_BOOTLOADER 1
#define CONFIG_APP_BUILD_GENERATE_BINARIES 1
#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1
#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1
#define CONFIG_EFUSE_MAX_BLK_LEN 256
#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv"
#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv"
#define CONFIG_PARTITION_TABLE_SINGLE_APP 1
/**
* Bluetooth configuration (DO NOT CHANGE)
* ESP32-C3 specific MAC configuration
*/
#define CONFIG_BT_ENABLED 0
#define CONFIG_BT_RESERVE_DRAM 0
/**
* SPI Flash driver configuration (DO NOT CHANGE)
*/
#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
#define CONFIG_SPI_FLASH_USE_LEGACY_IMPL 1
#define CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS 1
#define CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE 1
#define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20
#define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1
#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
#define CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP 1
#define CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE 8192
#define CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS
#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1
/**
* Serial flasher config (defined by CFLAGS, only sanity check here)
*/
#if !defined(CONFIG_FLASHMODE_DOUT) && \
!defined(CONFIG_FLASHMODE_DIO) && \
!defined(CONFIG_FLASHMODE_QOUT) && \
!defined(CONFIG_FLASHMODE_QIO)
#error "Flash mode not configured"
#endif
/**
* Wi-Fi driver configuration (DO NOT CHANGE)
*/
#ifdef MODULE_ESP_WIFI_ANY
#define CONFIG_ESP32_WIFI_ENABLED 1
#endif
#if defined(MODULE_ESP_WIFI_AP) || defined(MODULE_ESP_NOW)
#define CONFIG_ESP_WIFI_SOFTAP_SUPPORT 1
#endif
#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER CONFIG_ESP_PHY_MAX_WIFI_TX_POWER
#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1
#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1
#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32
#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER 1
#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32
#define CONFIG_ESP32_WIFI_ENABLED 1
#define CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE 1
#define CONFIG_ESP32_WIFI_IRAM_OPT 1
#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM 32
#if MODULE_ESP_IDF_NVS_ENABLED
#define CONFIG_ESP32_WIFI_NVS_ENABLED 1
#endif
#define CONFIG_ESP32_WIFI_RX_BA_WIN 6
#define CONFIG_ESP32_WIFI_RX_IRAM_OPT 1
#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN 752
#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10
#define CONFIG_ESP32_WIFI_TX_BA_WIN 6
#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
#define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1
#define CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES 4
/**
* PHY configuration
* ESP32-C3 specific system configuration (DO NOT CHANGE)
*/
#if MODULE_ESP_IDF_NVS_ENABLED
#define CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE 1
#endif
#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1
#define CONFIG_ESP_PHY_MAX_TX_POWER 20
#define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20
#define CONFIG_ESP32C3_DEBUG_OCDAWARE 1
#define CONFIG_ESP32C3_REV_MIN 3
#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE
#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER CONFIG_ESP_PHY_MAX_WIFI_TX_POWER
#define CONFIG_ESP32C3_BROWNOUT_DET 1
#define CONFIG_ESP32C3_BROWNOUT_DET_LVL 7
/**
* ESP32-C3 specific sleep configuration (DO NOT CHANGE)
*/
#define CONFIG_ESP_SLEEP_POWER_DOWN_FLASH 1
#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1
#ifdef __cplusplus
}