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https://github.com/RIOT-OS/RIOT.git
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a51d167a43
To simplify board definitions and for unification between samd2x and newer models, don't use the GCLK bitmask in board definitions. Instead use the GCLK index and generate the bitmask when needed.
266 lines
7.0 KiB
C
266 lines
7.0 KiB
C
/*
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* Copyright (C) 2018 HAW Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_sensebox_samd21
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* @{
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*
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* @file
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* @brief Configuration of CPU peripherals for SenseBox MCU with SAMD21
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*
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* @author Jose Alamos <jose.alamos@haw-hamburg.de>
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* @author Leandro Lanzieri <leandro.lanzieri@haw-hamburg.de>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include <stdint.h>
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#include "cpu.h"
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name External oscillator and clock configuration
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*
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* For selection of the used CORECLOCK, we have implemented two choices:
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*
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* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
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* - usage of the internal 8MHz oscillator directly, divided by N if needed
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*
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*
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* The PLL option allows for the usage of a wider frequency range and a more
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* stable clock with less jitter. This is why we use this option as default.
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*
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* The target frequency is computed from the PLL multiplier and the PLL divisor.
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* Use the following formula to compute your values:
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*
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* CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
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*
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* NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
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* frequency is 96MHz. So PLL_MULL must be between 31 and 95!
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*
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*
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* The internal Oscillator used directly can lead to a slightly better power
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* efficiency to the cost of a less stable clock. Use this option when you know
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* what you are doing! The actual core frequency is adjusted as follows:
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*
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* CORECLOCK = 8MHz / DIV
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*
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* NOTE: A core clock frequency below 1MHz is not recommended
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*
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* @{
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*/
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#define CLOCK_USE_PLL (1)
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#if CLOCK_USE_PLL
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/* edit these values to adjust the PLL output frequency */
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#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
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#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
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#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
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#else
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/* edit this value to your needs */
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#define CLOCK_DIV (1U)
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/* generate the actual core clock frequency */
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#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
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#endif
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/** @} */
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/**
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* @name Timer peripheral configuration
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* @{
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*/
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static const tc32_conf_t timer_config[] = {
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{ /* Timer 0 - System Clock */
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.dev = TC3,
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.irq = TC3_IRQn,
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.pm_mask = PM_APBCMASK_TC3,
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.gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
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#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
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.gclk_src = 1,
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.prescaler = TC_CTRLA_PRESCALER_DIV1,
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#else
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.gclk_src = 0,
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.prescaler = TC_CTRLA_PRESCALER_DIV8,
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#endif
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.flags = TC_CTRLA_MODE_COUNT16,
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},
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{ /* Timer 1 */
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.dev = TC4,
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.irq = TC4_IRQn,
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.pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
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.gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
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#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
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.gclk_src = 1,
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.prescaler = TC_CTRLA_PRESCALER_DIV1,
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#else
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.gclk_src = 0,
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.prescaler = TC_CTRLA_PRESCALER_DIV8,
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#endif
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.flags = TC_CTRLA_MODE_COUNT32,
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}
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};
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#define TIMER_0_MAX_VALUE 0xffff
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/* interrupt function name mapping */
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#define TIMER_0_ISR isr_tc3
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#define TIMER_1_ISR isr_tc4
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = &SERCOM3->USART,
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.rx_pin = GPIO_PIN(PA, 23),
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.tx_pin = GPIO_PIN(PA, 22),
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#ifdef MODULE_SAM0_PERIPH_UART_HW_FC
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.rts_pin = GPIO_UNDEF,
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.cts_pin = GPIO_UNDEF,
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#endif
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.mux = GPIO_MUX_C,
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.rx_pad = UART_PAD_RX_1,
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.tx_pad = UART_PAD_TX_0,
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.flags = UART_FLAG_NONE,
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.gclk_src = 0,
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},
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{
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.dev = &SERCOM4->USART,
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.rx_pin = GPIO_PIN(PB, 9),
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.tx_pin = GPIO_PIN(PB, 8),
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#ifdef MODULE_SAM0_PERIPH_UART_HW_FC
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.rts_pin = GPIO_UNDEF,
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.cts_pin = GPIO_UNDEF,
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#endif
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.mux = GPIO_MUX_D,
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.rx_pad = UART_PAD_RX_1,
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.tx_pad = UART_PAD_TX_0,
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.flags = UART_FLAG_NONE,
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.gclk_src = 0,
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}
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};
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/* interrupt function name mapping */
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#define UART_0_ISR isr_sercom3
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#define UART_1_ISR isr_sercom4
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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static const spi_conf_t spi_config[] = {
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{
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.dev = &SERCOM1->SPI,
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.miso_pin = GPIO_PIN(PA, 19),
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.mosi_pin = GPIO_PIN(PA, 16),
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.clk_pin = GPIO_PIN(PA, 17),
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.miso_mux = GPIO_MUX_C,
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.mosi_mux = GPIO_MUX_C,
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.clk_mux = GPIO_MUX_C,
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.miso_pad = SPI_PAD_MISO_3,
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.mosi_pad = SPI_PAD_MOSI_0_SCK_1,
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.gclk_src = 0
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}
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.dev = &(SERCOM0->I2CM),
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PA, 8),
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.sda_pin = GPIO_PIN(PA, 9),
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.mux = GPIO_MUX_C,
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.gclk_src = 0,
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.flags = I2C_FLAG_NONE
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},
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{
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.dev = &(SERCOM2->I2CM),
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PA, 12),
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.sda_pin = GPIO_PIN(PA, 13),
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.mux = GPIO_MUX_C,
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.gclk_src = 0,
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.flags = I2C_FLAG_NONE
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}
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};
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#define I2C_NUMOF ARRAY_SIZE(i2c_config)
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/**
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* @name RTC configuration
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* @{
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*/
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#define RTC_DEV RTC->MODE2
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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/* ADC Default values */
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#define ADC_PRESCALER ADC_CTRLB_PRESCALER_DIV512
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#define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
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#define ADC_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
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#define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
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/* Digital pins (1 to 6) on the board can be configured as analog inputs */
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static const adc_conf_chan_t adc_channels[] = {
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/* port, pin, muxpos */
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{ GPIO_PIN(PA, 4), ADC_INPUTCTRL_MUXPOS_PIN4 }, /* Digital 1 */
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{ GPIO_PIN(PA, 5), ADC_INPUTCTRL_MUXPOS_PIN5 }, /* Digital 2 */
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{ GPIO_PIN(PA, 6), ADC_INPUTCTRL_MUXPOS_PIN6 }, /* Digital 3 */
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{ GPIO_PIN(PA, 7), ADC_INPUTCTRL_MUXPOS_PIN7 }, /* Digital 4 */
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{ GPIO_PIN(PA, 3), ADC_INPUTCTRL_MUXPOS_PIN1 }, /* Digital 5 */
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{ GPIO_PIN(PA, 2), ADC_INPUTCTRL_MUXPOS_PIN0 }, /* Digital 6 */
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};
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#define ADC_NUMOF ARRAY_SIZE(adc_channels)
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/** @} */
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/**
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* @name USB peripheral configuration
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* @{
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*/
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static const sam0_common_usb_config_t sam_usbdev_config[] = {
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{
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.dm = GPIO_PIN(PA, 24),
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.dp = GPIO_PIN(PA, 25),
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.d_mux = GPIO_MUX_G,
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.device = &USB->DEVICE,
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}
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};
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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