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https://github.com/RIOT-OS/RIOT.git
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a51d167a43
To simplify board definitions and for unification between samd2x and newer models, don't use the GCLK bitmask in board definitions. Instead use the GCLK index and generate the bitmask when needed.
81 lines
1.8 KiB
C
81 lines
1.8 KiB
C
/*
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* Copyright (C) 2016 Kees Bakker, SODAQ
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_sodaq-autonomo
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* @{
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*
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* @file
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* @brief Default timer configuration for SODAQ boards
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*
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* @author Kees Bakker <kees@sodaq.com>
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*/
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#ifndef CFG_TIMER_DEFAULT_H
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#define CFG_TIMER_DEFAULT_H
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#include <stdint.h>
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#include "cpu.h"
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Timer peripheral configuration
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* @{
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*/
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static const tc32_conf_t timer_config[] = {
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{ /* Timer 0 - System Clock */
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.dev = TC3,
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.irq = TC3_IRQn,
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.pm_mask = PM_APBCMASK_TC3,
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.gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
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#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
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.gclk_src = 1,
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.prescaler = TC_CTRLA_PRESCALER_DIV1,
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#else
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.gclk_src = 0,
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.prescaler = TC_CTRLA_PRESCALER_DIV8,
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#endif
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.flags = TC_CTRLA_MODE_COUNT16,
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},
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{ /* Timer 1 */
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.dev = TC4,
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.irq = TC4_IRQn,
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.pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
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.gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
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#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
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.gclk_src = 1,
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.prescaler = TC_CTRLA_PRESCALER_DIV1,
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#else
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.gclk_src = 0,
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.prescaler = TC_CTRLA_PRESCALER_DIV8,
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#endif
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.flags = TC_CTRLA_MODE_COUNT32,
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}
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};
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#define TIMER_0_MAX_VALUE 0xffff
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/* interrupt function name mapping */
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#define TIMER_0_ISR isr_tc3
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#define TIMER_1_ISR isr_tc4
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CFG_TIMER_DEFAULT_H */
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/** @} */
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