mirror of
https://github.com/RIOT-OS/RIOT.git
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151 lines
3.9 KiB
C
151 lines
3.9 KiB
C
/*
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* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
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* 2015 FreshTemp, LLC.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_saml21
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* @{
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*
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* @file cpu.c
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* @brief Implementation of the CPU initialization for Atmel SAML21 MCUs
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*
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @}
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*/
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#include "cpu.h"
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#include "periph/init.h"
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#include "periph_conf.h"
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#include "stdio_base.h"
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static void _gclk_setup(int gclk, uint32_t reg)
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{
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GCLK->GENCTRL[gclk].reg = reg;
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while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(gclk)) {}
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}
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static void _osc32k_setup(void)
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{
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#if INTERNAL_OSC32_SOURCE
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uint32_t * pCalibrationArea;
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uint32_t osc32kcal;
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/* Read OSC32KCAL, calibration data for OSC32 !!! */
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pCalibrationArea = (uint32_t*) NVMCTRL_OTP5;
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osc32kcal = ( (*pCalibrationArea) & 0x1FC0 ) >> 6;
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/* RTC use Low Power Internal Oscillator at 32kHz */
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OSC32KCTRL->OSC32K.reg = OSC32KCTRL_OSC32K_RUNSTDBY
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| OSC32KCTRL_OSC32K_EN32K
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| OSC32KCTRL_OSC32K_CALIB(osc32kcal)
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| OSC32KCTRL_OSC32K_ENABLE;
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/* Wait OSC32K Ready */
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while (!OSC32KCTRL->STATUS.bit.OSC32KRDY) {}
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#endif /* INTERNAL_OSC32_SOURCE */
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}
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static void _xosc32k_setup(void)
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{
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#if EXTERNAL_OSC32_SOURCE
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/* RTC uses External 32,768KHz Oscillator */
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OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_XTALEN
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| OSC32KCTRL_XOSC32K_RUNSTDBY
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| OSC32KCTRL_XOSC32K_EN32K
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| OSC32KCTRL_XOSC32K_ENABLE;
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/* Wait XOSC32K Ready */
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while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) {}
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#endif
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}
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void sam0_gclk_enable(uint8_t id)
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{
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(void) id;
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/* clocks are always running */
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}
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uint32_t sam0_gclk_freq(uint8_t id)
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{
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switch (id) {
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case SAM0_GCLK_MAIN:
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return CLOCK_CORECLOCK;
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case SAM0_GCLK_32KHZ:
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return 32768;
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default:
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return 0;
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}
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}
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/**
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* @brief Initialize the CPU, set IRQ priorities, clocks
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*/
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void cpu_init(void)
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{
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/* disable the watchdog timer */
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WDT->CTRLA.bit.ENABLE = 0;
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/* initialize the Cortex-M core */
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cortexm_init();
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/* turn on only needed APB peripherals */
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MCLK->APBAMASK.reg =
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MCLK_APBAMASK_PM
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|MCLK_APBAMASK_MCLK
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|MCLK_APBAMASK_RSTC
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|MCLK_APBAMASK_OSCCTRL
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|MCLK_APBAMASK_OSC32KCTRL
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|MCLK_APBAMASK_SUPC
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|MCLK_APBAMASK_GCLK
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|MCLK_APBAMASK_WDT
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|MCLK_APBAMASK_RTC
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|MCLK_APBAMASK_EIC
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|MCLK_APBAMASK_PORT
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//|MCLK_APBAMASK_TAL
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;
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/* Software reset the GCLK module to ensure it is re-initialized correctly */
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GCLK->CTRLA.reg = GCLK_CTRLA_SWRST;
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while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {}
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while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {}
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PM->PLCFG.reg = PM_PLCFG_PLSEL_PL2;
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while (!PM->INTFLAG.bit.PLRDY) {}
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/* set OSC16M to 16MHz */
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OSCCTRL->OSC16MCTRL.bit.FSEL = 3;
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OSCCTRL->OSC16MCTRL.bit.ONDEMAND = 0;
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OSCCTRL->OSC16MCTRL.bit.RUNSTDBY = 0;
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_osc32k_setup();
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_xosc32k_setup();
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/* Setup GCLK generators */
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_gclk_setup(SAM0_GCLK_MAIN, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M);
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#if EXTERNAL_OSC32_SOURCE
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_gclk_setup(SAM0_GCLK_32KHZ, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K);
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#else
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_gclk_setup(SAM0_GCLK_32KHZ, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSCULP32K);
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#endif
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#ifdef MODULE_PERIPH_PM
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PM->CTRLA.reg = PM_CTRLA_MASK & (~PM_CTRLA_IORET);
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/* disable brownout detection
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* (Caused unexplicable reboots from sleep on saml21. /KS)
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*/
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SUPC->BOD33.bit.ENABLE=0;
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#endif
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/* initialize stdio prior to periph_init() to allow use of DEBUG() there */
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stdio_init();
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/* trigger static peripheral initialization */
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periph_init();
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}
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