Marian Buschsieweke 8b1c43afb0 cpu/gd32v: Allow configuration of SWJ_CFG ... Expose the compile time configuration knob `CONFIG_AFIO_PCF0_SWJ_CFG` to allow freeing some/all JTAG pins and use them as GPIOs. As default, PB4 is remapped from NJTRST to be usable as regular GPIO. This still allows using the JTAG interface for debugging/flashing, but makes an GPIO exposed by some boards available.		2024-01-19 23:17:35 +01:00
..
include	cpu/gd32v: Allow configuration of SWJ_CFG	2024-01-19 23:17:35 +01:00
periph	cpu/gd32v: Fix periph_pwm	2024-01-17 21:58:56 +01:00
clock.c	cpu/gd32v: allow reconfig PLL multiplier in clock config	2023-04-18 06:20:14 +02:00
cpu.c	cpu/gd32v: Allow configuration of SWJ_CFG	2024-01-19 23:17:35 +01:00
doc.txt	cpu/gd32v: Initial include of the GD32VF103 device	2021-08-24 14:30:23 +02:00
gd32v.config	cpu/gdv32: add pm_layered support	2023-01-24 00:52:02 +01:00
Kconfig	cpu/gd32v: add periph_usbdev support	2023-04-16 23:24:23 +02:00
Makefile	cpu/gd32v: Initial include of the GD32VF103 device	2021-08-24 14:30:23 +02:00
Makefile.default	cpu/gdv32: add pm_layered support	2023-01-24 00:52:02 +01:00
Makefile.dep	cpu/gd32v: add periph_usbdev support	2023-04-16 23:24:23 +02:00
Makefile.features	Merge #17045 #19243	2023-02-07 17:39:20 +00:00
Makefile.include	sys/riotboot: common default NUM_SLOT, SLOT_* config	2023-04-18 06:20:14 +02:00