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cpu/gd32v: Allow configuration of SWJ_CFG

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Expose the compile time configuration knob `CONFIG_AFIO_PCF0_SWJ_CFG`
to allow freeing some/all JTAG pins and use them as GPIOs.

As default, PB4 is remapped from NJTRST to be usable as regular GPIO.
This still allows using the JTAG interface for debugging/flashing,
but makes an GPIO exposed by some boards available.
This commit is contained in:
Marian Buschsieweke 2024-01-18 21:16:42 +01:00
parent 3b5ed6d390
commit 8b1c43afb0
No known key found for this signature in database
GPG Key ID: 77AA882EC78084E6
2 changed files with 37 additions and 0 deletions
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9
cpu/gd32v/cpu.c
View File

@ -33,6 +33,15 @@ void cpu_init(void)
periph_clk_en(APB1, RCU_APB1EN_PMUEN_Msk);
/* Common RISC-V initialization */
riscv_init();
/* Apply configured SWJ_CFG, unless it is configured to the reset value */
if (CONFIG_AFIO_PCF0_SWJ_CFG != SWJ_CFG_FULL_JTAG) {
/* The remapping periph clock must first be enabled */
RCU->APB2EN |= RCU_APB2EN_AFEN_Msk;
/* Then the remap can occur */
AFIO->PCF0 |= CONFIG_AFIO_PCF0_SWJ_CFG;
}
early_init();
periph_init();
}

28
cpu/gd32v/include/cpu_conf.h
View File

@ -46,6 +46,34 @@ extern "C" {
#define CPU_FLASH_BASE 0x08000000
/** @} */
/**
* @brief Possible values of the `SWJ_CFG` field in the AFIO->PCF0 register
*/
typedef enum {
/**
* @brief Full JTAG interface (reset value)
*/
SWJ_CFG_FULL_JTAG = 0,
/**
* @brief JTAG enabled, but NJTRST disabled and pin PB4 usable as GPIO
*/
SWJ_CFG_NO_NJTRST = 1U << AFIO_PCF0_SWJ_CFG_Pos,
/**
* @brief JTAG disabled, all debug pins usable as GPIOs
*/
SWJ_CFG_NO_JTAG = 4U << AFIO_PCF0_SWJ_CFG_Pos,
} afio_pcf0_swj_cfg_t;
#ifndef CONFIG_AFIO_PCF0_SWJ_CFG
/**
* @brief By default, enable JTAG but disable NJTRST
*
* This default makes PB4 usable as GPIO while still being able to debug and
* flash via JTAG.
*/
#define CONFIG_AFIO_PCF0_SWJ_CFG SWJ_CFG_NO_NJTRST
#endif
#ifdef __cplusplus
}
#endif