diff --git a/cpu/gd32v/cpu.c b/cpu/gd32v/cpu.c
index 81ce057c8c..f27d9166d1 100644
--- a/cpu/gd32v/cpu.c
+++ b/cpu/gd32v/cpu.c
@@ -33,6 +33,15 @@ void cpu_init(void)
     periph_clk_en(APB1, RCU_APB1EN_PMUEN_Msk);
     /* Common RISC-V initialization */
     riscv_init();
+
+    /* Apply configured SWJ_CFG, unless it is configured to the reset value */
+    if (CONFIG_AFIO_PCF0_SWJ_CFG != SWJ_CFG_FULL_JTAG) {
+        /* The remapping periph clock must first be enabled */
+        RCU->APB2EN |= RCU_APB2EN_AFEN_Msk;
+        /* Then the remap can occur */
+        AFIO->PCF0 |= CONFIG_AFIO_PCF0_SWJ_CFG;
+    }
+
     early_init();
     periph_init();
 }
diff --git a/cpu/gd32v/include/cpu_conf.h b/cpu/gd32v/include/cpu_conf.h
index eab6b59b9f..97e3f95413 100644
--- a/cpu/gd32v/include/cpu_conf.h
+++ b/cpu/gd32v/include/cpu_conf.h
@@ -46,6 +46,34 @@ extern "C" {
 #define CPU_FLASH_BASE                  0x08000000
 /** @} */
 
+/**
+ * @brief   Possible values of the `SWJ_CFG` field in the AFIO->PCF0 register
+ */
+typedef enum {
+     /**
+      * @brief  Full JTAG interface (reset value)
+      */
+    SWJ_CFG_FULL_JTAG    = 0,
+    /**
+     * @brief   JTAG enabled, but NJTRST disabled and pin PB4 usable as GPIO
+     */
+    SWJ_CFG_NO_NJTRST   = 1U << AFIO_PCF0_SWJ_CFG_Pos,
+    /**
+     * @brief   JTAG disabled, all debug pins usable as GPIOs
+     */
+    SWJ_CFG_NO_JTAG     = 4U << AFIO_PCF0_SWJ_CFG_Pos,
+} afio_pcf0_swj_cfg_t;
+
+#ifndef CONFIG_AFIO_PCF0_SWJ_CFG
+/**
+ * @brief   By default, enable JTAG but disable NJTRST
+ *
+ * This default makes PB4 usable as GPIO while still being able to debug and
+ * flash via JTAG.
+ */
+#define CONFIG_AFIO_PCF0_SWJ_CFG    SWJ_CFG_NO_NJTRST
+#endif
+
 #ifdef __cplusplus
 }
 #endif