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https://github.com/RIOT-OS/RIOT.git
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287 lines
9.5 KiB
C
287 lines
9.5 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_samd21
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* @{
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*
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* @file
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* @brief Implementation of the CPU initialization
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @}
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*/
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#include "cpu.h"
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#include "kernel_init.h"
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#include "periph_conf.h"
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#include "periph/init.h"
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#include "stdio_base.h"
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#ifndef CLOCK_8MHZ
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#define CLOCK_8MHZ 1
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#endif
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#ifndef GEN2_ULP32K
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#define GEN2_ULP32K 1
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#endif
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#ifndef GEN3_ULP32K
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#define GEN3_ULP32K GEN2_ULP32K
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#endif
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#ifndef XOSC32_STARTUP_TIME
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/**
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* @brief XOSC32 start up time
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*
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* @note Override this value in your boards periph_conf.h file
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* if a different start up time is to be used.
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*/
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#define XOSC32_STARTUP_TIME 6
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#endif
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#ifndef VDD
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/**
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* @brief Set system voltage level in mV (determines flash wait states)
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*
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* @note Override this value in your boards periph_conf.h file
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* if a different system voltage is used.
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*/
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#define VDD (3300U)
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#endif
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/* determine the needed flash wait states based on the system voltage (Vdd)
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* see SAMD21 datasheet Rev A (2017) table 37-40 , page 816 */
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#if (VDD > 2700)
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#define WAITSTATES ((CLOCK_CORECLOCK - 1) / 24000000)
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#else
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#define WAITSTATES ((CLOCK_CORECLOCK - 1) / 14000000)
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#endif
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#ifndef GCLK_GENCTRL_SRC_FDPLL
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#define GCLK_GENCTRL_SRC_FDPLL_Val _U_(0x8)
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#define GCLK_GENCTRL_SRC_FDPLL (GCLK_GENCTRL_SRC_FDPLL_Val << GCLK_GENCTRL_SRC_Pos)
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#endif
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#ifndef GCLK_CLKCTRL_ID_DFLL48
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#define GCLK_CLKCTRL_ID_DFLL48 GCLK_CLKCTRL_ID_DFLL48M
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#endif
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void sam0_gclk_enable(uint8_t id)
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{
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(void) id;
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/* clocks are always running */
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}
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uint32_t sam0_gclk_freq(uint8_t id)
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{
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switch (id) {
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case SAM0_GCLK_MAIN:
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return CLOCK_CORECLOCK;
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case SAM0_GCLK_1MHZ:
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return 1000000;
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case SAM0_GCLK_32KHZ:
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return 32768;
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case SAM0_GCLK_1KHZ:
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return 1024;
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default:
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return 0;
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}
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}
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void cpu_pm_cb_enter(int deep)
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{
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(void) deep;
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/* will be called before entering sleep */
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}
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void cpu_pm_cb_leave(int deep)
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{
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(void) deep;
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/* will be called after wake-up */
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}
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/**
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* @brief Configure clock sources and the cpu frequency
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*/
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static void clk_init(void)
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{
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/* enable clocks for the power, sysctrl and gclk modules */
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PM->APBAMASK.reg = (PM_APBAMASK_PM | PM_APBAMASK_SYSCTRL |
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PM_APBAMASK_GCLK);
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/* adjust NVM wait states */
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PM->APBBMASK.reg |= PM_APBBMASK_NVMCTRL;
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NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_RWS(WAITSTATES)
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#ifdef CPU_SAMD20
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/* errata: In Standby, Idle1 and Idle2 Sleep modes,
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the device might not wake up from sleep. */
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| NVMCTRL_CTRLB_SLEEPPRM_DISABLED
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#endif
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/* errata: Default value of MANW in NVM.CTRLB is 0. */
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| NVMCTRL_CTRLB_MANW;
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PM->APBBMASK.reg &= ~PM_APBBMASK_NVMCTRL;
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#if CLOCK_8MHZ
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/* configure internal 8MHz oscillator to run without prescaler */
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SYSCTRL->OSC8M.reg &= ~(SYSCTRL_OSC8M_PRESC_Msk);
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SYSCTRL->OSC8M.reg |= (SYSCTRL_OSC8M_ONDEMAND | SYSCTRL_OSC8M_ENABLE);
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while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY)) {}
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#endif
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#if CLOCK_USE_XOSC32_DFLL || !GEN2_ULP32K || !GEN3_ULP32K
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/* Use External 32.768KHz Oscillator */
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SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_EN32K |
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SYSCTRL_XOSC32K_XTALEN |
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SYSCTRL_XOSC32K_STARTUP(XOSC32_STARTUP_TIME) |
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SYSCTRL_XOSC32K_RUNSTDBY;
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/* Enable XOSC32 with Separate Call */
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SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
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#endif
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/* reset the GCLK module so it is in a known state */
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GCLK->CTRL.reg = GCLK_CTRL_SWRST;
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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/* Setup GCLK2 with divider 1 (32.768kHz) */
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GCLK->GENDIV.reg = (GCLK_GENDIV_ID(SAM0_GCLK_32KHZ) | GCLK_GENDIV_DIV(0));
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(SAM0_GCLK_32KHZ) | GCLK_GENCTRL_GENEN
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| GCLK_GENCTRL_RUNSTDBY
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#if GEN2_ULP32K
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| GCLK_GENCTRL_SRC_OSCULP32K);
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#else
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| GCLK_GENCTRL_SRC_XOSC32K);
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#endif
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#if CLOCK_USE_PLL
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/* setup generic clock 1 to feed DPLL with 1MHz */
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GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(8) |
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GCLK_GENDIV_ID(SAM0_GCLK_1MHZ));
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |
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GCLK_GENCTRL_SRC_OSC8M |
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GCLK_GENCTRL_ID(SAM0_GCLK_1MHZ));
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GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_GEN(SAM0_GCLK_1MHZ) |
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GCLK_CLKCTRL_ID_FDPLL |
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GCLK_CLKCTRL_CLKEN);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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/* enable PLL */
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SYSCTRL->DPLLRATIO.reg = (SYSCTRL_DPLLRATIO_LDR(CLOCK_PLL_MUL));
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SYSCTRL->DPLLCTRLB.reg = (SYSCTRL_DPLLCTRLB_REFCLK_GCLK);
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SYSCTRL->DPLLCTRLA.reg = (SYSCTRL_DPLLCTRLA_ENABLE);
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while(!(SYSCTRL->DPLLSTATUS.reg &
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(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK))) {}
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/* select the PLL as source for clock generator 0 (CPU core clock) */
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GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(CLOCK_PLL_DIV) |
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GCLK_GENDIV_ID(SAM0_GCLK_MAIN));
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |
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GCLK_GENCTRL_SRC_FDPLL |
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GCLK_GENCTRL_ID(SAM0_GCLK_MAIN));
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#elif CLOCK_USE_XOSC32_DFLL
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/* setup generic clock 1 as 1MHz for timer.c */
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GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(8) |
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GCLK_GENDIV_ID(SAM0_GCLK_1MHZ));
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |
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GCLK_GENCTRL_SRC_OSC8M |
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GCLK_GENCTRL_ID(SAM0_GCLK_1MHZ));
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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/* set GCLK2 as source for DFLL */
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GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_GEN(SAM0_GCLK_32KHZ) |
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GCLK_CLKCTRL_ID_DFLL48 |
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GCLK_CLKCTRL_CLKEN);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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/* Disable ONDEMAND mode while writing configurations */
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SYSCTRL->DFLLCTRL.reg &= ~(SYSCTRL_DFLLCTRL_ONDEMAND);
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while ((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0) {
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/* Wait for DFLL sync */
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}
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/* get the coarse and fine values stored in NVM (Section 9.3) */
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uint32_t coarse = (*(uint32_t *)(0x806024) >> 26); /* Bits 63:58 */
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uint32_t fine = (*(uint32_t *)(0x806028) & 0x3FF); /* Bits 73:64 */
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SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP(coarse >> 1) |
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SYSCTRL_DFLLMUL_FSTEP(fine >> 1) |
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SYSCTRL_DFLLMUL_MUL(CLOCK_CORECLOCK / CLOCK_XOSC32K);
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SYSCTRL->DFLLVAL.reg = SYSCTRL_DFLLVAL_COARSE(coarse) |
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SYSCTRL_DFLLVAL_FINE(fine);
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_MODE;
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while ((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0) {
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/* Wait for DFLL sync */
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}
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SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE;
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uint32_t mask = SYSCTRL_PCLKSR_DFLLRDY |
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SYSCTRL_PCLKSR_DFLLLCKF |
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SYSCTRL_PCLKSR_DFLLLCKC;
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while ((SYSCTRL->PCLKSR.reg & mask) != mask) { } /* Wait for DFLL lock */
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/* select the DFLL as source for clock generator 0 (CPU core clock) */
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GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(1U) | GCLK_GENDIV_ID(SAM0_GCLK_MAIN));
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN
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| GCLK_GENCTRL_SRC_DFLL48M
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| GCLK_GENCTRL_ID(SAM0_GCLK_MAIN);
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
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| GCLK_CLKCTRL_ID_DFLL48
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| GCLK_CLKCTRL_GEN(SAM0_GCLK_MAIN);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ONDEMAND;
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while ((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0) {
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/* Wait for DFLL sync */
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}
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#else /* do not use PLL, use internal 8MHz oscillator directly */
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GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(CLOCK_DIV) |
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GCLK_GENDIV_ID(SAM0_GCLK_MAIN));
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |
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GCLK_GENCTRL_SRC_OSC8M |
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GCLK_GENCTRL_ID(SAM0_GCLK_MAIN));
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#endif
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/* make sure we synchronize clock generator 0 before we go on */
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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/* Setup GCLK3 with divider 32 (1024 Hz) */
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GCLK->GENDIV.reg = (GCLK_GENDIV_ID(SAM0_GCLK_1KHZ) | GCLK_GENDIV_DIV(4));
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(SAM0_GCLK_1KHZ) | GCLK_GENCTRL_GENEN
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| GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_DIVSEL
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#if GEN3_ULP32K
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| GCLK_GENCTRL_SRC_OSCULP32K);
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#else
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| GCLK_GENCTRL_SRC_XOSC32K);
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#endif
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/* redirect all peripherals to a disabled clock generator (7) by default */
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for (unsigned i = 0x3; i <= GCLK_CLKCTRL_ID_Msk; i++) {
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(i) | GCLK_CLKCTRL_GEN(SAM0_GCLK_DISABLED);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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}
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}
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void cpu_init(void)
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{
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/* disable the watchdog timer */
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WDT->CTRL.reg = 0;
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/* initialize the Cortex-M core */
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cortexm_init();
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/* Initialise clock sources and generic clocks */
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clk_init();
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#ifdef MODULE_PERIPH_DMA
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/* initialize DMA streams */
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dma_init();
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#endif
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/* initialize stdio prior to periph_init() to allow use of DEBUG() there */
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early_init();
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/* trigger static peripheral initialization */
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periph_init();
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}
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