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72d0b2b180
It turns out that the legacy GPIO API and GPIO LL may disagree on what the GPIO base address is: GPIO LL will use the IOBUS as base address no matter what, the legacy GPIO API will use the APB as base address unless `periph_gpio_fast_read` is used. If the APIs disagree, we need to do impedance matching.
207 lines
5.1 KiB
C
207 lines
5.1 KiB
C
/*
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* Copyright (C) 2016 Freie Universität Berlin
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* 2017 OTA keys S.A.
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* 2023 Otto-von-Guericke-Universität Magdeburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam0_common
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* @ingroup drivers_periph_gpio_ll
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* @{
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*
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* @file
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* @brief CPU specific part of the Peripheral GPIO Low-Level API
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*
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* @author Marian Buschsieweke <marian.buschsieweke@posteo.net>
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*/
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#ifndef GPIO_LL_ARCH_H
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#define GPIO_LL_ARCH_H
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#include "architecture.h"
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef DOXYGEN /* hide implementation specific details from Doxygen */
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/* Provide base address of the GPIO peripheral via APB */
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#if defined(PORT_SEC)
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# define GPIO_APB_BASE PORT_SEC
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#else
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# define GPIO_APB_BASE PORT
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#endif
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/* Provide base address of the GPIO peripheral via IOBUS */
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#if defined(PORT_IOBUS_SEC)
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# define GPIO_IOBUS_BASE PORT_IOBUS_SEC
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#elif defined(PORT_IOBUS)
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# define GPIO_IOBUS_BASE PORT_IOBUS
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#else
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# define GPIO_IOBUS_BASE GPIO_APB_BASE /* no IOBUS present, fall back to APB */
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#endif
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#define GPIO_PORT_NUMBERING_ALPHABETIC 1
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#if PORT_GROUPS >= 1
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# define GPIO_PORT_0 ((uintptr_t)&GPIO_IOBUS_BASE->Group[0])
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#endif
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#if PORT_GROUPS >= 2
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# define GPIO_PORT_1 ((uintptr_t)&GPIO_IOBUS_BASE->Group[1])
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#endif
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#if PORT_GROUPS >= 3
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# define GPIO_PORT_2 ((uintptr_t)&GPIO_IOBUS_BASE->Group[2])
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#endif
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#if PORT_GROUPS >= 4
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# define GPIO_PORT_3 ((uintptr_t)&GPIO_IOBUS_BASE->Group[3])
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#endif
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#if PORT_GROUPS >= 5
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# define GPIO_PORT_4 ((uintptr_t)&GPIO_IOBUS_BASE->Group[4])
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#endif
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#if PORT_GROUPS >= 5
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# define GPIO_PORT_4 ((uintptr_t)&GPIO_IOBUS_BASE->Group[4])
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#endif
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#if PORT_GROUPS >= 6
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# define GPIO_PORT_5 ((uintptr_t)&GPIO_IOBUS_BASE->Group[5])
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#endif
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#if PORT_GROUPS >= 7
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# define GPIO_PORT_6 ((uintptr_t)&GPIO_IOBUS_BASE->Group[6])
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#endif
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#if PORT_GROUPS >= 8
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# define GPIO_PORT_7 ((uintptr_t)&GPIO_IOBUS_BASE->Group[7])
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#endif
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/**
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* @brief Get a GPIO port by number
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*/
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#define GPIO_PORT(num) ((uintptr_t)&GPIO_IOBUS_BASE->Group[(num)])
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/**
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* @brief Get a GPIO port number by gpio_port_t value
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*/
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#define GPIO_PORT_NUM(port) \
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(((port) - (uintptr_t)&GPIO_IOBUS_BASE->Group[0]) / sizeof(GPIO_IOBUS_BASE->Group[0]))
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static inline gpio_port_t gpio_port(uword_t num)
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{
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return (uintptr_t)&GPIO_IOBUS_BASE->Group[num];
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}
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static inline uword_t gpio_port_num(gpio_port_t port)
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{
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return (port - (uintptr_t)&GPIO_IOBUS_BASE->Group[0]) / sizeof(GPIO_IOBUS_BASE->Group[0]);
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}
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static inline PortGroup *sam0_gpio_iobus2ap(PortGroup *iobus)
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{
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const uintptr_t iobus_base = (uintptr_t)GPIO_IOBUS_BASE;
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const uintptr_t apb_base = (uintptr_t)GPIO_APB_BASE;
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return (PortGroup *)((uintptr_t)iobus - (iobus_base - apb_base));
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}
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static inline uword_t gpio_ll_read(gpio_port_t port)
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{
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PortGroup *p = (PortGroup *)port;
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if (!IS_USED(MODULE_PERIPH_GPIO_FAST_READ)) {
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p = sam0_gpio_iobus2ap(p);
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}
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return p->IN.reg;
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}
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static inline uword_t gpio_ll_read_output(gpio_port_t port)
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{
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PortGroup *p = (PortGroup *)port;
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return p->OUT.reg;
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}
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static inline void gpio_ll_set(gpio_port_t port, uword_t mask)
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{
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PortGroup *p = (PortGroup *)port;
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p->OUTSET.reg = mask;
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}
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static inline void gpio_ll_clear(gpio_port_t port, uword_t mask)
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{
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PortGroup *p = (PortGroup *)port;
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p->OUTCLR.reg = mask;
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}
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static inline void gpio_ll_toggle(gpio_port_t port, uword_t mask)
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{
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PortGroup *p = (PortGroup *)port;
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p->OUTTGL.reg = mask;
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}
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static inline void gpio_ll_write(gpio_port_t port, uword_t mask)
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{
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PortGroup *p = (PortGroup *)port;
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p->OUT.reg = mask;
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}
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static inline void gpio_ll_switch_dir_output(gpio_port_t port, uword_t outputs)
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{
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PortGroup *p = (PortGroup *)port;
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p->DIRSET.reg = outputs;
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}
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static inline void gpio_ll_switch_dir_input(gpio_port_t port, uword_t inputs)
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{
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PortGroup *p = (PortGroup *)port;
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p->DIRCLR.reg = inputs;
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}
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static inline gpio_port_t gpio_get_port(gpio_t pin)
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{
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/* GPIO LL and legacy GPIO API may disagree on what is the GPIO base
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* address if one is using the IOBUS and the other is using the APB for
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* access. In this case, we need to do impedance matching by adding the
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* offset. */
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const uintptr_t gpio_ll_base = GPIO_PORT_0;
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const uintptr_t gpio_legacy_base = GPIO_PIN(0, 0) & ~(0x1f);
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uintptr_t addr = (pin & ~(0x1f));
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return addr + (gpio_ll_base - gpio_legacy_base);
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}
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static inline uint8_t gpio_get_pin_num(gpio_t pin)
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{
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return pin & 0x1f;
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}
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static inline gpio_port_t gpio_port_pack_addr(void *addr)
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{
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return (gpio_port_t)addr;
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}
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static inline void * gpio_port_unpack_addr(gpio_port_t port)
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{
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if (port < GPIO_PORT(0)) {
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return (void *)port;
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}
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if (port > GPIO_PORT(ARRAY_SIZE(GPIO_IOBUS_BASE->Group))) {
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return (void *)port;
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}
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return NULL;
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}
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static inline bool is_gpio_port_num_valid(uint_fast8_t num)
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{
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return (num < ARRAY_SIZE(GPIO_IOBUS_BASE->Group));
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}
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#endif /* DOXYGEN */
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_LL_ARCH_H */
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/** @} */
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