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106 lines
3.5 KiB
C
106 lines
3.5 KiB
C
/*
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* Copyright (C) 2021 Otto-von-Guericke Universität Magdeburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_rpx0xx
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* @{
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*
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* @file
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* @brief Implementation of the CPU initialization
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*
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* @author Fabian Hüßler <fabian.huessler@ovgu.de>
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*
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* @}
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*/
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#include "cpu.h"
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#include "kernel_init.h"
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#include "macros/units.h"
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#include "periph/init.h"
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#include "periph_cpu.h"
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#include "io_reg.h"
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#include "stdio_base.h"
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#include "vendor/RP2040.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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static void _cpu_reset(void)
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{
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/* 2.14 subsystem resets */
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uint32_t rst;
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/* Reset hardware components except for critical ones */
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rst = RESETS_RESET_MASK
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& ~(RESETS_RESET_usbctrl_Msk
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| RESETS_RESET_syscfg_Msk
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| RESETS_RESET_pll_usb_Msk
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| RESETS_RESET_pll_sys_Msk
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| RESETS_RESET_pads_qspi_Msk
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| RESETS_RESET_pads_bank0_Msk
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| RESETS_RESET_io_qspi_Msk);
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periph_reset(rst);
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/* Assert that reset has completed except for those components which
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are not clocked by clk_ref or clk_sys */
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rst = RESETS_RESET_MASK
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& ~(RESETS_RESET_usbctrl_Msk
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| RESETS_RESET_uart1_Msk
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| RESETS_RESET_uart0_Msk
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| RESETS_RESET_spi1_Msk
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| RESETS_RESET_spi0_Msk
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| RESETS_RESET_rtc_Msk
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| RESETS_RESET_adc_Msk);
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periph_reset_done(rst);
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/* power the reference clock from its default source: the ROSC */
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clock_ref_configure_source(MHZ(12), MHZ(12), CLOCKS_CLK_REF_CTRL_SRC_rosc_clksrc_ph);
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/* power the system clock from its default source: the reference clock */
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clock_sys_configure_source(MHZ(12), MHZ(12), CLOCKS_CLK_SYS_CTRL_SRC_clk_ref);
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/* start XOSC, typically running at 12 MHz */
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xosc_start(CLOCK_XOSC);
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/* reset system PLL */
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pll_reset_sys();
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/* start the system PLL (typically takes the 12 MHz XOSC to generate 125 MHz) */
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pll_start_sys(PLL_SYS_REF_DIV, PLL_SYS_VCO_FEEDBACK_SCALE, PLL_SYS_POSTDIV1, PLL_SYS_POSTDIV2);
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/* configure reference clock to run from XOSC (typically 12 MHz) */
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clock_ref_configure_source(CLOCK_XOSC, CLOCK_XOSC,
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CLOCKS_CLK_REF_CTRL_SRC_xosc_clksrc);
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/* configure system clock output */
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clock_sys_configure_aux_source(CLOCK_CORECLOCK, CLOCK_CORECLOCK,
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CLOCKS_CLK_SYS_CTRL_AUXSRC_clksrc_pll_sys);
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/* configure the peripheral clock to run from the system clock */
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clock_periph_configure(CLOCK_PERIPH_SOURCE);
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if (IS_USED(ENABLE_DEBUG)) {
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/* check clk_ref with logic analyzer */
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clock_gpout0_configure(CLOCK_XOSC, CLOCK_XOSC,
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CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clk_ref);
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}
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/* Configure USB PLL to deliver 48MHz needed by ADC */
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if (IS_USED(MODULE_PERIPH_ADC)) {
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pll_start_usb(PLL_USB_REF_DIV, PLL_USB_VCO_FEEDBACK_SCALE,
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PLL_USB_POSTDIV1, PLL_USB_POSTDIV2);
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clock_adc_configure(CLOCKS_CLK_ADC_CTRL_AUXSRC_clksrc_pll_usb);
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}
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}
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void cpu_init(void)
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{
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/* initialize the Cortex-M core */
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cortexm_init();
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_cpu_reset();
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/* initialize stdio prior to periph_init() to allow use of DEBUG() there */
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early_init();
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DEBUG_PUTS("[rpx0xx] GPOUT0 (GPIO pin 21) is clocked from XOSC (typically 12 MHz)");
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/* trigger static peripheral initialization */
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periph_init();
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}
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