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https://github.com/RIOT-OS/RIOT.git
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cpu/rpx0xx: initialize USB PLL and ADC clock
Signed-off-by: Dylan Laduranty <dylan.laduranty@mesotic.com>
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parent
80e3f57205
commit
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@ -177,3 +177,17 @@ void clock_gpout3_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT3_CTR
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io_reg_atomic_set(&PADS_BANK0->GPIO25, 1U << PADS_BANK0_GPIO25_IE_Pos);
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gpio_set_function_select(25, FUNCTION_SELECT_CLOCK);
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}
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void clock_adc_configure(CLOCKS_CLK_ADC_CTRL_AUXSRC_Enum aux)
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{
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/* Stop the clock generator */
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io_reg_atomic_clear(&CLOCKS->CLK_ADC_CTRL,
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(1u << CLOCKS_CLK_ADC_CTRL_ENABLE_Pos));
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/* Selects the new auxiliary clock source */
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io_reg_write_dont_corrupt(&CLOCKS->CLK_ADC_CTRL,
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aux << CLOCKS_CLK_ADC_CTRL_AUXSRC_Pos,
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CLOCKS_CLK_ADC_CTRL_AUXSRC_Msk);
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/* Restart the clock generator */
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io_reg_atomic_set(&CLOCKS->CLK_ADC_CTRL,
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(1u << CLOCKS_CLK_ADC_CTRL_ENABLE_Pos));
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}
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@ -41,6 +41,7 @@ static void _cpu_reset(void)
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| RESETS_RESET_pll_usb_Msk
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| RESETS_RESET_pll_sys_Msk
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| RESETS_RESET_pads_qspi_Msk
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| RESETS_RESET_pads_bank0_Msk
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| RESETS_RESET_io_qspi_Msk);
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periph_reset(rst);
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/* Assert that reset has completed except for those components which
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@ -78,6 +79,13 @@ static void _cpu_reset(void)
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clock_gpout0_configure(CLOCK_XOSC, CLOCK_XOSC,
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CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clk_ref);
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}
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/* Configure USB PLL to deliver 48MHz needed by ADC */
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if (IS_USED(MODULE_PERIPH_ADC)) {
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pll_start_usb(PLL_USB_REF_DIV, PLL_USB_VCO_FEEDBACK_SCALE,
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PLL_USB_POSTDIV1, PLL_USB_POSTDIV2);
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clock_adc_configure(CLOCKS_CLK_ADC_CTRL_AUXSRC_clksrc_pll_usb);
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}
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}
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void cpu_init(void)
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@ -613,6 +613,13 @@ void clock_gpout2_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT2_CTR
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*/
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void clock_gpout3_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_Enum aux);
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/**
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* @brief Configure the ADC clock to run from a dedicated auxiliary
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* clock source
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*
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* @param aux Auxiliary clock source
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*/
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void clock_adc_configure(CLOCKS_CLK_ADC_CTRL_AUXSRC_Enum aux);
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/** @} */
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/**
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