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66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/*
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* Copyright (C) 2021 Mesotic SAS
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup cpu_nrf9160 Nordic nRF9160 MCU
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* @ingroup cpu
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* @brief Nordic nRF9160 family of CPUs
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* @{
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*
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* @file
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* @brief nRF9160 specific CPU configuration
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*
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* @author Dylan Laduranty <dylan.laduranty@mesotic.com>
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*
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*/
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#include "vendor/nrf9160.h"
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#include "vendor/nrf9160_bitfields.h"
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#include "vendor/nrf9160_peripherals.h"
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#include "cpu_conf_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name ARM Cortex-M specific CPU configuration
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* @{
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U) /**< Default ARM IRQ priority */
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#define CPU_FLASH_BASE (0x00000000) /**< ROM Base Address */
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#define CPU_IRQ_NUMOF (65U) /**< nRF9160 specific IRQ count */
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/** @} */
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/**
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* @name Flash page configuration
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* @{
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*/
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#define FLASHPAGE_SIZE (4096U) /**< Size of a page in bytes */
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#define FLASHPAGE_NUMOF (256U) /**< Total number of flash pages */
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/* The minimum block size which can be written is 4B. However, the erase
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* block is always FLASHPAGE_SIZE.
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*/
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#define FLASHPAGE_WRITE_BLOCK_SIZE (4U) /**< Minimum block size */
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/* Writing should be always 4 bytes aligned */
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#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U) /**< Mandatory alignment */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_H */
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/** @} */
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