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cpu/nrf9160: add flashpage configuration

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This commit is contained in:
Dylan Laduranty 2021-11-17 11:13:38 +01:00
parent b734622944
commit cc440bc296
2 changed files with 17 additions and 2 deletions
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4
cpu/nrf5x_common/Makefile.features
View File

@ -1,12 +1,12 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_pagewise
FEATURES_PROVIDED += periph_gpio periph_gpio_irq
FEATURES_PROVIDED += periph_timer_periodic
FEATURES_PROVIDED += periph_uart_modecfg
ifneq (nrf9160,$(CPU_MODEL))
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_pagewise
FEATURES_PROVIDED += periph_hwrng
FEATURES_PROVIDED += periph_rtt_overflow
FEATURES_PROVIDED += periph_temperature

15
cpu/nrf9160/include/cpu_conf.h
View File

@ -42,6 +42,21 @@ extern "C" {
#define CPU_IRQ_NUMOF (65U) /**< nRF9160 specific IRQ count */
/** @} */
/**
* @name Flash page configuration
* @{
*/
#define FLASHPAGE_SIZE (4096U) /**< Size of a page in bytes */
#define FLASHPAGE_NUMOF (256U) /**< Total number of flash pages */
/* The minimum block size which can be written is 4B. However, the erase
* block is always FLASHPAGE_SIZE.
*/
#define FLASHPAGE_WRITE_BLOCK_SIZE (4U) /**< Minimum block size */
/* Writing should be always 4 bytes aligned */
#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U) /**< Mandatory alignment */
/** @} */
#ifdef __cplusplus
}
#endif