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8b1c43afb0
Expose the compile time configuration knob `CONFIG_AFIO_PCF0_SWJ_CFG` to allow freeing some/all JTAG pins and use them as GPIOs. As default, PB4 is remapped from NJTRST to be usable as regular GPIO. This still allows using the JTAG interface for debugging/flashing, but makes an GPIO exposed by some boards available.
48 lines
1.2 KiB
C
48 lines
1.2 KiB
C
/*
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* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_gd32v
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* @{
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*
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* @file
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* @brief GD32V CPU initialization
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*
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* @author Koen Zandberg <koen@bergzand.net>
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*/
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#include "kernel_init.h"
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#include "stdio_uart.h"
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#include "periph/init.h"
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#include "irq_arch.h"
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#include "periph_cpu.h"
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#include "periph_conf.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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extern void __libc_init_array(void);
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void cpu_init(void)
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{
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gd32vf103_clock_init();
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/* enable PMU required for pm_layered */
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periph_clk_en(APB1, RCU_APB1EN_PMUEN_Msk);
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/* Common RISC-V initialization */
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riscv_init();
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/* Apply configured SWJ_CFG, unless it is configured to the reset value */
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if (CONFIG_AFIO_PCF0_SWJ_CFG != SWJ_CFG_FULL_JTAG) {
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/* The remapping periph clock must first be enabled */
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RCU->APB2EN |= RCU_APB2EN_AFEN_Msk;
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/* Then the remap can occur */
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AFIO->PCF0 |= CONFIG_AFIO_PCF0_SWJ_CFG;
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}
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early_init();
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periph_init();
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}
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