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258 lines
24 KiB
C
258 lines
24 KiB
C
/**************************************************************************//**
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* @file
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* @brief EFR32ZG23 ICACHE register and bit field definitions
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******************************************************************************
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* # License
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* <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b>
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******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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*****************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef EFR32ZG23_ICACHE_H
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#define EFR32ZG23_ICACHE_H
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#define ICACHE_HAS_SET_CLEAR
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/**************************************************************************//**
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* @addtogroup Parts
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* @{
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******************************************************************************/
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/**************************************************************************//**
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* @defgroup EFR32ZG23_ICACHE ICACHE
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* @{
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* @brief EFR32ZG23 ICACHE Register Declaration.
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*****************************************************************************/
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/** ICACHE Register Declaration. */
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typedef struct {
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__IM uint32_t IPVERSION; /**< IP Version */
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__IOM uint32_t CTRL; /**< Control Register */
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__IM uint32_t PCHITS; /**< Performance Counter Hits */
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__IM uint32_t PCMISSES; /**< Performance Counter Misses */
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__IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */
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__IM uint32_t STATUS; /**< Status Register */
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__IOM uint32_t CMD; /**< Command Register */
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__IOM uint32_t LPMODE; /**< Low Power Mode */
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__IOM uint32_t IF; /**< Interrupt Flag */
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__IOM uint32_t IEN; /**< Interrupt Enable */
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uint32_t RESERVED0[1014U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_SET; /**< IP Version */
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__IOM uint32_t CTRL_SET; /**< Control Register */
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__IM uint32_t PCHITS_SET; /**< Performance Counter Hits */
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__IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */
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__IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */
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__IM uint32_t STATUS_SET; /**< Status Register */
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__IOM uint32_t CMD_SET; /**< Command Register */
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__IOM uint32_t LPMODE_SET; /**< Low Power Mode */
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__IOM uint32_t IF_SET; /**< Interrupt Flag */
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__IOM uint32_t IEN_SET; /**< Interrupt Enable */
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uint32_t RESERVED1[1014U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_CLR; /**< IP Version */
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__IOM uint32_t CTRL_CLR; /**< Control Register */
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__IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */
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__IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */
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__IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */
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__IM uint32_t STATUS_CLR; /**< Status Register */
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__IOM uint32_t CMD_CLR; /**< Command Register */
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__IOM uint32_t LPMODE_CLR; /**< Low Power Mode */
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__IOM uint32_t IF_CLR; /**< Interrupt Flag */
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__IOM uint32_t IEN_CLR; /**< Interrupt Enable */
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uint32_t RESERVED2[1014U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_TGL; /**< IP Version */
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__IOM uint32_t CTRL_TGL; /**< Control Register */
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__IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */
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__IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */
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__IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */
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__IM uint32_t STATUS_TGL; /**< Status Register */
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__IOM uint32_t CMD_TGL; /**< Command Register */
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__IOM uint32_t LPMODE_TGL; /**< Low Power Mode */
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__IOM uint32_t IF_TGL; /**< Interrupt Flag */
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__IOM uint32_t IEN_TGL; /**< Interrupt Enable */
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} ICACHE_TypeDef;
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/** @} End of group EFR32ZG23_ICACHE */
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/**************************************************************************//**
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* @addtogroup EFR32ZG23_ICACHE
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* @{
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* @defgroup EFR32ZG23_ICACHE_BitFields ICACHE Bit Fields
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* @{
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*****************************************************************************/
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/* Bit fields for ICACHE IPVERSION */
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#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */
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#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */
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#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */
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#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */
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#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */
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#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */
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/* Bit fields for ICACHE CTRL */
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#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */
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#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */
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#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */
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#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */
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#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */
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#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */
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#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */
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#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */
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#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */
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#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */
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#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */
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#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */
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#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */
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#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */
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#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */
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#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */
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#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */
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/* Bit fields for ICACHE PCHITS */
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#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */
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#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */
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#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */
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#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */
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#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */
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#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */
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/* Bit fields for ICACHE PCMISSES */
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#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */
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#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */
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#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */
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#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */
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#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */
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#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */
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/* Bit fields for ICACHE PCAHITS */
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#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */
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#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */
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#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */
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#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */
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#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */
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#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */
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/* Bit fields for ICACHE STATUS */
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#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */
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#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */
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#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */
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#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */
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#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */
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#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */
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#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */
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/* Bit fields for ICACHE CMD */
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#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */
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#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */
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#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */
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#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */
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#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */
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#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */
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#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */
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#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */
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#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */
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#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */
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#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */
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#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */
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#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */
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#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */
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#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */
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#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */
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#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */
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/* Bit fields for ICACHE LPMODE */
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#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */
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#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */
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#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */
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#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */
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#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */
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#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */
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#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */
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#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */
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#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */
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#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */
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#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */
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#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */
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#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */
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#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */
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#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */
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#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */
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/* Bit fields for ICACHE IF */
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#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */
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#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */
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#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */
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#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */
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#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */
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#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */
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#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */
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#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */
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#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */
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#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */
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#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */
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#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */
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#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */
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#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */
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#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */
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#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */
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#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */
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#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */
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#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */
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#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */
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#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */
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#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */
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/* Bit fields for ICACHE IEN */
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#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */
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#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */
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#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */
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#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */
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#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */
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#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */
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#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */
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#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */
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#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */
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#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */
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#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */
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#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */
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#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */
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#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */
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#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */
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#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */
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#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */
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#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */
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#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */
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#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */
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#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */
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#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */
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/** @} End of group EFR32ZG23_ICACHE_BitFields */
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/** @} End of group EFR32ZG23_ICACHE */
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/** @} End of group Parts */
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#endif /* EFR32ZG23_ICACHE_H */
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#ifdef __cplusplus
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}
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#endif
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