mirror of
https://github.com/RIOT-OS/RIOT.git
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390 lines
14 KiB
C
390 lines
14 KiB
C
/*
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* Copyright (C) 2016 Leon George
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc26x2_cc13x2_definitions
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* @{
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*
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* @file
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* @brief CC26x2, CC13x2 PRCM register definitions
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*/
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#ifndef CC26X2_CC13X2_PRCM_H
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#define CC26X2_CC13X2_PRCM_H
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#include <cc26xx_cc13xx.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief DDI_0_OSC registers
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*/
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typedef struct {
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reg32_t CTL0; /**< Control 0 */
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reg32_t CTL1; /**< Control 1 */
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reg32_t RADCEXTCFG; /**< RADC External Configuration */
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reg32_t AMPCOMPCTL; /**< Amplitude Compensation Control */
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reg32_t AMPCOMPTH1; /**< Amplitude Compensation Threshold 1 */
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reg32_t AMPCOMPTH2; /**< Amplitude Compensation Threshold 2 */
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reg32_t ANABYPASSVAL1; /**< Analog Bypass Values 1 */
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reg32_t ANABYPASSVAL2; /**< Internal */
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reg32_t ATESTCTL; /**< Analog Test Control */
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reg32_t ADCDOUBLERNANOAMPCTL; /**< ADC Doubler Nanoamp Control */
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reg32_t XOSCHFCTL; /**< XOSCHF Control */
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reg32_t LFOSCCTL; /**< Low Frequency Oscillator Control */
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reg32_t RCOSCHFCTL; /**< RCOSCHF Control */
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reg32_t RCOSCMFCTL; /**< RCOSC_MF Control */
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reg32_t __reserved1; /**< Reserved */
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reg32_t STAT0; /**< Status 0 */
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reg32_t STAT1; /**< Status 1 */
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reg32_t STAT2; /**< Status 2 */
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} ddi0_osc_regs_t;
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/**
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* @brief DDI_0_OSC registers with masked 16-bit access
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*/
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typedef struct {
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reg32_m16_t CTL0; /**< Control 0 */
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reg32_m16_t CTL1; /**< Control 1 */
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reg32_m16_t RADCEXTCFG; /**< RADC External Configuration */
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reg32_m16_t AMPCOMPCTL; /**< Amplitude Compensation Control */
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reg32_m16_t AMPCOMPTH1; /**< Amplitude Compensation Threshold 1 */
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reg32_m16_t AMPCOMPTH2; /**< Amplitude Compensation Threshold 2 */
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reg32_m16_t ANABYPASSVAL1; /**< Analog Bypass Values 1 */
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reg32_m16_t ANABYPASSVAL2; /**< Internal */
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reg32_m16_t ATESTCTL; /**< Analog Test Control */
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reg32_m16_t ADCDOUBLERNANOAMPCTL; /**< ADC Doubler Nanoamp Control */
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reg32_m16_t XOSCHFCTL; /**< XOSCHF Control */
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reg32_m16_t LFOSCCTL; /**< Low Frequency Oscillator Control */
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reg32_m16_t RCOSCHFCTL; /**< RCOSCHF Control */
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reg32_m16_t RCOSCMFCTL; /**< RCOSC_MF Control */
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reg32_m16_t __reserved1; /**< Reserved */
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reg32_m16_t STAT0; /**< Status 0 */
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reg32_m16_t STAT1; /**< Status 1 */
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reg32_m16_t STAT2; /**< Status 2 */
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} ddi0_osc_regs_m16_t;
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/**
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* @brief DDI_0_OSC register values
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* @{
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*/
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#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_m 0x00000001
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#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_s 0
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#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001
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#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000
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#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_m 0x0000000C
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#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_s 2
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#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL 0x00000180
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#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200
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#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400
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#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800
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#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000
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#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000
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#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_m 0x01000000
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#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000
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#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION 0x0C000000
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#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000
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#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000
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#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000
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#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001
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#define DDI_0_OSC_STAT0_SCLK_HF_SRC_m 0x10000000
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#define DDI_0_OSC_STAT0_SCLK_HF_SRC_s 28
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#define DDI_0_OSC_STAT0_SCLK_LF_SRC_m 0x60000000
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#define DDI_0_OSC_STAT0_SCLK_LF_SRC_s 29
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/** @} */
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/**
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* @ingroup cpu_cc26x2_cc13x2_peripheral_memory_map
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* @{
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*/
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#define DDI_DIR 0x00000000
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#define DDI_SET 0x00000080
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#define DDI_CLR 0x00000100
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#define DDI_MASK4B 0x00000200
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#define DDI_MASK8B 0x00000300
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#define DDI_MASK16B 0x00000400
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/**
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* @brief DDI0_OSC base address
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*/
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#define DDI0_OSC_BASE (PERIPH_BASE + 0xCA000)
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/**
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* @brief DDI0_OSC 16-bit masked access base address
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*/
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#define DDI0_OSC_BASE_M16 (DDI0_OSC_BASE + DDI_MASK16B)
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/** @} */
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/**
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* @brief DDI_0_OSC register bank
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*/
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#define DDI_0_OSC ((ddi0_osc_regs_t *) (DDI0_OSC_BASE))
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/**
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* @brief DDI_0_OSC 16-bit masked access register bank
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*/
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#define DDI_0_OSC_M16 ((ddi0_osc_regs_m16_t *) (DDI0_OSC_BASE_M16))
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/**
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* @brief SCLK_HF oscillators.
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* @{
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*/
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#define OSC_RCOSC_HF 0x00000000 /**< Internal HF RC oscillator */
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#define OSC_XOSC_HF 0x00000001 /**< External HF crystal oscillator */
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/** @} */
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/**
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* @brief DDI_0_OSC functions
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* @{
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*/
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/**
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* @brief Switch the high frequency clock.
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*
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* @note This function will not return until the clock source has been switched.
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*
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* @param[in] osc The oscillator to use.
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*/
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void osc_hf_source_switch(uint32_t osc);
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/** @} */
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/**
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* @brief AON_PMCTL registers
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*/
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typedef struct {
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reg32_t __reserved1; /**< Reserved */
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reg32_t AUXSCECLK; /**< AUX SCE management */
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reg32_t RAMCFG; /**< RAM configuration */
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reg32_t __reserved2; /**< Reserved */
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reg32_t PWRCTL; /**< Power management control */
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reg32_t PWRSTAT; /**< Power status */
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reg32_t SHUTDOWN; /**< Shutdown control */
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reg32_t RECHARGECFG; /**< Recharge controller configuration */
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reg32_t RECHARGESTAT; /**< Recharge controller status */
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reg32_t OSCCFG; /**< Oscillator configuration */
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reg32_t RESETCTL; /**< Reset control */
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reg32_t SLEEPCTL; /**< Reset control */
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reg32_t __reserved3; /**< Reserved */
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reg32_t JTAGCFG; /**< JTAG configuration */
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reg32_t __reserved4; /**< Reserved */
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reg32_t JTAGUSERCODE; /**< JTAG USERCODE */
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} aon_pmctl_regs_t;
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/**
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* @brief AON_PMTCTL register values
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* @{
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*/
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#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001
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#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_m 0x02000000
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#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_m 0x01000000
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#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_m 0x00020000
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#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_m 0x00010000
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#define AON_PMCTL_RESETCTL_BOOT_DET_1_m 0x00002000
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#define AON_PMCTL_RESETCTL_BOOT_DET_0_m 0x00001000
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#define AON_PMCTL_RESETCTL_BOOT_DET_0_s 12
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#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_m 0x00000010
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/** @} */
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief AON_PMCTL base address
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*/
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#define AON_PMCTL_BASE (PERIPH_BASE + 0x90000)
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/** @} */
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/**
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* @brief AON_PMCTL register bank
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*/
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#define AON_PMCTL ((aon_pmctl_regs_t *) (AON_PMCTL_BASE))
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/**
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* AON_RTC registers
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*/
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typedef struct {
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reg32_t CTL; /**< Control */
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reg32_t EVFLAGS; /**< Event Flags, RTC Status */
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reg32_t SEC; /**< Second Counter Value, Integer Part */
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reg32_t SUBSEC; /**< Second Counter Value, Fractional Part */
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reg32_t SUBSECINC; /**< Subseconds Increment */
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reg32_t CHCTL; /**< Channel Configuration */
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reg32_t CH0CMP; /**< Channel 0 Compare Value */
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reg32_t CH1CMP; /**< Channel 1 Compare Value */
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reg32_t CH2CMP; /**< Channel 2 Compare Value */
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reg32_t CH2CMPINC; /**< Channel 2 Compare Value Auto-increment */
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reg32_t CH1CAPT; /**< Channel 1 Capture Value */
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reg32_t SYNC; /**< AON Synchronization */
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reg32_t TIME; /**< Current Counter Value */
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reg32_t SYNCLF; /**< Synchronization to SCLK_LF */
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} aon_rtc_regs_t;
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/**
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* @brief RTC_UPD is a 16 KHz signal used to sync up the radio timer. The
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* 16 Khz is SCLK_LF divided by 2
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* @details 0h = RTC_UPD signal is forced to 0
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* 1h = RTC_UPD signal is toggling @16 kHz
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*/
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#define AON_RTC_CTL_RTC_UPD_EN 0x00000002
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AON_RTC_BASE (PERIPH_BASE + 0x92000) /**< AON_RTC base address */
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/** @} */
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#define AON_RTC ((aon_rtc_regs_t *) (AON_RTC_BASE)) /**< AON_RTC register bank */
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/**
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* PRCM registers
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*/
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typedef struct {
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reg32_t INFRCLKDIVR; /**< infrastructure clock division factor for run mode */
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reg32_t INFRCLKDIVS; /**< infrastructure clock division factor for sleep mode */
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reg32_t INFRCLKDIVDS; /**< infrastructure clock division factor for deep sleep mode */
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reg32_t VDCTL; /**< MCU voltage domain control */
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reg32_t __reserved1[6]; /**< Reserved */
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reg32_t CLKLOADCTL; /**< clock load control */
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reg32_t RFCCLKG; /**< RFC clock gate */
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reg32_t VIMSCLKG; /**< VIMS clock gate */
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reg32_t __reserved2[2]; /**< Reserved */
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reg32_t SECDMACLKGR; /**< TRNG, CRYPTO, and UDMA clock gate for run mode */
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reg32_t SECDMACLKGS; /**< TRNG, CRYPTO, and UDMA clock gate for sleep mode */
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reg32_t SECDMACLKGDS; /**< TRNG, CRYPTO, and UDMA clock gate for deep sleep mode */
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reg32_t GPIOCLKGR; /**< GPIO clock gate for run mode */
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reg32_t GPIOCLKGS; /**< GPIO clock gate for sleep mode */
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reg32_t GPIOCLKGDS; /**< GPIO clock gate for deep sleep mode */
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reg32_t GPTCLKGR; /**< GPT clock gate for run mode */
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reg32_t GPTCLKGS; /**< GPT clock gate for sleep mode */
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reg32_t GPTCLKGDS; /**< GPT clock gate for deep sleep mode */
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reg32_t I2CCLKGR; /**< I2C clock gate for run mode */
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reg32_t I2CCLKGS; /**< I2C clock gate for sleep mode */
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reg32_t I2CCLKGDS; /**< I2C clock gate for deep sleep mode */
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reg32_t UARTCLKGR; /**< UART clock gate for run mode */
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reg32_t UARTCLKGS; /**< UART clock gate for sleep mode */
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reg32_t UARTCLKGDS; /**< UART clock gate for deep sleep mode */
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reg32_t SSICLKGR; /**< SSI clock gate for run mode */
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reg32_t SSICLKGS; /**< SSI clock gate for sleep mode */
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reg32_t SSICLKGDS; /**< SSI clock gate for deep sleep mode */
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reg32_t I2SCLKGR; /**< I2S clock gate for run mode */
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reg32_t I2SCLKGS; /**< I2S clock gate for sleep mode */
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reg32_t I2SCLKGDS; /**< I2S clock gate for deep sleep mode */
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reg32_t __reserved3[9]; /**< Reserved */
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reg32_t SYSBUSCLKDIV; /**< System bus clock division factor */
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reg32_t CPUCLKDIV; /**< CPU clock division factor */
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reg32_t PERBUSCPUCLKDIV; /**< Peripheral bus division factor */
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reg32_t __reserved4; /**< Reserved */
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reg32_t PERDMACLKDIV; /**< DMA clock division factor */
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reg32_t I2SBCLKSEL; /**< I2S clock select */
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reg32_t GPTCLKDIV; /**< GPT scalar */
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reg32_t I2SCLKCTL; /**< I2S clock control */
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reg32_t I2SMCLKDIV; /**< MCLK division ratio */
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reg32_t I2SBCLKDIV; /**< BCLK division ratio */
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reg32_t I2SWCLKDIV; /**< WCLK division ratio */
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reg32_t __reserved5[4]; /**< Reserved */
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reg32_t RESETSECDMA; /**< Reset SEC and UDMA */
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reg32_t RESETGPIO; /**< Reset GPIO */
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reg32_t RESETGPT; /**< Reset GPTs */
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reg32_t RESETI2C; /**< Reset I2C */
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reg32_t RESETUART; /**< Reset UART */
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reg32_t RESETSSI; /**< Reset SSI */
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reg32_t RESETI2S; /**< Reset I2S */
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reg32_t __reserved6[8]; /**< Reserved */
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reg32_t PDCTL0; /**< power domain control */
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reg32_t PDCTL0RFC; /**< RFC power domain control */
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reg32_t PDCTL0SERIAL; /**< SERIAL power domain control */
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reg32_t PDCTL0PERIPH; /**< PERIPH power domain control */
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reg32_t __reserved7; /**< Reserved */
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reg32_t PDSTAT0; /**< power domain status */
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reg32_t PDSTAT0RFC; /**< RFC power domain status */
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reg32_t PDSTAT0SERIAL; /**< SERIAL power domain status */
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reg32_t PDSTAT0PERIPH; /**< PERIPH power domain status */
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reg32_t __reserved8[11]; /**< Reserved */
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reg32_t PDCTL1; /**< power domain control */
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reg32_t __reserved9; /**< power domain control */
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reg32_t PDCTL1CPU; /**< CPU power domain control */
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reg32_t PDCTL1RFC; /**< RFC power domain control */
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reg32_t PDCTL1VIMS; /**< VIMS power domain control */
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reg32_t __reserved10; /**< Reserved */
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reg32_t PDSTAT1; /**< power domain status */
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reg32_t PDSTAT1BUS; /**< BUS power domain status */
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reg32_t PDSTAT1RFC; /**< RFC power domain status */
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reg32_t PDSTAT1CPU; /**< CPU power domain status */
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reg32_t PDSTAT1VIMS; /**< VIMS power domain status */
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reg32_t __reserved11[9]; /**< Reserved */
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reg32_t RFCBITS; /**< Control to RFC */
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reg32_t RFCMODESEL; /**< selected RFC mode */
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reg32_t RFCMODEHWOPT; /**< allowed RFC modes */
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reg32_t __reserved12[2]; /**< Reserved */
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reg32_t PWRPROFSTAT; /**< power profiler register */
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reg32_t __reserved13[14]; /**< Reserved */
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reg32_t MCUSRAMCFG; /**< MCU SRAM configuration */
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reg32_t __reserved14; /**< Reserved */
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reg32_t RAMRETEN; /**< memory retention control */
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reg32_t __reserved15[27]; /**< Reserved */
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reg32_t OSCIMSC; /**< oscillator interrupt mask */
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reg32_t OSCRIS; /**< oscillator raw interrupt status */
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reg32_t OSCICR; /**< oscillator raw interrupt clear */
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} prcm_regs_t;
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/**
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* @brief PRCM register values
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* @{
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*/
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#define CLKLOADCTL_LOAD 0x1
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#define CLKLOADCTL_LOADDONE 0x2
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#define PDCTL0_RFC_ON 0x1
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#define PDCTL0_SERIAL_ON 0x2
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#define PDCTL0_PERIPH_ON 0x4
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#define PDSTAT0_RFC_ON 0x1
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#define PDSTAT0_SERIAL_ON 0x2
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#define PDSTAT0_PERIPH_ON 0x4
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#define PDCTL1_CPU_ON 0x2
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#define PDCTL1_RFC_ON 0x4
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#define PDCTL1_VIMS_ON 0x8
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#define PDSTAT1_CPU_ON 0x2
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#define PDSTAT1_RFC_ON 0x4
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#define PDSTAT1_VIMS_ON 0x8
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#define GPIOCLKGR_CLK_EN 0x1
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#define I2CCLKGR_CLK_EN 0x1
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#define UARTCLKGR_CLK_EN_UART0 0x1
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#define UARTCLKGR_CLK_EN_UART1 0x2
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#define GPIOCLKGS_CLK_EN 0x1
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#define I2CCLKGS_CLK_EN 0x1
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#define UARTCLKGS_CLK_EN_UART0 0x1
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#define UARTCLKGS_CLK_EN_UART1 0x2
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#define GPIOCLKGDS_CLK_EN 0x1
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#define I2CCLKGDS_CLK_EN 0x1
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#define UARTCLKGDS_CLK_EN_UART0 0x1
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#define UARTCLKGDS_CLK_EN_UART1 0x2
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/** @} */
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define PRCM_BASE (PERIPH_BASE + 0x82000) /**< PRCM base address */
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#define PRCM_BASE_NONBUF (PERIPH_BASE_NONBUF + 0x82000) /**< PRCM base address (nonbuf) */
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/** @} */
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#define PRCM ((prcm_regs_t *) (PRCM_BASE)) /**< PRCM register bank */
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#define PRCM_NONBUF ((prcm_regs_t *) (PRCM_BASE_NONBUF)) /**< PRCM register bank (nonbuf) */
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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#endif /* CC26X2_CC13X2_PRCM_H */
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/** @} */
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