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71 lines
1.8 KiB
C
71 lines
1.8 KiB
C
/*
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* Copyright (C) 2016 Freie Universität Berlin
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* 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief QDEC CPU specific definitions for the STM32 family
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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*/
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#ifndef PERIPH_CPU_QDEC_H
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#define PERIPH_CPU_QDEC_H
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#include <stdint.h>
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#include "cpu.h"
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#include "periph/cpu_gpio.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief All STM QDEC timers have 2 capture channels
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*/
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#define QDEC_CHAN (2U)
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/**
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* @brief QDEC channel
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*/
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typedef struct {
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gpio_t pin; /**< GPIO pin mapped to this channel */
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uint8_t cc_chan; /**< capture compare channel used */
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} qdec_chan_t;
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/**
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* @brief QDEC configuration
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*/
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typedef struct {
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TIM_TypeDef *dev; /**< Timer used */
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uint32_t max; /**< Maximum counter value */
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uint32_t rcc_mask; /**< bit in clock enable register */
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qdec_chan_t chan[QDEC_CHAN]; /**< channel mapping, set to {GPIO_UNDEF, 0}
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* if not used */
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#ifdef CPU_FAM_STM32F1
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uint32_t remap; /**< AFIO remap mask to route periph to other
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pins (or zero, if not needed) */
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#else
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gpio_af_t af; /**< alternate function used */
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#endif
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uint8_t bus; /**< APB bus */
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uint8_t irqn; /**< global IRQ channel */
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} qdec_conf_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_QDEC_H */
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/** @} */
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