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cpu/stm32/periph_qdec: support pin remap for F1

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Add support to route peripheral to alternative pins for the STM32F1
family.
This commit is contained in:
Marian Buschsieweke 2022-10-22 01:43:24 +02:00
parent 16df27c51d
commit b6845cef79
No known key found for this signature in database
GPG Key ID: CB8E3238CE715A94
2 changed files with 16 additions and 1 deletions
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5
cpu/stm32/include/periph/cpu_qdec.h
View File

@ -52,7 +52,10 @@ typedef struct {
uint32_t rcc_mask; /**< bit in clock enable register */
qdec_chan_t chan[QDEC_CHAN]; /**< channel mapping, set to {GPIO_UNDEF, 0}
* if not used */
#ifndef CPU_FAM_STM32F1
#ifdef CPU_FAM_STM32F1
uint32_t remap; /**< AFIO remap mask to route periph to other
pins (or zero, if not needed) */
#else
gpio_af_t af; /**< alternate function used */
#endif
uint8_t bus; /**< APB bus */

12
cpu/stm32/periph/qdec.c
View File

@ -26,6 +26,9 @@
#include "periph/qdec.h"
#include "periph/gpio.h"
#define ENABLE_DEBUG 0
#include "debug.h"
#ifdef QDEC_NUMOF
/**
@ -59,6 +62,15 @@ int32_t qdec_init(qdec_t qdec, qdec_mode_t mode, qdec_cb_t cb, void *arg)
/* Power on the used timer */
periph_clk_en(qdec_config[qdec].bus, qdec_config[qdec].rcc_mask);
/* Route peripheral to correct pins (STM32F1 only, other MCU families route
* pins to peripheral rather than peripheral to pins */
#ifdef CPU_FAM_STM32F1
DEBUG("[qdec] AFIO->MAPR = 0x%" PRIx32 ", |= 0x%" PRIx32 "\n",
AFIO->MAPR, qdec_config[qdec].remap);
AFIO->MAPR |= qdec_config[qdec].remap;
DEBUG("[qdec] AFIO->MAPR = 0x%" PRIx32 "\n", AFIO->MAPR);
#endif
/* Reset configuration and CC channels */
dev(qdec)->CR1 = 0;
dev(qdec)->CR2 = 0;