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https://github.com/RIOT-OS/RIOT.git
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411 lines
21 KiB
C
411 lines
21 KiB
C
/***************************************************************************//**
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* @file
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* @brief CMSIS Cortex-M Peripheral Access Layer Header File
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* for EFM32HG310F64
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*******************************************************************************
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* # License
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* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
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*******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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******************************************************************************/
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#if defined(__ICCARM__)
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#pragma system_include /* Treat file as system include file. */
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang system_header /* Treat file as system include file. */
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#endif
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#ifndef EFM32HG310F64_H
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#define EFM32HG310F64_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************************************************************//**
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* @addtogroup Parts
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @defgroup EFM32HG310F64 EFM32HG310F64
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* @{
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******************************************************************************/
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/** Interrupt Number Definition */
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typedef enum IRQn{
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/****** Cortex-M0+ Processor Exceptions Numbers *****************************************/
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NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M0+ Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< -13 Cortex-M0+ Hard Fault Interrupt */
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SVCall_IRQn = -5, /*!< -5 Cortex-M0+ SV Call Interrupt */
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PendSV_IRQn = -2, /*!< -2 Cortex-M0+ Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< -1 Cortex-M0+ System Tick Interrupt */
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/****** EFM32HG Peripheral Interrupt Numbers ********************************************/
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DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
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GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
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TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
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ACMP0_IRQn = 3, /*!< 3 EFM32 ACMP0 Interrupt */
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ADC0_IRQn = 4, /*!< 4 EFM32 ADC0 Interrupt */
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I2C0_IRQn = 5, /*!< 5 EFM32 I2C0 Interrupt */
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GPIO_ODD_IRQn = 6, /*!< 6 EFM32 GPIO_ODD Interrupt */
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TIMER1_IRQn = 7, /*!< 7 EFM32 TIMER1 Interrupt */
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USART1_RX_IRQn = 8, /*!< 8 EFM32 USART1_RX Interrupt */
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USART1_TX_IRQn = 9, /*!< 9 EFM32 USART1_TX Interrupt */
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LEUART0_IRQn = 10, /*!< 10 EFM32 LEUART0 Interrupt */
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PCNT0_IRQn = 11, /*!< 11 EFM32 PCNT0 Interrupt */
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RTC_IRQn = 12, /*!< 12 EFM32 RTC Interrupt */
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CMU_IRQn = 13, /*!< 13 EFM32 CMU Interrupt */
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VCMP_IRQn = 14, /*!< 14 EFM32 VCMP Interrupt */
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MSC_IRQn = 15, /*!< 15 EFM32 MSC Interrupt */
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AES_IRQn = 16, /*!< 16 EFM32 AES Interrupt */
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USART0_RX_IRQn = 17, /*!< 17 EFM32 USART0_RX Interrupt */
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USART0_TX_IRQn = 18, /*!< 18 EFM32 USART0_TX Interrupt */
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USB_IRQn = 19, /*!< 19 EFM32 USB Interrupt */
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TIMER2_IRQn = 20, /*!< 20 EFM32 TIMER2 Interrupt */
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} IRQn_Type;
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/***************************************************************************//**
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* @defgroup EFM32HG310F64_Core EFM32HG310F64 Core
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* @{
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* @brief Processor and Core Peripheral Section
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******************************************************************************/
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#define __MPU_PRESENT 0U /**< MPU not present */
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#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
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#define __NVIC_PRIO_BITS 2U /**< NVIC interrupt priority bits */
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#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
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/** @} End of group EFM32HG310F64_Core */
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/***************************************************************************//**
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* @defgroup EFM32HG310F64_Part EFM32HG310F64 Part
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* @{
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******************************************************************************/
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/** Part family */
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#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */
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#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
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#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
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#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
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#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /**< Silicon Labs internal use only, may change any time */
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#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /**< Silicon Labs internal use only, may change any time */
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#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */
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#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */
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/* If part number is not defined as compiler option, define it */
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#if !defined(EFM32HG310F64)
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#define EFM32HG310F64 1 /**< Happy Gecko Part */
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#endif
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/** Configure part number */
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#define PART_NUMBER "EFM32HG310F64" /**< Part Number */
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/** Memory Base addresses and limits */
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#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
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#define RAM_MEM_SIZE (0x40000UL) /**< RAM available address space */
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#define RAM_MEM_END (0x2003FFFFUL) /**< RAM end address */
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#define RAM_MEM_BITS (0x18UL) /**< RAM used bits */
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#define DEVICE_MEM_BASE (0xF0040000UL) /**< DEVICE base address */
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#define DEVICE_MEM_SIZE (0x1000UL) /**< DEVICE available address space */
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#define DEVICE_MEM_END (0xF0040FFFUL) /**< DEVICE end address */
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#define DEVICE_MEM_BITS (0x12UL) /**< DEVICE used bits */
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#define USBC_MEM_BASE (0x40100000UL) /**< USBC base address */
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#define USBC_MEM_SIZE (0x40000UL) /**< USBC available address space */
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#define USBC_MEM_END (0x4013FFFFUL) /**< USBC end address */
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#define USBC_MEM_BITS (0x18UL) /**< USBC used bits */
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#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
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#define RAM_CODE_MEM_SIZE (0x20000UL) /**< RAM_CODE available address space */
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#define RAM_CODE_MEM_END (0x1001FFFFUL) /**< RAM_CODE end address */
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#define RAM_CODE_MEM_BITS (0x17UL) /**< RAM_CODE used bits */
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#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
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#define PER_MEM_SIZE (0xE0000UL) /**< PER available address space */
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#define PER_MEM_END (0x400DFFFFUL) /**< PER end address */
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#define PER_MEM_BITS (0x20UL) /**< PER used bits */
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#define FLASH_MEM_BASE (0x0UL) /**< FLASH base address */
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#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
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#define FLASH_MEM_END (0xFFFFFFFUL) /**< FLASH end address */
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#define FLASH_MEM_BITS (0x28UL) /**< FLASH used bits */
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#define AES_MEM_BASE (0x400E0000UL) /**< AES base address */
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#define AES_MEM_SIZE (0x400UL) /**< AES available address space */
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#define AES_MEM_END (0x400E03FFUL) /**< AES end address */
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#define AES_MEM_BITS (0x10UL) /**< AES used bits */
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/** Flash and SRAM limits for EFM32HG310F64 */
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#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
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#define FLASH_SIZE (0x00010000UL) /**< Available Flash Memory */
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#define FLASH_PAGE_SIZE 1024U /**< Flash Memory page size */
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#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
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#define SRAM_SIZE (0x00002000UL) /**< Available SRAM Memory */
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#define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */
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#define PRS_CHAN_COUNT 6 /**< Number of PRS channels */
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#define DMA_CHAN_COUNT 6 /**< Number of DMA channels */
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#define EXT_IRQ_COUNT 21 /**< Number of External (NVIC) interrupts */
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/** AF channels connect the different on-chip peripherals with the af-mux */
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#define AFCHAN_MAX 42U
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#define AFCHANLOC_MAX 7U
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/** Analog AF channels */
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#define AFACHAN_MAX 27U
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/* Part number capabilities */
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#define TIMER_PRESENT /**< TIMER is available in this part */
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#define TIMER_COUNT 3 /**< 3 TIMERs available */
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#define ACMP_PRESENT /**< ACMP is available in this part */
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#define ACMP_COUNT 1 /**< 1 ACMPs available */
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#define USART_PRESENT /**< USART is available in this part */
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#define USART_COUNT 2 /**< 2 USARTs available */
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#define IDAC_PRESENT /**< IDAC is available in this part */
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#define IDAC_COUNT 1 /**< 1 IDACs available */
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#define ADC_PRESENT /**< ADC is available in this part */
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#define ADC_COUNT 1 /**< 1 ADCs available */
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#define LEUART_PRESENT /**< LEUART is available in this part */
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#define LEUART_COUNT 1 /**< 1 LEUARTs available */
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#define PCNT_PRESENT /**< PCNT is available in this part */
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#define PCNT_COUNT 1 /**< 1 PCNTs available */
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#define I2C_PRESENT /**< I2C is available in this part */
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#define I2C_COUNT 1 /**< 1 I2Cs available */
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#define AES_PRESENT /**< AES is available in this part */
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#define AES_COUNT 1 /**< 1 AES available */
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#define DMA_PRESENT /**< DMA is available in this part */
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#define DMA_COUNT 1 /**< 1 DMA available */
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#define LE_PRESENT /**< LE is available in this part */
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#define LE_COUNT 1 /**< 1 LE available */
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#define USBC_PRESENT /**< USBC is available in this part */
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#define USBC_COUNT 1 /**< 1 USBC available */
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#define USBLE_PRESENT /**< USBLE is available in this part */
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#define USBLE_COUNT 1 /**< 1 USBLE available */
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#define USB_PRESENT /**< USB is available in this part */
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#define USB_COUNT 1 /**< 1 USB available */
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#define MSC_PRESENT /**< MSC is available in this part */
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#define MSC_COUNT 1 /**< 1 MSC available */
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#define EMU_PRESENT /**< EMU is available in this part */
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#define EMU_COUNT 1 /**< 1 EMU available */
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#define RMU_PRESENT /**< RMU is available in this part */
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#define RMU_COUNT 1 /**< 1 RMU available */
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#define CMU_PRESENT /**< CMU is available in this part */
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#define CMU_COUNT 1 /**< 1 CMU available */
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#define PRS_PRESENT /**< PRS is available in this part */
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#define PRS_COUNT 1 /**< 1 PRS available */
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#define GPIO_PRESENT /**< GPIO is available in this part */
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#define GPIO_COUNT 1 /**< 1 GPIO available */
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#define VCMP_PRESENT /**< VCMP is available in this part */
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#define VCMP_COUNT 1 /**< 1 VCMP available */
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#define RTC_PRESENT /**< RTC is available in this part */
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#define RTC_COUNT 1 /**< 1 RTC available */
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#define HFXTAL_PRESENT /**< HFXTAL is available in this part */
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#define HFXTAL_COUNT 1 /**< 1 HFXTAL available */
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#define LFXTAL_PRESENT /**< LFXTAL is available in this part */
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#define LFXTAL_COUNT 1 /**< 1 LFXTAL available */
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#define USHFRCO_PRESENT /**< USHFRCO is available in this part */
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#define USHFRCO_COUNT 1 /**< 1 USHFRCO available */
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#define WDOG_PRESENT /**< WDOG is available in this part */
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#define WDOG_COUNT 1 /**< 1 WDOG available */
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#define DBG_PRESENT /**< DBG is available in this part */
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#define DBG_COUNT 1 /**< 1 DBG available */
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#define MTB_PRESENT /**< MTB is available in this part */
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#define MTB_COUNT 1 /**< 1 MTB available */
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#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
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#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
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#define ANALOG_PRESENT /**< ANALOG is available in this part */
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#define ANALOG_COUNT 1 /**< 1 ANALOG available */
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/** @} End of group EFM32HG310F64_Part */
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#ifndef ARM_MATH_CM0PLUS
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#define ARM_MATH_CM0PLUS
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#endif
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#include "arm_math.h" /* To get __CLZ definitions etc. */
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#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
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#include "system_efm32hg.h" /* System Header */
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/***************************************************************************//**
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* @defgroup EFM32HG310F64_Peripheral_TypeDefs EFM32HG310F64 Peripheral TypeDefs
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* @{
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* @brief Device Specific Peripheral Register Structures
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******************************************************************************/
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#include "efm32hg_aes.h"
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#include "efm32hg_dma_ch.h"
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#include "efm32hg_dma.h"
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#include "efm32hg_usb_diep.h"
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#include "efm32hg_usb_doep.h"
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#include "efm32hg_usb.h"
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#include "efm32hg_msc.h"
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#include "efm32hg_emu.h"
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#include "efm32hg_rmu.h"
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#include "efm32hg_cmu.h"
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#include "efm32hg_timer_cc.h"
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#include "efm32hg_timer.h"
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#include "efm32hg_acmp.h"
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#include "efm32hg_usart.h"
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#include "efm32hg_prs_ch.h"
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#include "efm32hg_prs.h"
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#include "efm32hg_idac.h"
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#include "efm32hg_gpio_p.h"
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#include "efm32hg_gpio.h"
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#include "efm32hg_vcmp.h"
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#include "efm32hg_adc.h"
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#include "efm32hg_leuart.h"
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#include "efm32hg_pcnt.h"
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#include "efm32hg_i2c.h"
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#include "efm32hg_rtc.h"
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#include "efm32hg_wdog.h"
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#include "efm32hg_mtb.h"
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#include "efm32hg_dma_descriptor.h"
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#include "efm32hg_devinfo.h"
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#include "efm32hg_romtable.h"
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#include "efm32hg_calibrate.h"
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/** @} End of group EFM32HG310F64_Peripheral_TypeDefs */
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/***************************************************************************//**
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* @defgroup EFM32HG310F64_Peripheral_Base EFM32HG310F64 Peripheral Memory Map
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* @{
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******************************************************************************/
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#define AES_BASE (0x400E0000UL) /**< AES base address */
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#define DMA_BASE (0x400C2000UL) /**< DMA base address */
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#define USB_BASE (0x400C4000UL) /**< USB base address */
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#define MSC_BASE (0x400C0000UL) /**< MSC base address */
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#define EMU_BASE (0x400C6000UL) /**< EMU base address */
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#define RMU_BASE (0x400CA000UL) /**< RMU base address */
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#define CMU_BASE (0x400C8000UL) /**< CMU base address */
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#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
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#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
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#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
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#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
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#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
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#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
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#define PRS_BASE (0x400CC000UL) /**< PRS base address */
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#define IDAC0_BASE (0x40004000UL) /**< IDAC0 base address */
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#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
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#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
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#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
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#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
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#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
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#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
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#define RTC_BASE (0x40080000UL) /**< RTC base address */
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#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
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#define MTB_BASE (0xF0040000UL) /**< MTB base address */
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#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
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#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
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#define ROMTABLE_BASE (0xF00FFFD0UL) /**< ROMTABLE base address */
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#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
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#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
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/** @} End of group EFM32HG310F64_Peripheral_Base */
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/***************************************************************************//**
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* @defgroup EFM32HG310F64_Peripheral_Declaration EFM32HG310F64 Peripheral Declarations
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* @{
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******************************************************************************/
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#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
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#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
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#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
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#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
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#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
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#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
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#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
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#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
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#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
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#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
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#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
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#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
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#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
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#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
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#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
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#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
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#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
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#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
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#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
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#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
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#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
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#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
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#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
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#define MTB ((MTB_TypeDef *) MTB_BASE) /**< MTB base pointer */
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#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
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#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
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#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
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/** @} End of group EFM32HG310F64_Peripheral_Declaration */
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/***************************************************************************//**
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* @defgroup EFM32HG310F64_BitFields EFM32HG310F64 Bit Fields
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* @{
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******************************************************************************/
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#include "efm32hg_prs_signals.h"
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#include "efm32hg_dmareq.h"
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#include "efm32hg_dmactrl.h"
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/***************************************************************************//**
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* @defgroup EFM32HG310F64_UNLOCK EFM32HG310F64 Unlock Codes
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* @{
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******************************************************************************/
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#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
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#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
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#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
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#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
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#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
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/** @} End of group EFM32HG310F64_UNLOCK */
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/** @} End of group EFM32HG310F64_BitFields */
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/***************************************************************************//**
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* @defgroup EFM32HG310F64_Alternate_Function EFM32HG310F64 Alternate Function
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* @{
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******************************************************************************/
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#include "efm32hg_af_ports.h"
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#include "efm32hg_af_pins.h"
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/** @} End of group EFM32HG310F64_Alternate_Function */
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/***************************************************************************//**
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* @brief Set the value of a bit field within a register.
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*
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* @param REG
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* The register to update
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* @param MASK
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* The mask for the bit field to update
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* @param VALUE
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* The value to write to the bit field
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* @param OFFSET
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* The number of bits that the field is offset within the register.
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* 0 (zero) means LSB.
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******************************************************************************/
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#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
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REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
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/** @} End of group EFM32HG310F64 */
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/** @} End of group Parts */
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#ifdef __cplusplus
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}
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#endif
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#endif /* EFM32HG310F64_H */
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