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https://github.com/RIOT-OS/RIOT.git
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17a5101b40
In commit 513b20ffd3 the SPI API was changed to
power up an configure the SPI bus on spi_acquire(). Sadly, the lpc2387 SPI
apparently needs to be reconfigured after each power up. This commit moves
the initialization code required after each power up from spi_init() to
spi_acquire().
143 lines
3.2 KiB
C
143 lines
3.2 KiB
C
/*
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* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
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* 2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_lpc2387
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* @ingroup drivers_periph_spi
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* @{
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*
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* @file
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* @brief Low-level SPI driver implementation
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*
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* This implementation is very basic and only supports a single SPI device with
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* limited configuration options.
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*
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* @todo This implementation needs a major rework
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*
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "cpu.h"
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#include "mutex.h"
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#include "assert.h"
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#include "periph/spi.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#define SPI_TX_EMPTY (SSP0SR & SSPSR_TFE)
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#define SPI_BUSY (SSP0SR & SSPSR_BSY)
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#define SPI_RX_AVAIL (SSP0SR & SSPSR_RNE)
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/**
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* @brief Array holding one pre-initialized mutex for each SPI device
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*/
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static mutex_t lock = MUTEX_INIT;
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void spi_init(spi_t bus)
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{
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assert(bus == SPI_DEV(0));
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/* configure pins */
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spi_init_pins(bus);
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/* power off the bus (default is on) */
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PCONP &= ~(PCSSP0);
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}
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void spi_init_pins(spi_t bus)
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{
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(void) bus;
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PINSEL3 |= (BIT8 | BIT9); /* SCLK */
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PINSEL3 |= (BIT14 | BIT15); /* MISO */
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PINSEL3 |= (BIT16 | BIT17); /* MOSI */
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}
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int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
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{
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(void) bus;
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(void) cs;
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uint32_t pclksel;
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uint32_t cpsr;
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/* only support for mode 0 at the moment */
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if (mode != SPI_MODE_0) {
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return SPI_NOMODE;
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}
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/* lock bus */
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mutex_lock(&lock);
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/* power on */
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PCONP |= (PCSSP0);
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/* interface setup */
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SSP0CR0 = 7;
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/* configure bus clock */
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lpc2387_pclk_scale(CLOCK_CORECLOCK / 1000, (uint32_t)clk, &pclksel, &cpsr);
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PCLKSEL1 &= ~(BIT10 | BIT11); /* CCLK to PCLK divider*/
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PCLKSEL1 |= pclksel << 10;
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SSP0CPSR = cpsr;
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/* enable the bus */
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SSP0CR1 |= BIT1;
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/* clear RxFIFO */
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int dummy;
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while (SPI_RX_AVAIL) { /* while RNE (Receive FIFO Not Empty)...*/
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dummy = SSP0DR; /* read data*/
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}
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(void) dummy; /* to suppress unused-but-set-variable */
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return SPI_OK;
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}
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void spi_release(spi_t bus)
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{
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(void) bus;
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/* disable, power off, and release the bus */
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SSP0CR1 &= ~(BIT1);
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PCONP &= ~(PCSSP0);
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mutex_unlock(&lock);
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}
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void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
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const void *out, void *in, size_t len)
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{
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(void) bus;
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const uint8_t *out_buf = out;
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uint8_t *in_buf = in;
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assert(out_buf || in_buf);
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if (cs != SPI_CS_UNDEF) {
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gpio_clear((gpio_t)cs);
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}
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for (size_t i = 0; i < len; i++) {
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uint8_t tmp = (out_buf) ? out_buf[i] : 0;
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while (!SPI_TX_EMPTY) {}
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SSP0DR = tmp;
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while (SPI_BUSY) {}
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while (!SPI_RX_AVAIL) {}
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tmp = (uint8_t)SSP0DR;
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if (in_buf) {
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in_buf[i] = tmp;
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}
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}
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if ((!cont) && cs != SPI_CS_UNDEF) {
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gpio_set((gpio_t)cs);
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}
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}
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