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Merge pull request #4780 from haukepetersen/opt_periph_spi2

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drivers/spi: reworked SPI driver interface
This commit is contained in:
Peter Kietzmann 2017-01-25 22:07:36 +01:00 committed by GitHub
commit 513b20ffd3
212 changed files with 5593 additions and 8269 deletions
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23
boards/airfy-beacon/include/periph_conf.h
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@ -1,9 +1,9 @@
/*
* Copyright (C) 2014 Christian Mehlis <mehlis@inf.fu-berlin.de>
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
@ -83,15 +83,16 @@ static const timer_conf_t timer_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
#define SPI_IRQ_PRIO 1
static const spi_conf_t spi_config[] = {
{
.dev = NRF_SPI0,
.sclk = 15,
.mosi = 13,
.miso = 14
}
};
/* SPI_0 device configuration */
#define SPI_0_DEV NRF_SPI0
#define SPI_0_PIN_MOSI 13
#define SPI_0_PIN_MISO 14
#define SPI_0_PIN_SCK 15
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

31
boards/arduino-due/include/periph_conf.h
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@ -88,27 +88,18 @@ static const uart_conf_t uart_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
.id = ID_SPI0,
.clk = GPIO_PIN(PA, 27),
.mosi = GPIO_PIN(PA, 26),
.miso = GPIO_PIN(PA, 25),
.mux = GPIO_MUX_A
}
};
/* SPI 0 device config */
#define SPI_0_DEV SPI0
#define SPI_0_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_SPI0));
#define SPI_0_CLKDIS() (PMC->PMC_PCER0 &= ~(1 << ID_SPI0));
#define SPI_0_IRQ SPI0_IRQn
#define SPI_0_IRQ_HANDLER isr_spi0
#define SPI_0_IRQ_PRIO 1
/* SPI 0 pin configuration */
#define SPI_0_MISO_PIN PIO_PA25A_SPI0_MISO
#define SPI_0_MOSI_PIN PIO_PA26A_SPI0_MOSI
#define SPI_0_SCK_PIN PIO_PA27A_SPI0_SPCK
#define SPI_0_MISO_PORT PIOA
#define SPI_0_MOSI_PORT PIOA
#define SPI_0_SCK_PORT PIOA
#define SPI_0_MISO_PORT_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_PIOA));
#define SPI_0_MOSI_PORT_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_PIOA));
#define SPI_0_SCK_PORT_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_PIOA));
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

79
boards/arduino-due/include/sdcard_spi_params.h Normal file
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@ -0,0 +1,79 @@
/*
* Copyright (C) 2017 Michel Rottleuthner <michel.rottleuthner@haw-hamburg.de>
* 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_arduino-due
* @{
*
* @file
* @brief SD card configuration for the Arduino due
*
* @author Michel Rottleuthner <michel.rottleuthner@haw-hamburg.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef SDCARD_SPI_PARAMS_H
#define SDCARD_SPI_PARAMS_H
#include "board.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Set default configuration parameters for the sdcard_spi driver
* @{
*/
#ifndef SDCARD_SPI_PARAM_SPI
#define SDCARD_SPI_PARAM_SPI (SPI_DEV(0))
#endif
#ifndef SDCARD_SPI_PARAM_CS
#define SDCARD_SPI_PARAM_CS (GPIO_PIN(PA, 29))
#endif
#ifndef SDCARD_SPI_PARAM_CLK
#define SDCARD_SPI_PARAM_CLK (GPIO_PIN(PA, 27))
#endif
#ifndef SDCARD_SPI_PARAM_MOSI
#define SDCARD_SPI_PARAM_MOSI (GPIO_PIN(PA, 26))
#endif
#ifndef SDCARD_SPI_PARAM_MISO
#define SDCARD_SPI_PARAM_MISO (GPIO_PIN(PA, 25))
#endif
#ifndef SDCARD_SPI_PARAM_POWER
#define SDCARD_SPI_PARAM_POWER (GPIO_UNDEF)
#endif
#ifndef SDCARD_SPI_PARAM_POWER_AH
/** treated as 'don't care' if SDCARD_SPI_PARAM_POWER is GPIO_UNDEF */
#define SDCARD_SPI_PARAM_POWER_AH (true)
#endif
/** @} */
/**
* @brief sdcard_spi configuration
*/
static const sdcard_spi_params_t sdcard_spi_params[] = {
{
.spi_dev = SDCARD_SPI_PARAM_SPI,
.cs = SDCARD_SPI_PARAM_CS,
.clk = SDCARD_SPI_PARAM_CLK,
.mosi = SDCARD_SPI_PARAM_MOSI,
.miso = SDCARD_SPI_PARAM_MISO,
.power = SDCARD_SPI_PARAM_POWER,
.power_act_high = SDCARD_SPI_PARAM_POWER_AH
},
};
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* SDCARD_SPI_PARAMS_H */
/** @} */

14
boards/arduino-due/include/w5100_params.h
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@ -28,10 +28,10 @@ extern "C" {
* @{
*/
#ifndef W5100_PARAM_SPI
#define W5100_PARAM_SPI (SPI_0)
#define W5100_PARAM_SPI (SPI_DEV(0))
#endif
#ifndef W5100_PARAM_SPI_SPEED
#define W5100_PARAM_SPI_SPEED (SPI_SPEED_5MHZ)
#ifndef W5100_PARAM_SPI_CLK
#define W5100_PARAM_SPI_CLK (SPI_CLK_5MHZ)
#endif
#ifndef W5100_PARAM_CS
#define W5100_PARAM_CS (GPIO_PIN(2, 29))
@ -46,10 +46,10 @@ extern "C" {
*/
static const w5100_params_t w5100_params[] = {
{
.spi = W5100_PARAM_SPI,
.spi_speed = W5100_PARAM_SPI_SPEED,
.cs = W5100_PARAM_CS,
.evt = W5100_PARAM_EVT
.spi = W5100_PARAM_SPI,
.clk = W5100_PARAM_SPI_CLK,
.cs = W5100_PARAM_CS,
.evt = W5100_PARAM_EVT
},
};
/** @} */

30
boards/arduino-zero/include/periph_conf.h
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@ -183,23 +183,21 @@ static const pwm_conf_t pwm_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (1)
#define SPI_0_EN 1
/* SPI0 */
#define SPI_0_DEV SERCOM4->SPI
#define SPI_IRQ_0 SERCOM4_IRQn
#define SPI_0_GCLK_ID SERCOM4_GCLK_ID_CORE
/* SPI 0 pin configuration */
#define SPI_0_SCLK GPIO_PIN(PB, 11)
#define SPI_0_SCLK_MUX GPIO_MUX_D
#define SPI_0_MISO GPIO_PIN(PA, 12)
#define SPI_0_MISO_MUX GPIO_MUX_D
#define SPI_0_MISO_PAD SPI_PAD_MISO_0
#define SPI_0_MOSI GPIO_PIN(PB, 10)
#define SPI_0_MOSI_MUX GPIO_MUX_D
#define SPI_0_MOSI_PAD SPI_PAD_MOSI_2_SCK_3
static const spi_conf_t spi_config[] = {
{
.dev = &SERCOM4->SPI,
.miso_pin = GPIO_PIN(PA, 12),
.mosi_pin = GPIO_PIN(PB, 10),
.clk_pin = GPIO_PIN(PB, 11),
.miso_mux = GPIO_MUX_D,
.mosi_mux = GPIO_MUX_D,
.clk_mux = GPIO_MUX_D,
.miso_pad = SPI_PAD_MISO_0,
.mosi_pad = SPI_PAD_MOSI_2_SCK_3
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

27
boards/cc2538dk/include/periph_conf.h
View File

@ -58,7 +58,6 @@ static const timer_conf_t timer_config[] = {
#define TIMER_IRQ_PRIO 1
/** @} */
/**
* @name UART configuration
* @{
@ -112,22 +111,36 @@ static const i2c_conf_t i2c_config[I2C_NUMOF] = {
};
/** @} */
/**
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**
* @name SPI configuration
* @{
*/
#define SPI_NUMOF 1
#define SPI_0_EN 1
static const periph_spi_conf_t spi_config[SPI_NUMOF] = {
static const spi_conf_t spi_config[] = {
{
.dev = SSI0,
.mosi_pin = GPIO_PA4,
.miso_pin = GPIO_PA5,
.sck_pin = GPIO_PA2,
.cs_pin = GPIO_PD0,
},
.cs_pin = GPIO_PD0
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

4
boards/fox/include/board.h
View File

@ -43,8 +43,8 @@ extern "C" {
*
* {spi bus, spi speed, cs pin, int pin, reset pin, sleep pin}
*/
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_0, \
.spi_speed = SPI_SPEED_5MHZ, \
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_DEV(0), \
.spi_clk = SPI_CLK_5MHZ, \
.cs_pin = GPIO_PIN(PORT_A, 1), \
.int_pin = GPIO_PIN(PORT_C, 2), \
.sleep_pin = GPIO_PIN(PORT_A, 0), \

45
boards/fox/include/periph_conf.h
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@ -115,21 +115,42 @@ static const uart_conf_t uart_config[] = {
/** @} */
/**
* @brief SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
/* SPI 0 device configuration */
#define SPI_0_DEV SPI2
#define SPI_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_0_BUS_DIV 0 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
/* SPI 0 pin configuration */
#define SPI_0_CLK_PIN GPIO_PIN(PORT_B,13)
#define SPI_0_MOSI_PIN GPIO_PIN(PORT_B,15)
#define SPI_0_MISO_PIN GPIO_PIN(PORT_B,14)
static const spi_conf_t spi_config[] = {
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

82
boards/frdm-k64f/include/periph_conf.h
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@ -147,35 +147,67 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
* @name SPI configuration
*
* Clock configuration values based on the configured 30Mhz module clock.
*
* Auto-generated by:
* cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
#define SPI_IRQ_PRIO 1
#define KINETIS_SPI_USE_HW_CS 1
static const uint32_t spi_clk_config[] = {
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) | /* -> 93750Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) | /* -> 375000Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | /* -> 1000000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 5000000Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 7500000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
)
};
/* SPI 0 device config */
#define SPI_0_DEV SPI0
#define SPI_0_INDEX 0
#define SPI_0_CTAS 0
#define SPI_0_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_SPI0_MASK))
#define SPI_0_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_SPI0_MASK))
#define SPI_0_IRQ SPI0_IRQn
#define SPI_0_IRQ_HANDLER isr_spi0
#define SPI_0_FREQ CLOCK_CORECLOCK
static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
.pin_miso = GPIO_PIN(PORT_D, 3),
.pin_mosi = GPIO_PIN(PORT_D, 2),
.pin_clk = GPIO_PIN(PORT_D, 1),
.pin_cs = {
GPIO_PIN(PORT_D, 0),
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF
},
.pcr = GPIO_AF_2,
.simmask = SIM_SCGC6_SPI0_MASK
}
};
/* SPI 0 pin configuration */
#define SPI_0_PORT PORTD
#define SPI_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
#define SPI_0_AF 2
#define SPI_0_PCS0_PIN 0
#define SPI_0_SCK_PIN 1
#define SPI_0_SOUT_PIN 2
#define SPI_0_SIN_PIN 3
#define SPI_0_PCS0_ACTIVE_LOW 1
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */

23
boards/iotlab-a8-m3/include/periph_conf.h
View File

@ -31,18 +31,19 @@ extern "C" {
* @brief SPI configuration
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
static const spi_conf_t spi_config[] = {
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
};
/* SPI 0 device configuration */
#define SPI_0_DEV SPI2
#define SPI_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
/* SPI 0 pin configuration */
#define SPI_0_CLK_PIN GPIO_PIN(PORT_B,13)
#define SPI_0_MISO_PIN GPIO_PIN(PORT_B,14)
#define SPI_0_MOSI_PIN GPIO_PIN(PORT_B,15)
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus

8
boards/iotlab-common/include/board_common.h
View File

@ -53,10 +53,10 @@ extern "C" {
*
* {spi bus, spi speed, cs pin, int pin, reset pin, sleep pin}
*/
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_0, \
.spi_speed = SPI_SPEED_5MHZ, \
.cs_pin = GPIO_PIN(PORT_A, 4), \
.int_pin = GPIO_PIN(PORT_C, 4), \
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_DEV(0), \
.spi_clk = SPI_CLK_5MHZ, \
.cs_pin = GPIO_PIN(PORT_A, 4), \
.int_pin = GPIO_PIN(PORT_C, 4), \
.sleep_pin = GPIO_PIN(PORT_A, 2), \
.reset_pin = GPIO_PIN(PORT_C, 1)}

23
boards/iotlab-common/include/periph_conf_common.h
View File

@ -159,6 +159,29 @@ static const uart_conf_t uart_config[] = {
#define I2C_0_SDA_PIN GPIO_PIN(PORT_B,7)
/** @} */
/**
* @brief Shared SPI clock div table
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
#ifdef __cplusplus
}
#endif

2
boards/iotlab-m3/include/board.h
View File

@ -38,7 +38,7 @@ extern "C" {
* @name Define the interface for the connected flash memory
* @{
*/
#define EXTFLASH_SPI SPI_1
#define EXTFLASH_SPI SPI_DEV(1)
#define EXTFLASH_CS GPIO_PIN(PORT_A,11)
#define EXTFLASH_WRITE GPIO_PIN(PORT_C,6)
#define EXTFLASH_HOLD GPIO_PIN(PORT_C,9)

31
boards/iotlab-m3/include/periph_conf.h
View File

@ -1,9 +1,9 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
* Copyright (C) 2014-2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
@ -31,18 +31,19 @@ extern "C" {
* @brief SPI configuration
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
/* SPI 0 device configuration */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
/* SPI 0 pin configuration */
#define SPI_0_CLK_PIN GPIO_PIN(PORT_A,5)
#define SPI_0_MOSI_PIN GPIO_PIN(PORT_A,7)
#define SPI_0_MISO_PIN GPIO_PIN(PORT_A,6)
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus

73
boards/limifrog-v1/include/periph_conf.h
View File

@ -109,40 +109,53 @@ static const uart_conf_t uart_config[] = {
/** @} */
/**
* @brief SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
/* SPI 0 device configuration */
#define SPI_0_DEV SPI1 /* Densitron DD-160128FC-1a OLED display; external pins */
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_ISR isr_spi1
/* SPI 0 pin configuration */
#define SPI_0_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
#define SPI_0_PORT GPIOA
#define SPI_0_PIN_SCK 5
#define SPI_0_PIN_MOSI 7
#define SPI_0_PIN_MISO 6
#define SPI_0_PIN_AF 5
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
{
.dev = SPI3,
.mosi_pin = GPIO_PIN(PORT_B, 5),
.miso_pin = GPIO_PIN(PORT_B, 4),
.sclk_pin = GPIO_PIN(PORT_B, 3),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF6,
.rccmask = RCC_APB1ENR_SPI3EN,
.apbbus = APB1
}
};
/* SPI 1 device configuration */
#define SPI_1_DEV SPI3 /* Adesto AT45DB641E data flash */
#define SPI_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_SPI3EN))
#define SPI_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_SPI3EN))
#define SPI_1_IRQ SPI3_IRQn
#define SPI_1_ISR isr_spi3
/* SPI 1 pin configuration */
#define SPI_1_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
#define SPI_1_PORT GPIOB
#define SPI_1_PIN_SCK 3
#define SPI_1_PIN_MOSI 5
#define SPI_1_PIN_MISO 4
#define SPI_1_PIN_AF 6
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

72
boards/maple-mini/include/periph_conf.h
View File

@ -163,39 +163,55 @@ static const uart_conf_t uart_config[] = {
#define I2C_1_SDA_PIN GPIO_PIN(PORT_B, 11) /* D0 */
/** @} */
/**
* @brief Shared SPI clock div table
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
/**
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 0
#define SPI_IRQ_PRIO 1
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
};
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
#define SPI_0_BUS_DIV 1
/* SPI 0 pin configuration */
#define SPI_0_CLK_PIN GPIO_PIN(PORT_A, 5) /* D6 */
#define SPI_0_MISO_PIN GPIO_PIN(PORT_A, 6) /* D5 */
#define SPI_0_MOSI_PIN GPIO_PIN(PORT_A, 7) /* D4 */
/* SPI 1 device config */
#define SPI_1_DEV SPI2
#define SPI_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_SPI2EN)
#define SPI_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN)
#define SPI_1_IRQ SPI2_IRQn
#define SPI_1_IRQ_HANDLER isr_spi2
#define SPI_1_BUS_DIV 1
/* SPI 1 pin configuration */
#define SPI_1_CLK_PIN GPIO_PIN(PORT_B, 13) /* D30 */
#define SPI_1_MISO_PIN GPIO_PIN(PORT_B, 14) /* D29 */
#define SPI_1_MOSI_PIN GPIO_PIN(PORT_B, 15) /* D28 */
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus

1
boards/msb-430/Makefile.features
View File

@ -1,6 +1,7 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_uart
# Various other features (if any)

2
boards/msb-430/include/periph_conf.h
View File

@ -75,7 +75,7 @@ extern "C" {
#define SPI_0_EN (1U)
/* SPI configuration */
#define SPI_DEV (USART_0)
#define SPI_BASE (USART_0)
#define SPI_IE (SFR->IE1)
#define SPI_IF (SFR->IFG1)
#define SPI_IE_RX_BIT (1 << 6)

2
boards/msb-430h/include/periph_conf.h
View File

@ -77,7 +77,7 @@ extern "C" {
#define SPI_0_EN (1U)
/* SPI configuration */
#define SPI_DEV (USART_0)
#define SPI_BASE (USART_0)
#define SPI_IE (SFR->IE1)
#define SPI_IF (SFR->IFG1)
#define SPI_IE_RX_BIT (1 << 6)

4
boards/msba2/include/periph_conf.h
View File

@ -82,10 +82,12 @@ extern "C" {
/**
* @brief SPI configuration
*
* The SPI implementation is very much fixed, so we don't need to configure
* anything besides the mandatory SPI_NUMOF.
* @{
*/
#define SPI_NUMOF (1)
#define SPI_0_EN (1)
/** @} */
#ifdef __cplusplus

2
boards/msbiot/include/board.h
View File

@ -32,7 +32,7 @@ extern "C" {
* @name Configure connected CC1101 (radio) device
* @{
*/
#define CC110X_SPI SPI_0
#define CC110X_SPI SPI_DEV(0)
#define CC110X_CS GPIO_PIN(PORT_B, 12)
#define CC110X_GDO0 GPIO_PIN(PORT_C, 4)
#define CC110X_GDO1 GPIO_PIN(PORT_A, 6)

59
boards/msbiot/include/periph_conf.h
View File

@ -187,34 +187,43 @@ static const uart_conf_t uart_config[] = {
/** @} */
/**
* @name SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF 1
#define SPI_0_EN 1
#define SPI_1_EN 0
#define SPI_IRQ_PRIO 1
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 42000000Hz */
7, /* -> 164062Hz */
6, /* -> 328125Hz */
4, /* -> 1312500Hz */
2, /* -> 5250000Hz */
1 /* -> 10500000Hz */
},
{ /* for APB2 @ 84000000Hz */
7, /* -> 328125Hz */
7, /* -> 328125Hz */
5, /* -> 1312500Hz */
3, /* -> 5250000Hz */
2 /* -> 10500000Hz */
}
};
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT GPIOA
#define SPI_0_SCK_PIN 5
#define SPI_0_SCK_AF 5
#define SPI_0_MISO_PORT GPIOA
#define SPI_0_MISO_PIN 6
#define SPI_0_MISO_AF 5
#define SPI_0_MOSI_PORT GPIOA
#define SPI_0_MOSI_PIN 7
#define SPI_0_MOSI_AF 5
#define SPI_0_SCK_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
#define SPI_0_MISO_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
#define SPI_0_MOSI_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_PIN(PORT_A, 4),
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

5
boards/mulle/board.c
View File

@ -34,6 +34,7 @@ static nvram_t mulle_nvram_dev;
nvram_t *mulle_nvram = &mulle_nvram_dev;
static nvram_spi_params_t nvram_spi_params = {
.spi = MULLE_NVRAM_SPI_DEV,
.clk = MULLE_NVRAM_SPI_CLK,
.cs = MULLE_NVRAM_SPI_CS,
.address_count = MULLE_NVRAM_SPI_ADDRESS_COUNT,
};
@ -184,10 +185,6 @@ static int mulle_nvram_init(void)
} rec;
rec.u32 = 0;
if (spi_init_master(MULLE_NVRAM_SPI_DEV, SPI_CONF_FIRST_RISING, SPI_SPEED_5MHZ) != 0) {
return -1;
}
if (nvram_spi_init(mulle_nvram, &nvram_spi_params, MULLE_NVRAM_CAPACITY) != 0) {
return -2;
}

30
boards/mulle/include/board.h
View File

@ -108,8 +108,8 @@ void board_init(void);
*
* {spi bus, spi speed, cs pin, int pin, reset pin, sleep pin}
*/
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_0, \
.spi_speed = SPI_SPEED_5MHZ, \
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_DEV(0), \
.spi_clk = SPI_CLK_5MHZ, \
.cs_pin = GPIO_PIN(PORT_D, 4), \
.int_pin = GPIO_PIN(PORT_B, 9), \
.sleep_pin = GPIO_PIN(PORT_E, 6), \
@ -121,31 +121,31 @@ void board_init(void);
* @{
*/
#define LIS3DH_INT1 GPIO_PIN(PORT_C, 18)
#define LIS3DH_INT2 GPIO_PIN(PORT_C, 17)
#define LIS3DH_CS GPIO_PIN(PORT_D, 0)
#define LIS3DH_SPI SPI_2
#define LIS3DH_INT1 GPIO_PIN(PORT_C, 18)
#define LIS3DH_INT2 GPIO_PIN(PORT_C, 17)
#define LIS3DH_CS GPIO_PIN(PORT_D, 0)
#define LIS3DH_CLK SPI_CLK_5MHZ
#define LIS3DH_SPI SPI_DEV(0)
/** @} */
/**
* @name Mulle power control configuration
*/
/** @{ */
#define MULLE_POWER_AVDD GPIO_PIN(PORT_B, 17) /**< AVDD enable pin */
#define MULLE_POWER_VPERIPH GPIO_PIN(PORT_D, 7) /**< VPERIPH enable pin */
#define MULLE_POWER_VSEC GPIO_PIN(PORT_B, 16) /**< VSEC enable pin */
#define MULLE_POWER_AVDD GPIO_PIN(PORT_B, 17) /**< AVDD enable pin */
#define MULLE_POWER_VPERIPH GPIO_PIN(PORT_D, 7) /**< VPERIPH enable pin */
#define MULLE_POWER_VSEC GPIO_PIN(PORT_B, 16) /**< VSEC enable pin */
/** @} */
/**
* @name Mulle NVRAM hardware configuration
*/
/** @{ */
/** FRAM SPI bus, SPI_2 in RIOT is mapped to hardware bus SPI0, see periph_conf.h */
#define MULLE_NVRAM_SPI_DEV SPI_2
#define MULLE_NVRAM_SPI_CS GPIO_PIN(PORT_D, 6) /**< FRAM CS pin */
#define MULLE_NVRAM_CAPACITY 512 /**< FRAM size, in bytes */
#define MULLE_NVRAM_SPI_ADDRESS_COUNT 1 /**< FRAM addressing size, in bytes */
#define MULLE_NVRAM_SPI_DEV SPI_DEV(0)
#define MULLE_NVRAM_SPI_CLK SPI_CLK_5MHZ
#define MULLE_NVRAM_SPI_CS GPIO_PIN(PORT_D, 6) /**< FRAM CS pin */
#define MULLE_NVRAM_CAPACITY 512 /**< FRAM size, in bytes */
#define MULLE_NVRAM_SPI_ADDRESS_COUNT 1 /**< FRAM addressing size, in bytes */
/** @} */
/**

1
boards/mulle/include/lis3dh_params.h
View File

@ -33,6 +33,7 @@ static const lis3dh_params_t lis3dh_params[] =
{
{
.spi = LIS3DH_SPI,
.clk = LIS3DH_CLK,
.cs = LIS3DH_CS,
.int1 = LIS3DH_INT1,
.int2 = LIS3DH_INT2,

229
boards/mulle/include/periph_conf.h
View File

@ -216,159 +216,83 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* Clock configuration values based on the configured 47988736Hz module clock.
*
* Auto-generated by:
* cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/
#define SPI_NUMOF 3
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_2_EN 1
#define SPI_3_EN 0
#define SPI_4_EN 0
#define SPI_5_EN 0
#define SPI_6_EN 0
#define SPI_7_EN 0
static const uint32_t spi_clk_config[] = {
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93728Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 374912Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 999765Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4798873Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 7998122Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
)
};
#define MULLE_PASTE_PARTS(left, index, right) MULLE_PASTE_PARTS2(left, index, right)
#define MULLE_PASTE_PARTS2(left, index, right) left##index##right
/* SPI 0 device config */
/* SPI_0 (in RIOT) is mapped to SPI0, CTAS=0 in hardware */
#define SPI_0_INDEX 0
#define SPI_0_CTAS 0
#define SPI_0_DEV MULLE_PASTE_PARTS(SPI, SPI_0_INDEX, )
#define SPI_0_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 1)
#define SPI_0_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
#define SPI_0_IRQ MULLE_PASTE_PARTS(SPI, SPI_0_INDEX, _IRQn)
#define SPI_0_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_0_INDEX, )
#define SPI_0_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
#define SPI_0_FREQ SystemBusClock
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT PORTD
#define SPI_0_SCK_PIN 1
#define SPI_0_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SCK_AF 2
#define SPI_0_SIN_PORT PORTD
#define SPI_0_SIN_PIN 3
#define SPI_0_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SIN_AF 2
#define SPI_0_SOUT_PORT PORTD
#define SPI_0_SOUT_PIN 2
#define SPI_0_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SOUT_AF 2
#define SPI_0_PCS0_PORT PORTD
#define SPI_0_PCS0_PIN 0
#define SPI_0_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_0_PCS0_ACTIVE_LOW 1
#define SPI_0_PCS1_ACTIVE_LOW 1
#define SPI_0_PCS2_ACTIVE_LOW 1
#define SPI_0_PCS3_ACTIVE_LOW 1
/* SPI 1 device config */
/* SPI_1 (in RIOT) is mapped to SPI1, CTAS=0 in hardware */
#define SPI_1_INDEX 1
#define SPI_1_CTAS 0
#define SPI_1_DEV MULLE_PASTE_PARTS(SPI, SPI_1_INDEX, )
#define SPI_1_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 1)
#define SPI_1_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 0)
#define SPI_1_IRQ MULLE_PASTE_PARTS(SPI, SPI_1_INDEX, _IRQn)
#define SPI_1_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_1_INDEX, )
#define SPI_1_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
#define SPI_1_FREQ SystemBusClock
/* SPI 0 pin configuration */
#define SPI_1_SCK_PORT PORTE
#define SPI_1_SCK_PIN 2
#define SPI_1_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SCK_AF 2
#define SPI_1_SIN_PORT PORTE
#define SPI_1_SIN_PIN 3
#define SPI_1_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SIN_AF 2
#define SPI_1_SOUT_PORT PORTE
#define SPI_1_SOUT_PIN 1
#define SPI_1_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SOUT_AF 2
#define SPI_1_PCS0_PORT PORTE
#define SPI_1_PCS0_PIN 4
#define SPI_1_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_1_PCS0_ACTIVE_LOW 1
#define SPI_1_PCS1_ACTIVE_LOW 1
#define SPI_1_PCS2_ACTIVE_LOW 1
#define SPI_1_PCS3_ACTIVE_LOW 1
/* SPI 2 device config */
/* SPI_2 (in RIOT) is mapped to SPI0, CTAS=1 in hardware */
#define SPI_2_INDEX 0
#define SPI_2_CTAS 1
#define SPI_2_DEV MULLE_PASTE_PARTS(SPI, SPI_2_INDEX, )
#define SPI_2_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 1)
#define SPI_2_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
#define SPI_2_IRQ MULLE_PASTE_PARTS(SPI, SPI_2_INDEX, _IRQn)
/* #define SPI_2_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_2_INDEX, ) */
#define SPI_2_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
#define SPI_2_FREQ SystemBusClock
/* SPI 2 pin configuration, must be the same as the other RIOT device using this
* hardware module */
#define SPI_2_SCK_PORT PORTD
#define SPI_2_SCK_PIN 1
#define SPI_2_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SCK_AF 2
#define SPI_2_SIN_PORT PORTD
#define SPI_2_SIN_PIN 3
#define SPI_2_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SIN_AF 2
#define SPI_2_SOUT_PORT PORTD
#define SPI_2_SOUT_PIN 2
#define SPI_2_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SOUT_AF 2
#define SPI_2_PCS0_PORT PORTD
#define SPI_2_PCS0_PIN 0
#define SPI_2_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_2_PCS0_ACTIVE_LOW 1
#define SPI_2_PCS1_ACTIVE_LOW 1
#define SPI_2_PCS2_ACTIVE_LOW 1
#define SPI_2_PCS3_ACTIVE_LOW 1
/**
* @name SPI delay timing configuration
* @{ */
/* These values are necessary for communicating with the AT86RF212B when running
* the MCU core at high clock frequencies. */
/* NB: The given values are the reciprocals of the time, in order to compute the
* scalers using only integer math. */
#define SPI_0_TCSC_FREQ (5555555) /* It looks silly, but this is correct. 1/180e-9 */
#define SPI_0_TASC_FREQ (5454545) /* It looks silly, but this is correct. 1/183e-9 */
#define SPI_0_TDT_FREQ (4000000) /* 1/250e-9 */
/* SPI_1 timings */
#define SPI_1_TCSC_FREQ (0)
#define SPI_1_TASC_FREQ (0)
#define SPI_1_TDT_FREQ (0)
/* SPI_2 timings */
#define SPI_2_TCSC_FREQ (0)
#define SPI_2_TASC_FREQ (0)
#define SPI_2_TDT_FREQ (0)
static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
.pin_miso = GPIO_PIN(PORT_D, 3),
.pin_mosi = GPIO_PIN(PORT_D, 2),
.pin_clk = GPIO_PIN(PORT_D, 1),
.pin_cs = {
GPIO_PIN(PORT_D, 0),
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF
},
.pcr = GPIO_AF_2,
.simmask = SIM_SCGC6_SPI0_MASK
},
{
.dev = SPI1,
.pin_miso = GPIO_PIN(PORT_E, 3),
.pin_mosi = GPIO_PIN(PORT_E, 1),
.pin_clk = GPIO_PIN(PORT_E, 2),
.pin_cs = {
GPIO_PIN(PORT_E, 4),
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF
},
.pcr = GPIO_AF_2,
.simmask = SIM_SCGC6_SPI1_MASK
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/** @} */
/**
* @name I2C configuration
* @{
*/
#define I2C_NUMOF (1U)
#define I2C_CLK SystemBusClock
#define I2C_0_EN 1
#define I2C_1_EN 0
#define I2C_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
/**
* @name I2C baud rate configuration
* @{
@ -387,6 +311,16 @@ static const pwm_conf_t pwm_config[] = {
#define KINETIS_I2C_F_MULT_FAST_PLUS (0)
/** @} */
/**
* @name I2C configuration
* @{
*/
#define I2C_NUMOF (1U)
#define I2C_CLK SystemBusClock
#define I2C_0_EN 1
#define I2C_1_EN 0
#define I2C_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
/* I2C 0 device configuration */
#define I2C_0_DEV I2C0
#define I2C_0_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 1)
@ -402,7 +336,6 @@ static const pwm_conf_t pwm_config[] = {
#define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
/** @} */
/**
* @name GPIO configuration
* @{

1
boards/nrf52dk/Makefile.features
View File

@ -4,6 +4,7 @@ FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_hwrng
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart

15
boards/nrf52dk/include/periph_conf.h
View File

@ -74,6 +74,21 @@ static const timer_conf_t timer_config[] = {
#define UART_PIN_TX 6
/** @} */
/**
* @name SPI configuration
* @{
*/
static const spi_conf_t spi_config[] = {
{
.dev = NRF_SPI0,
.sclk = 15,
.mosi = 13,
.miso = 14 }
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus
}
#endif

30
boards/nrf6310/include/periph_conf.h
View File

@ -100,22 +100,22 @@ static const timer_conf_t timer_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_IRQ_PRIO 1
static const spi_conf_t spi_config[] = {
{
.dev = NRF_SPI0,
.sclk = 23,
.mosi = 22,
.miso = 20
},
{
.dev = NRF_SPI1,
.sclk = 16,
.mosi = 17,
.miso = 18
}
};
/* SPI Master 0 pin configuration */
#define SPI_0_DEV NRF_SPI0
#define SPI_0_PIN_SCK 23
#define SPI_0_PIN_MISO 22
#define SPI_0_PIN_MOSI 20
/* SPI Master 1 pin configuration */
#define SPI_1_DEV NRF_SPI1
#define SPI_1_PIN_SCK 16
#define SPI_1_PIN_MISO 17
#define SPI_1_PIN_MOSI 18
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

1
boards/nucleo-f072/Makefile.features
View File

@ -6,6 +6,7 @@ FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_spi
# load the common Makefile.features for Nucleo boards
include $(RIOTBOARD)/nucleo-common/Makefile.features

40
boards/nucleo-f072/include/periph_conf.h
View File

@ -161,6 +161,46 @@ static const pwm_conf_t pwm_config[] = {
#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
/** @} */
/**
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_PIN(PORT_A, 4),
.af = GPIO_AF0,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**
* @brief ADC configuration
* @{

1
boards/nucleo-f091/Makefile.features
View File

@ -6,6 +6,7 @@ FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_spi
# load the common Makefile.features for Nucleo boards
include $(RIOTBOARD)/nucleo-common/Makefile.features

42
boards/nucleo-f091/include/periph_conf.h
View File

@ -104,6 +104,48 @@ static const uart_conf_t uart_config[] = {
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_PIN(PORT_B, 6),
.af = GPIO_AF0,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**
* @brief PWM configuration
* @{

69
boards/nucleo-f103/include/periph_conf.h
View File

@ -160,38 +160,51 @@ static const uart_conf_t uart_config[] = {
/** @} */
/**
* @name SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 0
#define SPI_IRQ_PRIO 1
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
#define SPI_0_BUS_DIV 1
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
};
/* SPI 0 pin configuration */
#define SPI_0_CLK_PIN GPIO_PIN(PORT_A, 5)
#define SPI_0_MISO_PIN GPIO_PIN(PORT_A, 6)
#define SPI_0_MOSI_PIN GPIO_PIN(PORT_A, 7)
/* SPI 1 device config */
#define SPI_1_DEV SPI2
#define SPI_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_1_IRQ SPI2_IRQn
#define SPI_1_IRQ_HANDLER isr_spi2
#define SPI_1_BUS_DIV 1
/* SPI 1 pin configuration */
#define SPI_1_CLK_PIN GPIO_PIN(PORT_B, 13)
#define SPI_1_MISO_PIN GPIO_PIN(PORT_B, 14)
#define SPI_1_MOSI_PIN GPIO_PIN(PORT_B, 15)
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus

91
boards/nucleo-f207/include/periph_conf.h
View File

@ -167,58 +167,55 @@ static const uart_conf_t uart_config[] = {
/** @} */
/**
* @name SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_IRQ_PRIO 1
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 30000000Hz */
7, /* -> 117187Hz */
5, /* -> 468750Hz */
4, /* -> 937500Hz */
2, /* -> 3750000Hz */
1 /* -> 7500000Hz */
},
{ /* for APB2 @ 60000000Hz */
7, /* -> 234375Hz */
6, /* -> 468750Hz */
5, /* -> 937500Hz */
3, /* -> 3750000Hz */
2 /* -> 7500000Hz */
}
};
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_BUS_DIV 1 /* 1 -> SPI bus runs with half CPU clock, 0 -> quarter CPU clock */
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT GPIOA /* A5 pin is shared with the green LED. */
#define SPI_0_SCK_PIN 5
#define SPI_0_SCK_AF 5
#define SPI_0_SCK_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
#define SPI_0_MISO_PORT GPIOA
#define SPI_0_MISO_PIN 6
#define SPI_0_MISO_AF 5
#define SPI_0_MISO_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
#define SPI_0_MOSI_PORT GPIOA
#define SPI_0_MOSI_PIN 7
#define SPI_0_MOSI_AF 5
#define SPI_0_MOSI_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_PIN(PORT_A, 4),
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_C, 2),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_PIN(PORT_B, 12),
.af = GPIO_AF5,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
};
/* SPI 1 device config */
#define SPI_1_DEV SPI2
#define SPI_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_1_BUS_DIV 0 /* 1 -> SPI bus runs with half CPU clock, 0 -> quarter CPU clock */
#define SPI_1_IRQ SPI2_IRQn
#define SPI_1_IRQ_HANDLER isr_spi2
/* SPI 1 pin configuration */
#define SPI_1_SCK_PORT GPIOB
#define SPI_1_SCK_PIN 3
#define SPI_1_SCK_AF 5
#define SPI_1_SCK_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
#define SPI_1_MISO_PORT GPIOB
#define SPI_1_MISO_PIN 4
#define SPI_1_MISO_AF 5
#define SPI_1_MISO_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
#define SPI_1_MOSI_PORT GPIOB
#define SPI_1_MOSI_PIN 5
#define SPI_1_MOSI_AF 5
#define SPI_1_MOSI_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**
* @name I2C configuration
* @{
@ -258,7 +255,7 @@ static const uart_conf_t uart_config[] = {
*/
#define ADC_CONFIG { \
{GPIO_PIN(PORT_A, 4), 0, 0}, \
{GPIO_PIN(PORT_A, 5), 1, 0} \
{GPIO_PIN(PORT_C, 0), 1, 0} \
}
#define ADC_NUMOF (2)

86
boards/nucleo-f303/include/periph_conf.h
View File

@ -138,53 +138,53 @@ static const pwm_conf_t pwm_config[] = {
/** @} */
/**
* @name SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_IRQ_PRIO 1
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT GPIOA
#define SPI_0_SCK_PIN 5
#define SPI_0_SCK_AF 5
#define SPI_0_SCK_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
#define SPI_0_MISO_PORT GPIOA
#define SPI_0_MISO_PIN 6
#define SPI_0_MISO_AF 5
#define SPI_0_MISO_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
#define SPI_0_MOSI_PORT GPIOA
#define SPI_0_MOSI_PIN 7
#define SPI_0_MOSI_AF 5
#define SPI_0_MOSI_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_PIN(PORT_A, 4),
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_C, 12),
.miso_pin = GPIO_PIN(PORT_C, 11),
.sclk_pin = GPIO_PIN(PORT_C, 10),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF6,
.rccmask = RCC_APB1ENR_SPI3EN,
.apbbus = APB1
}
};
/* SPI 1 device config */
#define SPI_1_DEV SPI3
#define SPI_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_SPI3EN))
#define SPI_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_SPI3EN))
#define SPI_1_IRQ SPI3_IRQn
#define SPI_1_IRQ_HANDLER isr_spi3
/* SPI 1 pin configuration */
#define SPI_1_SCK_PORT GPIOC
#define SPI_1_SCK_PIN 10
#define SPI_1_SCK_AF 6
#define SPI_1_SCK_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOCEN))
#define SPI_1_MISO_PORT GPIOC
#define SPI_1_MISO_PIN 11
#define SPI_1_MISO_AF 6
#define SPI_1_MISO_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOCEN))
#define SPI_1_MOSI_PORT GPIOC
#define SPI_1_MOSI_PIN 12
#define SPI_1_MOSI_AF 6
#define SPI_1_MOSI_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOCEN))
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

57
boards/nucleo-f334/include/periph_conf.h
View File

@ -122,32 +122,43 @@ static const pwm_conf_t pwm_config[] = {
/** @} */
/**
* @name SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
#define SPI_IRQ_PRIO 1
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT GPIOA
#define SPI_0_SCK_PIN 5
#define SPI_0_SCK_AF 5
#define SPI_0_SCK_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
#define SPI_0_MISO_PORT GPIOA
#define SPI_0_MISO_PIN 6
#define SPI_0_MISO_AF 5
#define SPI_0_MISO_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
#define SPI_0_MOSI_PORT GPIOA
#define SPI_0_MOSI_PIN 7
#define SPI_0_MOSI_AF 5
#define SPI_0_MOSI_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus

58
boards/nucleo-f401/include/periph_conf.h
View File

@ -141,33 +141,43 @@ static const pwm_conf_t pwm_config[] = {
/** @} */
/**
* @name SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
#define SPI_IRQ_PRIO 1
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 42000000Hz */
7, /* -> 164062Hz */
6, /* -> 328125Hz */
4, /* -> 1312500Hz */
2, /* -> 5250000Hz */
1 /* -> 10500000Hz */
},
{ /* for APB2 @ 84000000Hz */
7, /* -> 328125Hz */
7, /* -> 328125Hz */
5, /* -> 1312500Hz */
3, /* -> 5250000Hz */
2 /* -> 10500000Hz */
}
};
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_BUS_DIV 1 /* 1 -> SPI bus runs with half CPU clock, 0 -> quarter CPU clock */
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT GPIOA /* A5 pin is shared with the green LED. */
#define SPI_0_SCK_PIN 5
#define SPI_0_SCK_AF 5
#define SPI_0_SCK_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
#define SPI_0_MISO_PORT GPIOA
#define SPI_0_MISO_PIN 6
#define SPI_0_MISO_AF 5
#define SPI_0_MISO_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
#define SPI_0_MOSI_PORT GPIOA
#define SPI_0_MOSI_PIN 7
#define SPI_0_MOSI_AF 5
#define SPI_0_MOSI_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_PIN(PORT_A, 4),
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */

58
boards/nucleo-f446/include/periph_conf.h
View File

@ -167,33 +167,43 @@ static const pwm_conf_t pwm_config[] = {
/** @} */
/**
* @name SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
#define SPI_IRQ_PRIO 1
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 90000000Hz */
7, /* -> 351562Hz */
7, /* -> 351562Hz */
6, /* -> 703125Hz */
3, /* -> 5625000Hz */
2 /* -> 11250000Hz */
},
{ /* for APB2 @ 180000000Hz */
7, /* -> 703125Hz */
7, /* -> 703125Hz */
7, /* -> 703125Hz */
4, /* -> 5625000Hz */
3 /* -> 11250000Hz */
}
};
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_BUS_DIV 1 /* 1 -> SPI bus runs with half CPU clock, 0 -> quarter CPU clock */
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT GPIOA /* A5 pin is shared with the green LED. */
#define SPI_0_SCK_PIN 5
#define SPI_0_SCK_AF 5
#define SPI_0_SCK_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
#define SPI_0_MISO_PORT GPIOA
#define SPI_0_MISO_PIN 6
#define SPI_0_MISO_AF 5
#define SPI_0_MISO_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
#define SPI_0_MOSI_PORT GPIOA
#define SPI_0_MOSI_PIN 7
#define SPI_0_MOSI_AF 5
#define SPI_0_MOSI_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_PIN(PORT_A, 4),
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */

56
boards/nucleo-l1/include/periph_conf.h
View File

@ -1,9 +1,9 @@
/*
* Copyright (C) 2014-2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
@ -105,25 +105,43 @@ static const uart_conf_t uart_config[] = {
/** @} */
/**
* @brief SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
/* SPI 0 device configuration */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_ISR isr_spi1
/* SPI 0 pin configuration */
#define SPI_0_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
#define SPI_0_PORT GPIOA
#define SPI_0_PIN_SCK 5
#define SPI_0_PIN_MOSI 7
#define SPI_0_PIN_MISO 6
#define SPI_0_PIN_AF 5
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

7
boards/opencm9-04/include/periph_conf.h
View File

@ -135,13 +135,6 @@ static const uart_conf_t uart_config[] = {
#define I2C_NUMOF (0)
/** @} */
/**
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (0)
/** @} */
#ifdef __cplusplus
}
#endif

24
boards/openmote-cc2538/include/periph_conf.h
View File

@ -30,7 +30,7 @@
* @name Clock system configuration
* @{
*/
#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency, 32MHz */
#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency, 32MHz */
/** @} */
/**
@ -104,14 +104,26 @@ static const i2c_conf_t i2c_config[I2C_NUMOF] = {
};
/** @} */
/**
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**
* @name SPI configuration
* @{
*/
#define SPI_NUMOF 1
#define SPI_0_EN 1
static const periph_spi_conf_t spi_config[SPI_NUMOF] = {
static const spi_conf_t spi_config[] = {
{
.dev = SSI0,
.mosi_pin = GPIO_PA5,
@ -120,6 +132,8 @@ static const periph_spi_conf_t spi_config[SPI_NUMOF] = {
.cs_pin = GPIO_PA3,
},
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

4
boards/pba-d-01-kw2x/include/board.h
View File

@ -68,10 +68,10 @@ extern "C"
@name KW2XRF configuration
@{
*/
#define KW2XRF_SPI (SPI_1)
#define KW2XRF_SPI (SPI_DEV(1))
#define KW2XRF_CS (GPIO_PIN(KW2XDRF_PORT, KW2XDRF_PCS0_PIN))
#define KW2XRF_INT (GPIO_PIN(KW2XDRF_PORT, KW2XDRF_IRQ_PIN))
#define KW2XRF_SPI_SPEED (SPI_SPEED_10MHZ)
#define KW2XRF_SPI_SPEED (SPI_CLK_10MHZ)
#define KW2XRF_SHARED_SPI 0
/** @}*/

121
boards/pba-d-01-kw2x/include/periph_conf.h
View File

@ -163,59 +163,82 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
* @name SPI device configuration
*
* Clock configuration values based on the configured 48Mhz module clock.
*
* Auto-generated by:
* cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_IRQ_PRIO 1
#define KINETIS_SPI_USE_HW_CS 1
static const uint32_t spi_clk_config[] = {
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
)
};
/* SPI 0 device config */
#define SPI_0_DEV SPI0
#define SPI_0_INDEX 0
#define SPI_0_CTAS 0
#define SPI_0_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_SPI0_MASK))
#define SPI_0_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_SPI0_MASK))
#define SPI_0_IRQ SPI0_IRQn
#define SPI_0_IRQ_HANDLER isr_spi0
#define SPI_0_FREQ (48e6)
/* SPI 0 pin configuration */
#define SPI_0_PORT PORTC
#define SPI_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
#define SPI_0_AF 2
#define SPI_0_PCS0_PIN 4
#define SPI_0_SCK_PIN 5
#define SPI_0_SOUT_PIN 6
#define SPI_0_SIN_PIN 7
#define SPI_0_PCS0_ACTIVE_LOW 1
/* SPI 1 device config */
#define SPI_1_DEV SPI1
#define SPI_1_INDEX 1
#define SPI_1_CTAS 0
#define SPI_1_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_SPI1_MASK))
#define SPI_1_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_SPI1_MASK))
#define SPI_1_IRQ SPI1_IRQn
#define SPI_1_IRQ_HANDLER isr_spi1
#define SPI_1_FREQ (48e6)
/* SPI 1 pin1configuration */
#define SPI_1_PORT KW2XDRF_PORT_DEV
#define SPI_1_PORT_CLKEN() KW2XDRF_PORT_CLKEN();
#define SPI_1_AF KW2XDRF_PIN_AF
#define SPI_1_PCS0_PIN KW2XDRF_PCS0_PIN
#define SPI_1_SCK_PIN KW2XDRF_SCK_PIN
#define SPI_1_SOUT_PIN KW2XDRF_SOUT_PIN
#define SPI_1_SIN_PIN KW2XDRF_SIN_PIN
#define SPI_1_PCS0_ACTIVE_LOW 1
static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
.pin_miso = GPIO_PIN(PORT_C, 7),
.pin_mosi = GPIO_PIN(PORT_C, 6),
.pin_clk = GPIO_PIN(PORT_C, 5),
.pin_cs = {
GPIO_PIN(PORT_C, 4),
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF
},
.simmask = SIM_SCGC6_SPI0_MASK,
.pcr = GPIO_AF_2
},
{
.dev = SPI1,
.pin_miso = GPIO_PIN(PORT_B, 17),
.pin_mosi = GPIO_PIN(PORT_B, 16),
.pin_clk = GPIO_PIN(PORT_B, 11),
.pin_cs = {
GPIO_PIN(PORT_B, 10),
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF
},
.simmask = SIM_SCGC6_SPI1_MASK,
.pcr = GPIO_AF_2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */

30
boards/pca10005/include/periph_conf.h
View File

@ -83,22 +83,22 @@ static const timer_conf_t timer_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_IRQ_PRIO 1
static const spi_conf_t spi_config[] = {
{
.dev = NRF_SPI0,
.sclk = 19,
.mosi = 17,
.miso = 18
},
{
.dev = NRF_SPI1,
.sclk = 22,
.mosi = 20,
.miso = 21
}
};
/* SPI_0 device configuration */
#define SPI_0_DEV NRF_SPI0
#define SPI_0_PIN_MOSI 17
#define SPI_0_PIN_MISO 18
#define SPI_0_PIN_SCK 19
/* SPI_1 device configuration */
#define SPI_1_DEV NRF_SPI1
#define SPI_1_PIN_MOSI 20
#define SPI_1_PIN_MISO 21
#define SPI_1_PIN_SCK 22
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

1
boards/remote-common/include/periph_common.h
View File

@ -21,7 +21,6 @@
#ifndef PERIPH_COMMON_H
#define PERIPH_COMMON_H
#include "cc2538_gpio.h"
#include "periph_cpu.h"
#ifdef __cplusplus

7
boards/remote-pa/include/board.h
View File

@ -24,8 +24,6 @@
#define BOARD_H
#include "cpu.h"
#include "periph/gpio.h"
#include "board_common.h"
#ifdef __cplusplus
extern "C" {
@ -74,6 +72,11 @@
#define RF_SWITCH_TOGGLE (RF_SWITCH_PORT->DATA ^= (1 << RF_SWITCH_PIN))
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
} /* end extern "C" */
#endif

42
boards/remote-pa/include/periph_conf.h
View File

@ -1,10 +1,10 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
* Copyright (C) 2015 Zolertia SL
* Copyright (C) 2014-2016 Freie Universität Berlin
* 2015 Zolertia SL
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
@ -15,14 +15,12 @@
* @brief Peripheral MCU configuration for the Re-Mote board prototype A
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* Antonio Lignan <alinan@zolertia.com>
* @author Antonio Lignan <alinan@zolertia.com>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "cc2538_gpio.h"
#include "periph_cpu.h"
#include "periph_common.h"
#ifdef __cplusplus
@ -70,29 +68,43 @@ static const i2c_conf_t i2c_config[I2C_NUMOF] = {
};
/** @} */
/**
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**
* @name SPI configuration
* @{
*/
#define SPI_NUMOF 2
#define SPI_0_EN 1
#define SPI_1_EN 1
static const periph_spi_conf_t spi_config[SPI_NUMOF] = {
static const spi_conf_t spi_config[] = {
{
.dev = SSI0,
.mosi_pin = GPIO_PD0,
.miso_pin = GPIO_PC4,
.sck_pin = GPIO_PD1,
.cs_pin = GPIO_PD3,
.cs_pin = GPIO_PD3
},
{
.dev = SSI1,
.mosi_pin = GPIO_PC7,
.miso_pin = GPIO_PA4,
.sck_pin = GPIO_PB5,
},
.cs_pin = GPIO_UNDEF
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus

8
boards/remote-reva/include/board.h
View File

@ -23,9 +23,6 @@
#define BOARD_H
#include "cpu.h"
#include "periph/gpio.h"
#include "periph/spi.h"
#include "board_common.h"
#ifdef __cplusplus
extern "C" {
@ -111,6 +108,11 @@
#define CC1200_GPD2_GPIO GPIO_PB0
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
} /* end extern "C" */
#endif

43
boards/remote-reva/include/periph_conf.h
View File

@ -1,10 +1,10 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
* Copyright (C) 2015 Zolertia SL
* Copyright (C) 2014-2016 Freie Universität Berlin
* 2015 Zolertia SL
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
@ -15,14 +15,12 @@
* @brief Peripheral MCU configuration for the RE-Mote board revision A
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* Antonio Lignan <alinan@zolertia.com>
* @author Antonio Lignan <alinan@zolertia.com>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "cc2538_gpio.h"
#include "periph_cpu.h"
#include "periph_common.h"
#ifdef __cplusplus
@ -70,30 +68,43 @@ static const i2c_conf_t i2c_config[I2C_NUMOF] = {
};
/** @} */
/**
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**
* @name SPI configuration
* @{
*/
#define SPI_NUMOF 2
#define SPI_0_EN 1
#define SPI_1_EN 1
static const periph_spi_conf_t spi_config[SPI_NUMOF] = {
static const spi_conf_t spi_config[] = {
{
.dev = SSI0,
.mosi_pin = GPIO_PB1,
.miso_pin = GPIO_PB3,
.sck_pin = GPIO_PB2,
.cs_pin = GPIO_PB5,
.cs_pin = GPIO_PB5
},
{
.dev = SSI1,
.mosi_pin = GPIO_PC5,
.miso_pin = GPIO_PC6,
.sck_pin = GPIO_PC4,
.cs_pin = GPIO_PA7,
},
.cs_pin = GPIO_PA7
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus

10
boards/remote-revb/include/board.h
View File

@ -23,9 +23,6 @@
#define BOARD_H
#include "cpu.h"
#include "periph/gpio.h"
#include "periph/spi.h"
#include "board_common.h"
#ifdef __cplusplus
extern "C" {
@ -114,7 +111,7 @@
* @name Onboard micro-sd slot pin definitions
* @{
*/
#define SDCARD_SPI_PARAM_SPI SPI_1
#define SDCARD_SPI_PARAM_SPI SPI_DEV(1)
#define SDCARD_SPI_PARAM_CS GPIO_PIN(0,7)
#define SDCARD_SPI_PARAM_CLK GPIO_PIN(2,4)
#define SDCARD_SPI_PARAM_MOSI GPIO_PIN(2,5)
@ -123,6 +120,11 @@
#define SDCARD_SPI_PARAM_POWER_AH false
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
} /* end extern "C" */
#endif

29
boards/remote-revb/include/periph_conf.h
View File

@ -70,30 +70,43 @@ static const i2c_conf_t i2c_config[I2C_NUMOF] = {
};
/** @} */
/**
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**
* @name SPI configuration
* @{
*/
#define SPI_NUMOF 2
#define SPI_0_EN 1
#define SPI_1_EN 1
static const periph_spi_conf_t spi_config[SPI_NUMOF] = {
static const spi_conf_t spi_config[] = {
{
.dev = SSI0,
.mosi_pin = GPIO_PB1,
.miso_pin = GPIO_PB3,
.sck_pin = GPIO_PB2,
.cs_pin = GPIO_PB5,
.cs_pin = GPIO_PB5
},
{
.dev = SSI1,
.mosi_pin = GPIO_PC5,
.miso_pin = GPIO_PC6,
.sck_pin = GPIO_PC4,
.cs_pin = GPIO_PA7,
},
.cs_pin = GPIO_PA7
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus

27
boards/saml21-xpro/include/periph_conf.h
View File

@ -1,7 +1,7 @@
/*
* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
* 2015 FreshTemp, LLC.
* 2014 Freie Universität Berlin
* 2014-2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -16,12 +16,15 @@
* @brief Peripheral MCU configuration for the Atmel SAM L21 Xplained Pro board
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
* @autor Kaspar Schleiser <kaspar@schleiser.de>
* @author Kaspar Schleiser <kaspar@schleiser.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -29,7 +32,7 @@ extern "C" {
/**
* @brief GCLK reference speed
*/
#define GCLK_REF (16000000U)
#define CLOCK_CORECLOCK (16000000U)
/**
* @name Timer peripheral configuration
@ -71,8 +74,22 @@ extern "C" {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (1)
#define SPI_0_EN 1
static const spi_conf_t spi_config[] = {
{
.dev = &(SERCOM0->SPI),
.miso_pin = GPIO_PIN(PA, 4),
.mosi_pin = GPIO_PIN(PA, 6),
.clk_pin = GPIO_PIN(PA, 7),
.miso_mux = GPIO_MUX_D,
.mosi_mux = GPIO_MUX_D,
.clk_mux = GPIO_MUX_D,
.miso_pad = SPI_PAD_MISO_0,
.mosi_pad = SPI_PAD_MOSI_2_SCK_3
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

4
boards/samr21-xpro/include/board.h
View File

@ -43,8 +43,8 @@ extern "C" {
*
* {spi bus, spi speed, cs pin, int pin, reset pin, sleep pin}
*/
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_0, \
.spi_speed = SPI_SPEED_5MHZ, \
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_DEV(0), \
.spi_clk = SPI_CLK_5MHZ, \
.cs_pin = GPIO_PIN(PB, 31), \
.int_pin = GPIO_PIN(PB, 0), \
.sleep_pin = GPIO_PIN(PA, 20), \

55
boards/samr21-xpro/include/periph_conf.h
View File

@ -168,37 +168,32 @@ static const pwm_conf_t pwm_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (2)
#define SPI_0_EN 1
#define SPI_1_EN 1
static const spi_conf_t spi_config[] = {
{
.dev = &SERCOM4->SPI,
.miso_pin = GPIO_PIN(PC, 19),
.mosi_pin = GPIO_PIN(PB, 30),
.clk_pin = GPIO_PIN(PC, 18),
.miso_mux = GPIO_MUX_F,
.mosi_mux = GPIO_MUX_F,
.clk_mux = GPIO_MUX_F,
.miso_pad = SPI_PAD_MISO_0,
.mosi_pad = SPI_PAD_MOSI_2_SCK_3
},
{
.dev = &SERCOM5->SPI,
.miso_pin = GPIO_PIN(PB, 2),
.mosi_pin = GPIO_PIN(PB, 22),
.clk_pin = GPIO_PIN(PB, 23),
.miso_mux = GPIO_MUX_D,
.mosi_mux = GPIO_MUX_D,
.clk_mux = GPIO_MUX_D,
.miso_pad = SPI_PAD_MISO_0,
.mosi_pad = SPI_PAD_MOSI_2_SCK_3
}
};
/* SPI0 */
#define SPI_0_DEV SERCOM4->SPI
#define SPI_IRQ_0 SERCOM4_IRQn
#define SPI_0_GCLK_ID SERCOM4_GCLK_ID_CORE
/* SPI 0 pin configuration */
#define SPI_0_SCLK GPIO_PIN(PC, 18)
#define SPI_0_SCLK_MUX GPIO_MUX_F
#define SPI_0_MISO GPIO_PIN(PC, 19)
#define SPI_0_MISO_MUX GPIO_MUX_F
#define SPI_0_MISO_PAD SPI_PAD_MISO_0
#define SPI_0_MOSI GPIO_PIN(PB, 30)
#define SPI_0_MOSI_MUX GPIO_MUX_F
#define SPI_0_MOSI_PAD SPI_PAD_MOSI_2_SCK_3
/* SPI1 */
#define SPI_1_DEV SERCOM5->SPI
#define SPI_IRQ_1 SERCOM5_IRQn
#define SPI_1_GCLK_ID SERCOM5_GCLK_ID_CORE
/* SPI 1 pin configuration */
#define SPI_1_SCLK GPIO_PIN(PB, 23)
#define SPI_1_SCLK_MUX GPIO_MUX_D
#define SPI_1_MISO GPIO_PIN(PB, 02)
#define SPI_1_MISO_MUX GPIO_MUX_D
#define SPI_1_MISO_PAD SPI_PAD_MISO_0
#define SPI_1_MOSI GPIO_PIN(PB, 22)
#define SPI_1_MOSI_MUX GPIO_MUX_D
#define SPI_1_MOSI_PAD SPI_PAD_MOSI_2_SCK_3
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

36
boards/sodaq-autonomo/include/periph_conf.h
View File

@ -133,7 +133,7 @@ static const uart_conf_t uart_config[] = {
.mux = GPIO_MUX_C,
.rx_pad = UART_PAD_RX_1,
.tx_pad = UART_PAD_TX_2,
},
}
};
/* interrupt function name mapping */
@ -184,27 +184,21 @@ static const pwm_conf_t pwm_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (1)
#define SPI_0_EN 1
#define SPI_1_EN 0
/* SPI0 */
#define SPI_0_DEV SERCOM3->SPI
#define SPI_IRQ_0 SERCOM3_IRQn
#define SPI_0_GCLK_ID SERCOM3_GCLK_ID_CORE
/* SPI 0 pin configuration */
#define SPI_0_SCLK GPIO_PIN(PA, 21)
#define SPI_0_SCLK_MUX GPIO_MUX_D
#define SPI_0_MISO GPIO_PIN(PA, 22)
#define SPI_0_MISO_MUX GPIO_MUX_C
#define SPI_0_MISO_PAD SPI_PAD_MISO_0
#define SPI_0_MOSI GPIO_PIN(PA, 20)
#define SPI_0_MOSI_MUX GPIO_MUX_D
#define SPI_0_MOSI_PAD SPI_PAD_MOSI_2_SCK_3
// How/where do we define SS?
#define SPI_0_SS GPIO_PIN(PA, 23)
static const spi_conf_t spi_config[] = {
{
.dev = &SERCOM3->SPI,
.miso_pin = GPIO_PIN(PA, 22),
.mosi_pin = GPIO_PIN(PA, 20),
.clk_pin = GPIO_PIN(PA, 21),
.miso_mux = GPIO_MUX_C,
.mosi_mux = GPIO_MUX_D,
.clk_mux = GPIO_MUX_D,
.miso_pad = SPI_PAD_MISO_0,
.mosi_pad = SPI_PAD_MOSI_2_SCK_3,
},
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

1
boards/spark-core/Makefile.features
View File

@ -1,6 +1,7 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_uart
# Various other features (if any)

4
boards/spark-core/include/board.h
View File

@ -81,7 +81,7 @@
* @name CC3000 pin configuration
* @{
*/
#define CC3000_SPI SPI_0
#define CC3000_SPI SPI_DEV(0)
#define CC3000_CS GPIO_PIN(PORT_B,12)
#define CC3000_EN GPIO_PIN(PORT_B,8)
#define CC3000_INT GPIO_PIN(PORT_B,11)
@ -91,7 +91,7 @@
* @name EXTFLASH pin configuration
* @{
*/
#define EXTFLASH_SPI SPI_0
#define EXTFLASH_SPI SPI_DEV(0)
#define EXTFLASH GPIO_PIN(PORT_B,9)
/** @} */

45
boards/spark-core/include/periph_conf.h
View File

@ -106,21 +106,42 @@ static const uart_conf_t uart_config[] = {
/** @} */
/**
* @brief SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
/* SPI 0 device configuration */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_BUS_DIV 0 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
/* SPI 0 pin configuration */
#define SPI_0_CLK_PIN GPIO_PIN(PORT_B,15)
#define SPI_0_MOSI_PIN GPIO_PIN(PORT_B,17)
#define SPI_0_MISO_PIN GPIO_PIN(PORT_B,16)
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_B, 17),
.miso_pin = GPIO_PIN(PORT_B, 16),
.sclk_pin = GPIO_PIN(PORT_B, 15),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus

69
boards/stm32f0discovery/include/periph_conf.h
View File

@ -123,38 +123,47 @@ static const uart_conf_t uart_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_IRQ_PRIO 1
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
}
};
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_ISR isr_spi1
/* SPI 1 pin configuration */
#define SPI_0_PORT GPIOA
#define SPI_0_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
#define SPI_0_PIN_SCK 5
#define SPI_0_PIN_MISO 6
#define SPI_0_PIN_MOSI 7
#define SPI_0_PIN_AF 0
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF0,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF0,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
};
/* SPI 1 device config */
#define SPI_1_DEV SPI2
#define SPI_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_1_IRQ SPI2_IRQn
#define SPI_1_ISR isr_spi2
/* SPI 1 pin configuration */
#define SPI_1_PORT GPIOB
#define SPI_1_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
#define SPI_1_PIN_SCK 13
#define SPI_1_PIN_MISO 14
#define SPI_1_PIN_MOSI 15
#define SPI_1_PIN_AF 0
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus

81
boards/stm32f3discovery/include/periph_conf.h
View File

@ -153,50 +153,47 @@ static const pwm_conf_t pwm_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_IRQ_PRIO 1
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT GPIOA
#define SPI_0_SCK_PIN 5
#define SPI_0_SCK_AF 5
#define SPI_0_SCK_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
#define SPI_0_MISO_PORT GPIOA
#define SPI_0_MISO_PIN 6
#define SPI_0_MISO_AF 5
#define SPI_0_MISO_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
#define SPI_0_MOSI_PORT GPIOA
#define SPI_0_MOSI_PIN 7
#define SPI_0_MOSI_AF 5
#define SPI_0_MOSI_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
{
.dev = SPI3,
.mosi_pin = GPIO_PIN(PORT_C, 12),
.miso_pin = GPIO_PIN(PORT_C, 11),
.sclk_pin = GPIO_PIN(PORT_C, 10),
.cs_pin = GPIO_PIN(PORT_A, 15),
.af = GPIO_AF6,
.rccmask = RCC_APB1ENR_SPI3EN,
.apbbus = APB1
}
};
/* SPI 1 device config */
#define SPI_1_DEV SPI3
#define SPI_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_SPI3EN))
#define SPI_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_SPI3EN))
#define SPI_1_IRQ SPI3_IRQn
#define SPI_1_IRQ_HANDLER isr_spi3
/* SPI 1 pin configuration */
#define SPI_1_SCK_PORT GPIOC
#define SPI_1_SCK_PIN 10
#define SPI_1_SCK_AF 6
#define SPI_1_SCK_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOCEN))
#define SPI_1_MISO_PORT GPIOC
#define SPI_1_MISO_PIN 11
#define SPI_1_MISO_AF 6
#define SPI_1_MISO_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOCEN))
#define SPI_1_MOSI_PORT GPIOC
#define SPI_1_MOSI_PIN 12
#define SPI_1_MOSI_AF 6
#define SPI_1_MOSI_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOCEN))
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

88
boards/stm32f4discovery/include/periph_conf.h
View File

@ -182,55 +182,53 @@ static const pwm_conf_t pwm_config[] = {
/** @} */
/**
* @name SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_IRQ_PRIO 1
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 42000000Hz */
7, /* -> 164062Hz */
6, /* -> 328125Hz */
4, /* -> 1312500Hz */
2, /* -> 5250000Hz */
1 /* -> 10500000Hz */
},
{ /* for APB2 @ 84000000Hz */
7, /* -> 328125Hz */
7, /* -> 328125Hz */
5, /* -> 1312500Hz */
3, /* -> 5250000Hz */
2 /* -> 10500000Hz */
}
};
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT GPIOA
#define SPI_0_SCK_PIN 5
#define SPI_0_SCK_AF 5
#define SPI_0_SCK_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
#define SPI_0_MISO_PORT GPIOA
#define SPI_0_MISO_PIN 6
#define SPI_0_MISO_AF 5
#define SPI_0_MISO_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
#define SPI_0_MOSI_PORT GPIOA
#define SPI_0_MOSI_PIN 7
#define SPI_0_MOSI_AF 5
#define SPI_0_MOSI_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_PIN(PORT_A, 4),
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_PIN(PORT_B, 12),
.af = GPIO_AF5,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
};
/* SPI 1 device config */
#define SPI_1_DEV SPI2
#define SPI_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_1_BUS_DIV 0 /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */
#define SPI_1_IRQ SPI2_IRQn
#define SPI_1_IRQ_HANDLER isr_spi2
/* SPI 1 pin configuration */
#define SPI_1_SCK_PORT GPIOB
#define SPI_1_SCK_PIN 13
#define SPI_1_SCK_AF 5
#define SPI_1_SCK_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
#define SPI_1_MISO_PORT GPIOB
#define SPI_1_MISO_PIN 14
#define SPI_1_MISO_AF 5
#define SPI_1_MISO_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
#define SPI_1_MOSI_PORT GPIOB
#define SPI_1_MOSI_PIN 15
#define SPI_1_MOSI_AF 5
#define SPI_1_MOSI_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

4
boards/telosb/include/board.h
View File

@ -102,8 +102,8 @@ extern "C" {
/**
* @brief Definition of the interface to the CC2420 radio
*/
#define CC2420_PARAMS_BOARD {.spi = SPI_0, \
.spi_clk = SPI_SPEED_1MHZ , \
#define CC2420_PARAMS_BOARD {.spi = SPI_DEV(0), \
.spi_clk = SPI_CLK_1MHZ , \
.pin_cs = GPIO_PIN(P4, 2), \
.pin_fifo = GPIO_PIN(P1, 3), \
.pin_fifop = GPIO_PIN(P1, 0), \

2
boards/telosb/include/periph_conf.h
View File

@ -75,7 +75,7 @@ extern "C" {
#define SPI_0_EN (1U)
/* SPI configuration */
#define SPI_DEV (USART_0)
#define SPI_BASE (USART_0)
#define SPI_IE (SFR->IE1)
#define SPI_IF (SFR->IFG1)
#define SPI_IE_RX_BIT (1 << 6)

33
boards/udoo/include/periph_conf.h
View File

@ -86,29 +86,18 @@ static const uart_conf_t uart_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
.id = ID_SPI0,
.clk = GPIO_PIN(PA, 25),
.mosi = GPIO_PIN(PA, 26),
.miso = GPIO_PIN(PA, 27),
.mux = GPIO_MUX_A
}
};
/* SPI 0 device config */
#define SPI_0_DEV SPI0
#define SPI_0_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_SPI0));
#define SPI_0_CLKDIS() (PMC->PMC_PCER0 &= ~(1 << ID_SPI0));
#define SPI_0_IRQ SPI0_IRQn
#define SPI_0_IRQ_HANDLER isr_spi0
#define SPI_0_IRQ_PRIO 1
/* SPI 0 pin configuration */
#define SPI_0_MISO_PIN PIO_PA25A_SPI0_MISO
#define SPI_0_MOSI_PIN PIO_PA26A_SPI0_MOSI
#define SPI_0_SCK_PIN PIO_PA27A_SPI0_SPCK
#define SPI_0_MISO_PORT PIOA
#define SPI_0_MOSI_PORT PIOA
#define SPI_0_SCK_PORT PIOA
#define SPI_0_MISO_PORT_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_PIOA));
#define SPI_0_MOSI_PORT_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_PIOA));
#define SPI_0_SCK_PORT_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_PIOA));
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus

17
boards/weio/include/periph_conf.h
View File

@ -81,9 +81,20 @@ extern "C" {
* @brief SPI configuration
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
static const spi_conf_t spi_config[] = {
{
.dev = LPC_SSP0,
.preset_bit = (1 << 0),
.ahb_bit = (1 << 11)
},
{
.dev = LPC_SSP1,
.preset_bit = (1 << 2),
.ahb_bit = (1 << 18)
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/* @} */
/**

2
boards/wsn430-common/include/periph_conf.h
View File

@ -75,7 +75,7 @@ extern "C" {
#define SPI_0_EN (1U)
/* SPI configuration */
#define SPI_DEV (USART_0)
#define SPI_BASE (USART_0)
#define SPI_IE (SFR->IE1)
#define SPI_IF (SFR->IFG1)
#define SPI_IE_RX_BIT (1 << 6)

1
boards/wsn430-v1_3b/Makefile.features
View File

@ -1,6 +1,7 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_uart
# Various other features (if any)

1
boards/wsn430-v1_4/Makefile.features
View File

@ -1,6 +1,7 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_uart
# Various other features (if any)

30
boards/yunjia-nrf51822/include/periph_conf.h
View File

@ -81,22 +81,22 @@ static const timer_conf_t timer_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_IRQ_PRIO 1
static const spi_conf_t spi_config[] = {
{
.dev = NRF_SPI0,
.sclk = 19,
.mosi = 17,
.miso = 18
},
{
.dev = NRF_SPI1,
.sclk = 22,
.mosi = 20,
.miso = 21
}
};
/* SPI_0 device configuration */
#define SPI_0_DEV NRF_SPI0
#define SPI_0_PIN_MOSI 17
#define SPI_0_PIN_MISO 18
#define SPI_0_PIN_SCK 19
/* SPI_1 device configuration */
#define SPI_1_DEV NRF_SPI1
#define SPI_1_PIN_MOSI 20
#define SPI_1_PIN_MISO 21
#define SPI_1_PIN_SCK 22
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

4
boards/z1/include/board.h
View File

@ -110,8 +110,8 @@ extern "C" {
/**
* @brief Definition of the interface to the CC2420 radio
*/
#define CC2420_PARAMS_BOARD {.spi = SPI_0, \
.spi_clk = SPI_SPEED_5MHZ, \
#define CC2420_PARAMS_BOARD {.spi = SPI_DEV(0), \
.spi_clk = SPI_CLK_5MHZ, \
.pin_cs = GPIO_PIN(P3, 0), \
.pin_fifo = GPIO_PIN(P1, 3), \
.pin_fifop = GPIO_PIN(P1, 2), \

2
boards/z1/include/periph_conf.h
View File

@ -76,7 +76,7 @@ extern "C" {
/* SPI configuration */
#define SPI_USE_USCI
#define SPI_DEV (USCI_0_B_SPI)
#define SPI_BASE (USCI_0_B_SPI)
#define SPI_IE (SFR->IE2)
#define SPI_IF (SFR->IFG2)
#define SPI_IE_RX_BIT (1 << 2)

5
cpu/atmega1281/cpu.c
View File

@ -18,12 +18,13 @@
*/
#include "cpu.h"
#include "periph/init.h"
/**
* @brief Initialize the CPU, set IRQ priorities
*/
void cpu_init(void)
{
/* Right now we need to do nothing here */
;
/* trigger static peripheral initialization */
periph_init();
}

5
cpu/atmega2560/cpu.c
View File

@ -18,12 +18,13 @@
*/
#include "cpu.h"
#include "periph/init.h"
/**
* @brief Initialize the CPU, set IRQ priorities
*/
void cpu_init(void)
{
/* Right now we need to do nothing here */
;
/* trigger static peripheral initialization */
periph_init();
}

5
cpu/atmega328p/cpu.c
View File

@ -18,12 +18,13 @@
*/
#include "cpu.h"
#include "periph/init.h"
/**
* @brief Initialize the CPU, set IRQ priorities
*/
void cpu_init(void)
{
/* Right now we need to do nothing here */
;
/* trigger static peripheral initialization */
periph_init();
}

38
cpu/atmega_common/include/periph_cpu_common.h
View File

@ -32,6 +32,16 @@ extern "C" {
*/
#define GPIO_PIN(x, y) ((x << 4) | y)
/**
* @brief Use some common SPI functions
* @{
*/
#define PERIPH_SPI_NEEDS_INIT_CS
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
/** @} */
/**
* @brief SPI mode select macro
*
@ -47,13 +57,13 @@ extern "C" {
* correct configuration there
* @{
*/
#define HAVE_SPI_CONF_T
#define HAVE_SPI_MODE_T
typedef enum {
SPI_CONF_FIRST_RISING = SPI_MODE_SEL(0, 0), /**< mode 0 */
SPI_CONF_SECOND_RISING = SPI_MODE_SEL(0, 1), /**< mode 1 */
SPI_CONF_FIRST_FALLING = SPI_MODE_SEL(1, 0), /**< mode 2 */
SPI_CONF_SECOND_FALLING = SPI_MODE_SEL(1, 1) /**< mode 3 */
} spi_conf_t;
SPI_MODE_0 = SPI_MODE_SEL(0, 0), /**< mode 0 */
SPI_MODE_1 = SPI_MODE_SEL(0, 1), /**< mode 1 */
SPI_MODE_2 = SPI_MODE_SEL(1, 0), /**< mode 2 */
SPI_MODE_3 = SPI_MODE_SEL(1, 1) /**< mode 3 */
} spi_mode_t;
/** @} */
/**
@ -62,7 +72,7 @@ typedef enum {
* We encode the speed in bits 2, 1, and 0, where bit0 and bit1 hold the SPCR
* prescaler bits, while bit2 holds the SPI2X bit.
*/
#define SPI_SPEED_SEL(s2x, pr1, pr0) ((s2x << 2) | (pr1 << 1) | pr0)
#define SPI_CLK_SEL(s2x, pr1, pr0) ((s2x << 2) | (pr1 << 1) | pr0)
/**
* @brief Override SPI speed values
@ -70,14 +80,14 @@ typedef enum {
* We assume a master clock speed of 16MHz here.
* @{
*/
#define HAVE_SPI_SPEED_T
#define HAVE_SPI_CLK_T
typedef enum {
SPI_SPEED_100KHZ = SPI_SPEED_SEL(0, 1, 1), /**< 16/128 -> 125KHz */
SPI_SPEED_400KHZ = SPI_SPEED_SEL(1, 1, 0), /**< 16/32 -> 500KHz */
SPI_SPEED_1MHZ = SPI_SPEED_SEL(0, 0, 1), /**< 16/16 -> 1MHz */
SPI_SPEED_5MHZ = SPI_SPEED_SEL(0, 0, 0), /**< 16/4 -> 4MHz */
SPI_SPEED_10MHZ = SPI_SPEED_SEL(1, 0, 0) /**< 16/2 -> 8MHz */
} spi_speed_t;
SPI_CLK_100KHZ = SPI_CLK_SEL(0, 1, 1), /**< 16/128 -> 125KHz */
SPI_CLK_400KHZ = SPI_CLK_SEL(1, 1, 0), /**< 16/32 -> 500KHz */
SPI_CLK_1MHZ = SPI_CLK_SEL(0, 0, 1), /**< 16/16 -> 1MHz */
SPI_CLK_5MHZ = SPI_CLK_SEL(0, 0, 0), /**< 16/4 -> 4MHz */
SPI_CLK_10MHZ = SPI_CLK_SEL(1, 0, 0) /**< 16/2 -> 8MHz */
} spi_clk_t;
/** @} */
#ifdef __cplusplus

121
cpu/atmega_common/periph/spi.c
View File

@ -22,31 +22,30 @@
#include "cpu.h"
#include "mutex.h"
#include "assert.h"
#include "periph/spi.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
/* guard this file in case no SPI device is defined */
#if SPI_NUMOF
/**
* @brief Extract BR0, BR1 and SPI2X bits from speed value
* @{
*/
#define SPEED_MASK (0x3)
#define CLK_MASK (0x3)
#define S2X_SHIFT (2)
/** @} */
static mutex_t lock = MUTEX_INIT;
int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
void spi_init(spi_t bus)
{
assert(bus == 0);
/* power off the SPI peripheral */
MEGA_PRR |= (1 << PRSPI);
/* trigger the pin configuration */
spi_init_pins(bus);;
}
void spi_init_pins(spi_t bus)
{
DEBUG("spi.c: conf = %d, speed = %d\n", conf, speed);
/* make sure device is valid (there is only one...) */
if (dev != 0) {
return -1;
}
/* the pin configuration for this CPU is fixed:
* - PB3: MISO (configure as input - done automatically)
@ -59,93 +58,59 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
* select externally for now)
*/
DDRB |= ((1 << DDB2) | (1 << DDB1) | (1 << DDB0));
}
/* make sure the SPI is not powered off */
int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
{
(void)cs;
/* lock the bus and power on the SPI peripheral */
mutex_lock(&lock);
MEGA_PRR &= ~(1 << PRSPI);
/* configure as master, with given mode and clock */
SPSR = (speed >> S2X_SHIFT);
SPCR = ((1 << SPE) | (1 << MSTR) | conf | (speed & SPEED_MASK));
SPSR = (clk >> S2X_SHIFT);
SPCR = ((1 << SPE) | (1 << MSTR) | mode | (clk & CLK_MASK));
SPCR |= (1 << SPE);
/* clear interrupt flag by reading SPSR */
/* clear interrupt flag by reading SPSR and data register by reading SPDR */
(void)SPSR;
/* clear data register */
(void)SPDR;
return 0;
return SPI_OK;
}
int spi_acquire(spi_t dev)
{
mutex_lock(&lock);
return 0;
}
int spi_release(spi_t dev)
void spi_release(spi_t bus)
{
/* power off and release the bus */
SPCR &= ~(1 << SPE);
MEGA_PRR |= (1 << PRSPI);
mutex_unlock(&lock);
return 0;
}
int spi_init_slave(spi_t dev, spi_conf_t conf, char (*cb)(char data))
void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
const void *out, void *in, size_t len)
{
(void) dev;
(void) conf;
(void) cb;
uint8_t *out_buf = (uint8_t *)out;
uint8_t *in_buf = (uint8_t *)in;
/* not implemented */
return -1;
}
assert(out_buf || in_buf);
void spi_transmission_begin(spi_t dev, char reset_val)
{
(void)dev;
(void)reset_val;
if (cs != SPI_CS_UNDEF) {
gpio_clear((gpio_t)cs);
}
/* not implemented */
}
int spi_transfer_byte(spi_t dev, char out, char *in)
{
return spi_transfer_bytes(dev, &out, in, 1);
}
int spi_transfer_bytes(spi_t dev, char *out, char *in, unsigned int length)
{
for (unsigned int i = 0; i < length; i++) {
char tmp = (out) ? out[i] : 0;
for (size_t i = 0; i < len; i++) {
uint8_t tmp = (out_buf) ? out_buf[i] : 0;
SPDR = tmp;
while (!(SPSR & (1 << SPIF))) {}
tmp = SPDR;
if (in) {
in[i] = tmp;
if (in_buf) {
in_buf[i] = tmp;
}
}
return (int)length;
if ((!cont) && (cs != SPI_CS_UNDEF)) {
gpio_set((gpio_t)cs);
}
}
int spi_transfer_reg(spi_t dev, uint8_t reg, char out, char *in)
{
spi_transfer_bytes(dev, (char *)&reg, NULL, 1);
return spi_transfer_bytes(dev, &out, in, 1);
}
int spi_transfer_regs(spi_t dev, uint8_t reg, char *out, char *in, unsigned int length)
{
spi_transfer_bytes(dev, (char *)&reg, NULL, 1);
return spi_transfer_bytes(dev, out, in, length);
}
void spi_poweron(spi_t dev)
{
SPCR |= (1 << SPE);
}
void spi_poweroff(spi_t dev)
{
SPCR &= ~(1 << SPE);
}
#endif /* SPI_NUMOF */

3
cpu/cc2538/cpu.c
View File

@ -20,6 +20,7 @@
#include <assert.h>
#include "cpu.h"
#include "periph/init.h"
#define BIT(n) ( 1UL << (n) )
@ -47,6 +48,8 @@ void cpu_init(void)
SYS_CTRL->I_MAP = 1;
/* initialize the clock system */
cpu_clock_init();
/* trigger static peripheral initialization */
periph_init();
}
/**

40
cpu/cc2538/include/cc2538_ssi.h
View File

@ -77,6 +77,46 @@ typedef struct {
#define SSI0 ( (cc2538_ssi_t*)0x40008000 ) /**< SSI0 Instance */
#define SSI1 ( (cc2538_ssi_t*)0x40009000 ) /**< SSI1 Instance */
/**
* @brief Define CR0 register bitfields
* @{
*/
#define SSI_CR0_DSS(x) ((x - 1) << 0)
#define SSI_CR0_SPO (1 << 6)
#define SSI_CR0_SPH (1 << 7)
/** @} */
/**
* @brief Define CR1 register bitfields
* @{
*/
#define SSI_CR1_LBM (1 << 0)
#define SSI_CR1_SSE (1 << 1)
#define SSI_CR1_MS (1 << 2)
#define SSI_CR1_SOD (1 << 3)
/** @} */
/**
* @brief Define SR register bitfields
* @{
*/
#define SSI_SR_TFE (1 << 0)
#define SSI_SR_TNF (1 << 1)
#define SSI_SR_RNE (1 << 2)
#define SSI_SR_RFF (1 << 3)
#define SSI_SR_BSY (1 << 4)
/** @} */
/**
* @brief Define CC register bitfields
* @{
*/
#define SSI_SS_PIOSC (1 << 0)
#define SSI_SS_DSEN (1 << 2)
#define SSI_SS_SYSDIV (0)
#define SSI_SS_IODIV (SSI_SS_PIOSC)
/** @} */
#ifdef __cplusplus
} /* end extern "C" */
#endif

1
cpu/cc2538/include/cpu_conf.h
View File

@ -26,6 +26,7 @@
#include "cc2538_gptimer.h"
#include "cc2538_ioc.h"
#include "cc2538_soc_adc.h"
#include "cc2538_ssi.h"
#include "cc2538_rfcore.h"
#include "cc2538_sys_ctrl.h"

56
cpu/cc2538/include/periph_cpu.h
View File

@ -21,9 +21,7 @@
#include <stdint.h>
#include "cc2538_gptimer.h"
#include "cc2538_ssi.h"
#include "cc2538_gpio.h"
#include "cpu.h"
#ifdef __cplusplus
extern "C" {
@ -50,10 +48,25 @@ typedef uint32_t gpio_t;
*/
#define GPIO_PIN(port, pin) (gpio_t)(((uint32_t)GPIO_A + (port << 12)) | pin)
/**
* @brief Define a custom GPIO_UNDEF value
*/
#define GPIO_UNDEF 99
/**
* @brief I2C configuration options
*/
typedef struct {
gpio_t scl_pin; /**< pin used for SCL */
gpio_t sda_pin; /**< pin used for SDA */
} i2c_conf_t;
/**
* @brief declare needed generic SPI functions
* @{
*/
#define PERIPH_SPI_NEEDS_INIT_CS
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
/** @} */
@ -74,12 +87,39 @@ typedef enum {
/** @} */
/**
* @brief I2C configuration options
* @brief Override SPI mode settings
* @{
*/
#define HAVE_SPI_MODE_T
typedef enum {
SPI_MODE_0 = 0, /**< CPOL=0, CPHA=0 */
SPI_MODE_1 = (SSI_CR0_SPH), /**< CPOL=0, CPHA=1 */
SPI_MODE_2 = (SSI_CR0_SPO), /**< CPOL=1, CPHA=0 */
SPI_MODE_3 = (SSI_CR0_SPO | SSI_CR0_SPH) /**< CPOL=1, CPHA=1 */
} spi_mode_t;
/** @ */
/**
* @brief Override SPI clock settings
* @{
*/
#define HAVE_SPI_CLK_T
typedef enum {
SPI_CLK_100KHZ = 0, /**< drive the SPI bus with 100KHz */
SPI_CLK_400KHZ = 1, /**< drive the SPI bus with 400KHz */
SPI_CLK_1MHZ = 2, /**< drive the SPI bus with 1MHz */
SPI_CLK_5MHZ = 3, /**< drive the SPI bus with 5MHz */
SPI_CLK_10MHZ = 4 /**< drive the SPI bus with 10MHz */
} spi_clk_t;
/** @} */
/**
* @brief Datafields for static SPI clock configuration values
*/
typedef struct {
gpio_t scl_pin; /**< pin used for SCL */
gpio_t sda_pin; /**< pin used for SDA */
} i2c_conf_t;
uint8_t cpsr; /**< CPSR clock divider */
uint8_t scr; /**< SCR clock divider */
} spi_clk_conf_t;
/**
* @brief SPI configuration data structure
@ -91,7 +131,7 @@ typedef struct {
gpio_t miso_pin; /**< pin used for MISO */
gpio_t sck_pin; /**< pin used for SCK */
gpio_t cs_pin; /**< pin used for CS */
} periph_spi_conf_t;
} spi_conf_t;
/** @} */
/**

382
cpu/cc2538/periph/spi.c
View File

@ -1,327 +1,175 @@
/*
* Copyright (C) 2015 Loci Controls Inc.
* 2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup driver_periph
* @addtogroup cpu_cc2538
* @{
*
* @file
* @brief Low-level SPI driver implementation
*
* @author Ian Martin <ian@locicontrols.com>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include <assert.h>
#include <stdio.h>
#include "cc2538_ssi.h"
#include "cpu.h"
#include "mutex.h"
#include "assert.h"
#include "periph/spi.h"
#include "periph_conf.h"
/* guard file in case no SPI device is defined */
#if SPI_NUMOF
/* clock sources for the SSI_CC register */
#define CS_SYS_DIV 0
#define CS_IO_DIV 1
#define SSI0_MASK (1 << 0)
#define SSI1_MASK (1 << 1)
#ifndef SPI_DATA_BITS_NUMOF
#define SPI_DATA_BITS_NUMOF 8
#endif
#define spin_until(condition) while (!(condition)) thread_yield()
/**
* @brief Array holding one pre-initialized mutex for each SPI device
* @brief Array holding one pre-initialized mutex for each SPI device
*/
static mutex_t locks[SPI_NUMOF] = {MUTEX_INIT};
static mutex_t locks[SPI_NUMOF];
int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
static inline cc2538_ssi_t *dev(spi_t bus)
{
cc2538_ssi_t* ssi = spi_config[dev].dev;
if ((unsigned int)dev >= SPI_NUMOF) {
return -1;
}
/* power on the SPI device */
spi_poweron(dev);
/* configure SCK, MISO and MOSI pin */
spi_conf_pins(dev);
/* Disable the SSI and configure it for SPI master mode */
ssi->CR1 = 0;
/* 3. Configure the SSI clock source */
ssi->CC = CS_SYS_DIV;
/* 4. Configure the clock prescale divisor by writing the SSI_CPSR register.
* frequency of the SSIClk is defined by: SSIClk = SysClk / (CPSDVSR x (1 + SCR))
*/
const int32_t speed_lut[] = {
[SPI_SPEED_100KHZ] = 100000 /* Hz */,
[SPI_SPEED_400KHZ] = 400000 /* Hz */,
[SPI_SPEED_1MHZ ] = 1000000 /* Hz */,
[SPI_SPEED_5MHZ ] = 5000000 /* Hz */,
[SPI_SPEED_10MHZ ] = 10000000 /* Hz */,
};
int32_t SysClk = sys_clock_freq();
int32_t f_desired = speed_lut[speed];
int32_t f_actual;
int32_t err;
int32_t best_err = INT32_MAX;
int32_t div1;
int32_t div2;
int32_t best_div1 = 2;
int32_t best_div2 = 1;
/* System clock is first divided by CPSDVSR, then by SCR */
for (div1 = 2; div1 <= 254; div1++) {
div2 = SysClk;
int32_t denom = div1 * f_desired;
div2 += denom / 2;
div2 /= denom;
if (div2 < 1) {
div2 = 1;
}
else if (div2 > 256) {
div2 = 256;
}
f_actual = SysClk / (div1 * div2);
err = f_actual - f_desired;
if (err < 0) {
err = -err;
}
if (err <= best_err) {
best_div1 = div1;
best_div2 = div2;
best_err = err;
}
}
ssi->CPSR = best_div1; /* CPSDVSR */
ssi->CR0bits.SCR = best_div2 - 1; /* Serial clock rate (SCR) */
switch (conf) {
case SPI_CONF_FIRST_RISING:
ssi->CR0bits.SPO = 0;
ssi->CR0bits.SPH = 0;
break;
case SPI_CONF_SECOND_RISING:
ssi->CR0bits.SPO = 0;
ssi->CR0bits.SPH = 1;
break;
case SPI_CONF_FIRST_FALLING:
ssi->CR0bits.SPO = 1;
ssi->CR0bits.SPH = 0;
break;
case SPI_CONF_SECOND_FALLING:
ssi->CR0bits.SPO = 1;
ssi->CR0bits.SPH = 1;
break;
}
ssi->CR0bits.FRF = 0; /* SPI protocol mode */
ssi->CR0bits.DSS = SPI_DATA_BITS_NUMOF - 1; /* The data size */
ssi->CR1bits.SSE = 1;
return 0;
return spi_config[bus].dev;
}
int spi_init_slave(spi_t dev, spi_conf_t conf, char(*cb)(char data))
static inline void poweron(spi_t bus)
{
/* slave mode is not (yet) supported */
return -1;
SYS_CTRL_RCGCSSI |= (1 << bus);
SYS_CTRL_SCGCSSI |= (1 << bus);
SYS_CTRL_DCGCSSI |= (1 << bus);
}
int spi_conf_pins(spi_t dev)
static inline void poweroff(spi_t bus)
{
if ((unsigned int)dev >= SPI_NUMOF) {
return -1;
}
SYS_CTRL_RCGCSSI &= ~(1 << bus);
SYS_CTRL_SCGCSSI &= ~(1 << bus);
SYS_CTRL_DCGCSSI &= ~(1 << bus);
}
switch ((uintptr_t)spi_config[dev].dev) {
void spi_init(spi_t bus)
{
assert(bus <= SPI_NUMOF);
/* temporarily power on the device */
poweron(bus);
/* configure device to be a master and disable SSI operation mode */
dev(bus)->CR1 = 0;
/* configure system clock as SSI clock source */
dev(bus)->CC = SSI_SS_IODIV;
/* and power off the bus again */
poweroff(bus);
/* trigger SPI pin configuration */
spi_init_pins(bus);
}
void spi_init_pins(spi_t bus)
{
switch ((uintptr_t)spi_config[bus].dev) {
case (uintptr_t)SSI0:
IOC_PXX_SEL[spi_config[dev].mosi_pin] = SSI0_TXD;
IOC_PXX_SEL[spi_config[dev].sck_pin ] = SSI0_CLKOUT;
IOC_PXX_SEL[spi_config[dev].cs_pin ] = SSI0_FSSOUT;
IOC_PXX_SEL[spi_config[bus].mosi_pin] = SSI0_TXD;
IOC_PXX_SEL[spi_config[bus].sck_pin ] = SSI0_CLKOUT;
IOC_PXX_SEL[spi_config[bus].cs_pin ] = SSI0_FSSOUT;
IOC_SSIRXD_SSI0 = spi_config[dev].miso_pin;
IOC_SSIRXD_SSI0 = spi_config[bus].miso_pin;
break;
case (uintptr_t)SSI1:
IOC_PXX_SEL[spi_config[dev].mosi_pin] = SSI1_TXD;
IOC_PXX_SEL[spi_config[dev].sck_pin ] = SSI1_CLKOUT;
IOC_PXX_SEL[spi_config[dev].cs_pin ] = SSI1_FSSOUT;
IOC_PXX_SEL[spi_config[bus].mosi_pin] = SSI1_TXD;
IOC_PXX_SEL[spi_config[bus].sck_pin ] = SSI1_CLKOUT;
IOC_PXX_SEL[spi_config[bus].cs_pin ] = SSI1_FSSOUT;
IOC_SSIRXD_SSI1 = spi_config[dev].miso_pin;
IOC_SSIRXD_SSI1 = spi_config[bus].miso_pin;
break;
}
IOC_PXX_OVER[spi_config[dev].mosi_pin] = IOC_OVERRIDE_OE;
IOC_PXX_OVER[spi_config[dev].sck_pin ] = IOC_OVERRIDE_OE;
IOC_PXX_OVER[spi_config[dev].cs_pin ] = IOC_OVERRIDE_OE;
IOC_PXX_OVER[spi_config[dev].miso_pin] = IOC_OVERRIDE_DIS;
IOC_PXX_OVER[spi_config[bus].mosi_pin] = IOC_OVERRIDE_OE;
IOC_PXX_OVER[spi_config[bus].miso_pin] = IOC_OVERRIDE_DIS;
IOC_PXX_OVER[spi_config[bus].sck_pin ] = IOC_OVERRIDE_OE;
IOC_PXX_OVER[spi_config[bus].cs_pin ] = IOC_OVERRIDE_OE;
gpio_hardware_control(spi_config[dev].mosi_pin);
gpio_hardware_control(spi_config[dev].miso_pin);
gpio_hardware_control(spi_config[dev].sck_pin);
gpio_hardware_control(spi_config[dev].cs_pin);
return 0;
gpio_hardware_control(spi_config[bus].mosi_pin);
gpio_hardware_control(spi_config[bus].miso_pin);
gpio_hardware_control(spi_config[bus].sck_pin);
gpio_hardware_control(spi_config[bus].cs_pin);
}
int spi_acquire(spi_t dev)
int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
{
if ((unsigned int)dev >= SPI_NUMOF) {
return -1;
}
mutex_lock(&locks[dev]);
return 0;
/* lock the bus */
mutex_lock(&locks[bus]);
/* power on device */
poweron(bus);
/* configure SCR clock field, data-width and mode */
dev(bus)->CR0 = 0;
dev(bus)->CPSR = (spi_clk_config[clk].cpsr);
dev(bus)->CR0 = ((spi_clk_config[clk].scr << 8) | mode | SSI_CR0_DSS(8));
/* enable SSI device */
dev(bus)->CR1 = SSI_CR1_SSE;
return SPI_OK;
}
int spi_release(spi_t dev)
void spi_release(spi_t bus)
{
if ((unsigned int)dev >= SPI_NUMOF) {
return -1;
}
mutex_unlock(&locks[dev]);
return 0;
/* disable and power off device */
dev(bus)->CR1 = 0;
poweroff(bus);
/* and release lock... */
mutex_unlock(&locks[bus]);
}
static char ssi_flush_input(cc2538_ssi_t *ssi)
void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
const void *out, void *in, size_t len)
{
char tmp = 0;
uint8_t *out_buf = (uint8_t *)out;
uint8_t *in_buf = (uint8_t *)in;
while (ssi->SRbits.RNE) {
tmp = ssi->DR;
assert(out_buf || in_buf);
if (cs != SPI_CS_UNDEF) {
gpio_clear((gpio_t)cs);
}
return tmp;
}
int spi_transfer_byte(spi_t dev, char out, char *in)
{
cc2538_ssi_t* ssi = spi_config[dev].dev;
char tmp;
ssi_flush_input(ssi);
/* transmit byte */
spin_until(ssi->SRbits.TNF);
ssi->DR = out;
/* receive byte */
spin_until(ssi->SRbits.RNE);
tmp = ssi->DR;
if (in) {
*in = tmp;
}
return 1;
}
int spi_transfer_bytes(spi_t dev, char *out, char *in, unsigned int length)
{
cc2538_ssi_t* ssi = spi_config[dev].dev;
unsigned int tx_n = 0, rx_n = 0;
if ((unsigned int)dev >= SPI_NUMOF) {
return -1;
}
ssi_flush_input(ssi);
/* transmit and receive bytes */
while (tx_n < length) {
spin_until(ssi->SRbits.TNF || ssi->SRbits.RNE);
if (ssi->SRbits.TNF) {
ssi->DR = out[tx_n];
tx_n++;
if (!in_buf) {
for (size_t i = 0; i < len; i++) {
while (!(dev(bus)->SR & SSI_SR_TNF)) {}
dev(bus)->DR = out_buf[i];
}
else if (ssi->SRbits.RNE) {
assert(rx_n < length);
in[rx_n] = ssi->DR;
rx_n++;
/* flush RX FIFO while busy*/
while ((dev(bus)->SR & SSI_SR_BSY)) {
dev(bus)->DR;
}
}
/* receive remaining bytes */
while (rx_n < length) {
spin_until(ssi->SRbits.RNE);
assert(rx_n < length);
in[rx_n] = ssi->DR;
rx_n++;
else if (!out_buf) { /*TODO this case is currently untested */
size_t in_cnt = 0;
for (size_t i = 0; i < len; i++) {
while (!(dev(bus)->SR & SSI_SR_TNF)) {}
dev(bus)->DR = 0;
if (dev(bus)->SR & SSI_SR_RNE) {
in_buf[in_cnt++] = dev(bus)->DR;
}
}
/* get remaining bytes */
while (dev(bus)->SR & SSI_SR_RNE) {
in_buf[in_cnt++] = dev(bus)->DR;
}
}
else {
for (size_t i = 0; i < len; i++) {
while (!(dev(bus)->SR & SSI_SR_TNF)) {}
dev(bus)->DR = out_buf[i];
while (!(dev(bus)->SR & SSI_SR_RNE)){}
in_buf[i] = dev(bus)->DR;
}
/* wait until no more busy */
while ((dev(bus)->SR & SSI_SR_BSY)) {}
}
return rx_n;
}
void spi_transmission_begin(spi_t dev, char reset_val)
{
/* slave mode is not (yet) supported */
}
void spi_poweron(spi_t dev)
{
switch ((uintptr_t)spi_config[dev].dev) {
case (uintptr_t)SSI0:
/* enable SSI0 in all three power modes */
SYS_CTRL_RCGCSSI |= SSI0_MASK;
SYS_CTRL_SCGCSSI |= SSI0_MASK;
SYS_CTRL_DCGCSSI |= SSI0_MASK;
break;
case (uintptr_t)SSI1:
/* enable SSI1 in all three power modes */
SYS_CTRL_RCGCSSI |= SSI1_MASK;
SYS_CTRL_SCGCSSI |= SSI1_MASK;
SYS_CTRL_DCGCSSI |= SSI1_MASK;
break;
if ((!cont) && (cs != SPI_CS_UNDEF)) {
gpio_set((gpio_t)cs);
}
}
void spi_poweroff(spi_t dev)
{
switch ((uintptr_t)spi_config[dev].dev) {
case (uintptr_t)SSI0:
/* disable SSI0 in all three power modes */
SYS_CTRL_RCGCSSI &= ~SSI0_MASK;
SYS_CTRL_SCGCSSI &= ~SSI0_MASK;
SYS_CTRL_DCGCSSI &= ~SSI0_MASK;
break;
case (uintptr_t)SSI1:
/* disable SSI1 in all three power modes */
SYS_CTRL_RCGCSSI &= ~SSI1_MASK;
SYS_CTRL_SCGCSSI &= ~SSI1_MASK;
SYS_CTRL_DCGCSSI &= ~SSI1_MASK;
break;
}
}
#endif /* SPI_NUMOF */

8
cpu/cc26x0/cpu.c
View File

@ -17,8 +17,9 @@
* @}
*/
#include "cpu.h"
#include "periph_conf.h"
#include "cpu.h"
#include "periph_conf.h"
#include "periph/init.h"
#ifndef HF_CLOCK_SOURCE
#define HF_CLOCK_SOURCE DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC /* set 48MHz RCOSC */
@ -42,6 +43,9 @@ void cpu_init(void)
/* initialize the system clock */
cpu_clock_init();
/* trigger static peripheral initialization */
periph_init();
}
static void cpu_clock_init(void)

3
cpu/ezr32wg/cpu.c
View File

@ -19,6 +19,7 @@
#include "cpu.h"
#include "periph_conf.h"
#include "periph/init.h"
/**
* @brief Configure clock sources and the CPU frequency
@ -59,4 +60,6 @@ void cpu_init(void)
cortexm_init();
/* Initialise clock sources and generic clocks */
clk_init();
/* trigger static peripheral initialization */
periph_init();
}

3
cpu/k60/cpu.c
View File

@ -9,6 +9,7 @@
#include <stdint.h>
#include "cpu.h"
#include "board.h"
#include "periph/init.h"
/**
* @ingroup cpu_k60
@ -48,6 +49,8 @@ void cpu_init(void)
cortexm_init();
/* Check that we are running on the CPU that this code was built for */
check_running_cpu_revision();
/* trigger static peripheral initialization */
periph_init();
}
static void check_running_cpu_revision(void)

3
cpu/k64f/cpu.c
View File

@ -23,6 +23,7 @@
#include "cpu.h"
#include "mcg.h"
#include "cpu_conf.h"
#include "periph/init.h"
#define SIM_CLKDIV1_60MHZ (SIM_CLKDIV1_OUTDIV1(0) | \
SIM_CLKDIV1_OUTDIV2(0) | \
@ -40,6 +41,8 @@ void cpu_init(void)
cortexm_init();
/* initialize the clock system */
cpu_clock_init();
/* trigger static peripheral initialization */
periph_init();
}
/**

1
cpu/kinetis_common/Makefile.include
View File

@ -9,6 +9,7 @@ export UNDEF += $(BINDIR)/kinetis_common/fcfield.o
# include kinetis common periph drivers
export USEMODULE += kinetis_common_periph
export USEMODULE += periph_common
#include layered power mode module
USEMODULE += pm_layered

12
cpu/kinetis_common/dist/calc_spi_scalers/Makefile vendored Normal file
View File

@ -0,0 +1,12 @@
NAME = calc_spi_scalers
CC = gcc
CFLAGS = -std=c99 -Wall
SRC = $(wildcard *.c)
.PHONY: all clean
all:
$(CC) $(CFLAGS) -o $(NAME) $(SRC)
clean:
rm -f $(NAME)

242
cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c vendored Normal file
View File

@ -0,0 +1,242 @@
/*
* Copyright (C) 2014 Hamburg University of Applied Sciences
* 2014 PHYTEC Messtechnik GmbH
* 2015 Eistec AB
* 2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @brief SPI bus scaler computation
*
* This helper tool calculates the needed SPI scaler values for a given APB bus
* clock speed. The result of the computation must be placed in a board's
* periph_conf.h for quick reference by the SPI drivers.
*
* @author Peter Kietzmann <peter.kietzmann@haw-hamburg.de>
* @author Johann Fischer <j.fischer@phytec.de>
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
/**
* @brief Targeted SPI bus speed values (pre-defined by RIOT)
*/
static uint32_t targets[] = { 100000, 400000, 1000000, 5000000, 10000000 };
/**
* @brief Helper function for finding optimal baud rate scalers.
*
* Find the prescaler and scaler settings that will yield a clock frequency
* as close as possible (but not above) the target frequency, given the module
* runs at module_clock Hz.
*
* Hardware properties (Baud rate configuration):
* Possible prescalers: 2, 3, 5, 7
* Possible scalers: 2, 4, 6 (sic!), 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768
*
* SCK baud rate = (f_BUS/PBR) x [(1+DBR)/BR]
*
* where PBR is the prescaler, BR is the scaler, DBR is the Double BaudRate bit.
*
* @note We are not using the DBR bit because it may affect the SCK duty cycle.
*
* @param module_clock Module clock frequency (e.g. F_BUS)
* @param target_clock Desired baud rate
* @param closest_prescaler pointer where to write the optimal prescaler index.
* @param closest_scaler pointer where to write the optimal scaler index.
*
* @return The actual achieved frequency on success
* @return Less than 0 on error.
*/
static long find_closest_baudrate_scalers(const uint32_t module_clock, const long target_clock,
uint8_t *closest_prescaler, uint8_t *closest_scaler)
{
uint8_t i;
uint8_t k;
long freq;
static const uint8_t num_scalers = 16;
static const uint8_t num_prescalers = 4;
static const int br_scalers[16] = {
2, 4, 6, 8, 16, 32, 64, 128,
256, 512, 1024, 2048, 4096, 8192, 16384, 32768
};
static const int br_prescalers[4] = {2, 3, 5, 7};
long closest_frequency = -1;
/* Test all combinations until we arrive close to the target clock */
for (i = 0; i < num_prescalers; ++i) {
for (k = 0; k < num_scalers; ++k) {
freq = module_clock / (br_scalers[k] * br_prescalers[i]);
if (freq <= target_clock) {
/* Found closest lower frequency at this prescaler setting,
* compare to the best result */
if (closest_frequency < freq) {
closest_frequency = freq;
*closest_scaler = k;
*closest_prescaler = i;
}
break;
}
}
}
if (closest_frequency < 0) {
/* Error, no solution found, this line is never reachable with current
* hardware settings unless a _very_ low target clock is requested.
* (scaler_max * prescaler_max) = 229376 => target_min@100MHz = 435 Hz*/
return -1;
}
return closest_frequency;
}
/**
* @brief Helper function for finding optimal delay scalers.
*
* Find the prescaler and scaler settings that will yield a delay timing
* as close as possible (but not shorter than) the target delay, given the
* module runs at module_clock Hz.
*
* Hardware properties (delay configuration):
* Possible prescalers: 1, 3, 5, 7
* Possible scalers: 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536
*
* delay = (1/f_BUS) x prescaler x scaler
*
* Because we want to do this using only integers, the target_freq parameter is
* the reciprocal of the delay time.
*
* @param module_clock Module clock frequency (e.g. F_BUS)
* @param target_freq Reciprocal (i.e. 1/t [Hz], frequency) of the desired delay time.
* @param closest_prescaler pointer where to write the optimal prescaler index.
* @param closest_scaler pointer where to write the optimal scaler index.
*
* @return The actual achieved frequency on success
* @return Less than 0 on error.
*/
static long find_closest_delay_scalers(const uint32_t module_clock, const long target_freq,
uint8_t *closest_prescaler, uint8_t *closest_scaler)
{
uint8_t i;
uint8_t k;
long freq;
int prescaler;
int scaler;
static const uint8_t num_scalers = 16;
static const uint8_t num_prescalers = 4;
long closest_frequency = -1;
/* Test all combinations until we arrive close to the target clock */
for (i = 0; i < num_prescalers; ++i) {
for (k = 0; k < num_scalers; ++k) {
prescaler = (i * 2) + 1;
scaler = (1 << (k + 1)); /* 2^(k+1) */
freq = module_clock / (prescaler * scaler);
if (freq <= target_freq) {
/* Found closest lower frequency at this prescaler setting,
* compare to the best result */
if (closest_frequency < freq) {
closest_frequency = freq;
*closest_scaler = k;
*closest_prescaler = i;
}
break;
}
}
}
if (closest_frequency < 0) {
/* Error, no solution found, this line is never reachable with current
* hardware settings unless a _very_ low target clock is requested.
* (scaler_max * prescaler_max) = 458752 */
return -1;
}
return closest_frequency;
}
int main(int argc, char **argv)
{
uint32_t modclk;
int i;
if (argc != 2) {
printf("usage: %s <module clock>\n", argv[0]);
return 1;
}
modclk = (uint32_t)atoi(argv[1]);
if (modclk == 0) {
printf("error: invalid input value\n");
return 1;
}
printf("\nCalculating SPI clock scalers for a module clock of: %iHz\n\n",
(int)modclk);
puts("static const uint32_t spi_clk_config[] = {");
for (i = 0; i < (sizeof(targets) / sizeof(targets[0])); i++) {
uint8_t tmp, ptmp;
long res;
/* bus clock */
res = find_closest_baudrate_scalers(modclk, targets[i], &ptmp, &tmp);
if (res < 0) {
puts("error: no applicable bus clock scalers could be found!");
return 1;
}
puts(" (");
printf(" SPI_CTAR_PBR(%i) | SPI_CTAR_BR(%i) | /* -> %iHz */\n",
(int)ptmp, (int)tmp, (int)res);
/* t_csc: chip select to fist clock signal delay */
if (find_closest_delay_scalers(modclk, targets[i], &ptmp, &tmp) < 0) {
puts("error: no applicable delay values for t_csc found\n");
return 1;
}
printf(" SPI_CTAR_PCSSCK(%i) | SPI_CTAR_CSSCK(%i) |\n", (int)ptmp, (int)tmp);
/* t_asc: delay after last clock signal to release of chip select */
if (find_closest_delay_scalers(modclk, targets[i], &ptmp, &tmp) < 0) {
puts("error: no applicable delay values for t_asc found\n");
return 1;
}
printf(" SPI_CTAR_PASC(%i) | SPI_CTAR_ASC(%i) |\n", (int)ptmp, (int)tmp);
/* t_psc: delay between release and next assertion of chip select */
if (find_closest_delay_scalers(modclk, targets[i], &ptmp, &tmp) < 0) {
puts("error: no applicable delay values for t_csc found\n");
return 1;
}
printf(" SPI_CTAR_PDT(%i) | SPI_CTAR_DT(%i)\n", (int)ptmp, (int)tmp);
if (i == (sizeof(targets) / sizeof(targets[0])) - 1) {
puts(" )");
}
else {
puts(" ),");
}
}
puts("};");
return 0;
}

60
cpu/kinetis_common/include/periph_cpu.h
View File

@ -66,6 +66,28 @@ typedef uint16_t gpio_t;
*/
#define PWM_CHAN_MAX (4U)
/**
* @brief Define a CPU specific SPI hardware chip select line macro
*
* We simply map the 5 hardware channels to the numbers [0-4], this still allows
* us to differentiate between GPIP_PINs and SPI_HWSC lines.
*/
#define SPI_HWCS(x) (x)
/**
* @brief Kinetis CPUs have a maximum number of 5 hardware chip select lines
*/
#define SPI_HWCS_NUMOF (5)
/**
* @brief This CPU makes use of the following shared SPI functions
* @{
*/
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
/** @} */
#ifndef DOXYGEN
/**
* @brief Override GPIO modes
@ -88,7 +110,7 @@ typedef enum {
*
* To combine values just aggregate them using a logical OR.
*/
enum {
typedef enum {
GPIO_AF_ANALOG = PORT_PCR_MUX(0), /**< use pin as analog input */
GPIO_AF_GPIO = PORT_PCR_MUX(1), /**< use pin as GPIO */
GPIO_AF_2 = PORT_PCR_MUX(2), /**< use alternate function 2 */
@ -100,7 +122,7 @@ enum {
GPIO_PCR_OD = (PORT_PCR_ODE_MASK), /**< open-drain mode */
GPIO_PCR_PD = (PORT_PCR_PE_MASK), /**< enable pull-down */
GPIO_PCR_PU = (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK) /**< enable PU */
};
} gpio_pcr_t;
#ifndef DOXYGEN
/**
@ -161,6 +183,21 @@ typedef enum {
/** @} */
#endif /* ndef DOXYGEN */
#ifndef DOXYGEN
/**
* @brief Override default ADC resolution values
* @{
*/
#define HAVE_SPI_MODE_T
typedef enum {
SPI_MODE_0 = 0, /**< CPOL=0, CPHA=0 */
SPI_MODE_1 = (SPI_CTAR_CPHA_MASK), /**< CPOL=0, CPHA=1 */
SPI_MODE_2 = (SPI_CTAR_CPOL_MASK), /**< CPOL=1, CPHA=0 */
SPI_MODE_3 = (SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK) /**< CPOL=1, CPHA=1 */
} spi_mode_t;
/** @} */
#endif /* ndef DOXYGEN */
/**
* @brief CPU specific ADC configuration
*/
@ -208,15 +245,28 @@ typedef struct {
*/
typedef struct {
FTM_Type* ftm; /**< used FTM */
struct { /**< logical channel configuration */
struct {
gpio_t pin; /**< GPIO pin used, set to GPIO_UNDEF */
uint8_t af; /**< alternate function mapping */
uint8_t ftm_chan; /**< the actual FTM channel used */
} chan[PWM_CHAN_MAX];
} chan[PWM_CHAN_MAX]; /**< logical channel configuration */
uint8_t chan_numof; /**< number of actually configured channels */
uint8_t ftm_num; /**< FTM number used */
} pwm_conf_t;
/**
* @brief SPI module configuration options
*/
typedef struct {
SPI_Type *dev; /**< SPI device to use */
gpio_t pin_miso; /**< MISO pin used */
gpio_t pin_mosi; /**< MOSI pin used */
gpio_t pin_clk; /**< CLK pin used */
gpio_t pin_cs[SPI_HWCS_NUMOF]; /**< pins used for HW cs lines */
gpio_pcr_t pcr; /**< alternate pin function values */
uint32_t simmask; /**< bit in the SIM register */
} spi_conf_t;
/**
* @brief Possible timer module types
*/
@ -227,9 +277,11 @@ enum {
/**
* @brief Hardware timer type-specific device macros
* @{
*/
#define TIMER_PIT_DEV(x) (TIMER_DEV(0 + (x)))
#define TIMER_LPTMR_DEV(x) (TIMER_DEV(PIT_NUMOF + (x)))
/** @} */
/**
* @brief CPU internal function for initializing PORTs

1682
cpu/kinetis_common/periph/spi.c
View File

File diff suppressed because it is too large Load Diff

3
cpu/kw2x/cpu.c
View File

@ -23,6 +23,7 @@
#include "cpu.h"
#include "mcg.h"
#include "cpu_conf.h"
#include "periph/init.h"
#define FLASH_BASE (0x00000000)
@ -37,6 +38,8 @@ void cpu_init(void)
cortexm_init();
/* initialize the clock system */
cpu_clock_init();
/* trigger static peripheral initialization */
periph_init();
}
static inline void modem_clock_init(void)

4
cpu/lm4f120/cpu.c
View File

@ -23,6 +23,7 @@
#include "thread.h"
#include "arch/thread_arch.h"
#include "arch/irq_arch.h"
#include "periph/init.h"
/**
* @brief Initialize the CPU, set IRQ priorities
@ -34,6 +35,9 @@ void cpu_init(void)
/* initialize the clock system */
cpu_clock_init(CLOCK_SOURCE);
/* trigger static peripheral initialization */
periph_init();
}
void setup_fpu(void)

3
cpu/lpc11u34/cpu.c
View File

@ -18,6 +18,7 @@
*/
#include "cpu.h"
#include "periph/init.h"
#define SYSOSCCTRL_Val 0x00000000 /* Reset: 0x000 */
@ -111,4 +112,6 @@ void cpu_init(void)
cortexm_init();
/* initialize the clock */
clk_init();
/* trigger static peripheral initialization */
periph_init();
}

43
cpu/lpc11u34/include/periph_cpu.h
View File

@ -31,7 +31,8 @@ extern "C" {
* @brief declare needed generic SPI functions
* @{
*/
#define PERIPH_SPI_NEEDS_TRANSFER_BYTES
#define PERIPH_SPI_NEEDS_INIT_CS
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
/** @} */
@ -104,21 +105,43 @@ typedef enum {
/** @} */
#endif /* ndef DOXYGEN */
/**
* @brief PWM channel configuration
*/
/**
* @brief PWM configuration
*/
typedef struct {
LPC_CTxxBx_Type *dev;
__IO uint32_t *pins[PWM_CHAN_NUMOF]; /**< set to NULL if channel is not used */
uint16_t clk_bit;
uint8_t af;
LPC_CTxxBx_Type *dev; /**< PWM device */
__IO uint32_t *pins[PWM_CHAN_NUMOF]; /**< set to NULL if channel is not used */
uint16_t clk_bit; /**< clock enable bit */
uint8_t af; /**< alternate pin function */
} pwm_conf_t;
/**
* @brief Override SPI clock speed values
*
* @note The values expect the CPU to run at 12MHz
* @todo Generalize the SPI driver
*
* @{
*/
#define HAVE_SPI_CLK_T
typedef enum {
SPI_CLK_100KHZ = 119, /**< drive the SPI bus with 100KHz */
SPI_CLK_400KHZ = 29, /**< drive the SPI bus with 400KHz */
SPI_CLK_1MHZ = 11, /**< drive the SPI bus with 1MHz */
SPI_CLK_5MHZ = 2, /**< drive the SPI bus with 5MHz */
SPI_CLK_10MHZ = 0 /**< actual: 12 MHz */
} spi_clk_t;
/** @} */
/**
* @brief SPI configuration data
*/
typedef struct {
LPC_SSPx_Type *dev; /**< SPI device to configure */
uint32_t preset_bit; /**< mask of the corresponding preset bit */
uint32_t ahb_bit; /**< mask of the corresponding AHB bit */
} spi_conf_t;
#ifdef __cplusplus
}
#endif

295
cpu/lpc11u34/periph/spi.c
View File

@ -1,118 +1,86 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
* Copyright (C) 2015-2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_lpc11u34
* @{
*
* @file
* @brief Low-level GPIO driver implementation
* @brief Low-level SPI driver implementation
*
* @todo this implementation needs to be generalized in some aspects,
* e.g. clock configuration
*
* @author Paul RATHGEB <paul.rathgeb@skynet.be>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "board.h"
#include "mutex.h"
#include "assert.h"
#include "periph/spi.h"
#include "periph_conf.h"
#include "thread.h"
#include "sched.h"
/* guard file in case no SPI device is defined */
#if SPI_NUMOF
/**
* @brief Array holding one pre-initialized mutex for each SPI device
*/
static mutex_t locks[] = {
#if SPI_0_EN
[SPI_0] = MUTEX_INIT,
#endif
#if SPI_1_EN
[SPI_1] = MUTEX_INIT,
#endif
};
static mutex_t locks[SPI_NUMOF];
int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
static inline LPC_SSPx_Type *dev(spi_t bus)
{
LPC_SSPx_Type *spi;
/* power on the SPI device */
spi_poweron(dev);
/* configure SCK, MISO and MOSI pin */
spi_conf_pins(dev);
switch(dev) {
#if SPI_0_EN
case SPI_0:
spi = LPC_SSP0;
break;
#endif
#if SPI_1_EN
case SPI_1:
spi = LPC_SSP1;
break;
#endif
default:
return -1;
}
/* Master mode, SPI disabled */
spi->CR1 = 0;
/* Base clock frequency : 12MHz */
spi->CPSR = 4;
/* configure bus clock speed */
switch (speed) {
case SPI_SPEED_100KHZ:
spi->CR0 |= (119 << 8);
break;
case SPI_SPEED_400KHZ:
spi->CR0 |= (29 << 8);
break;
case SPI_SPEED_1MHZ:
spi->CR0 |= (11 << 8);
break;
case SPI_SPEED_5MHZ:
spi->CR0 |= (2 << 8); /* Actual : 4MHz */
break;
case SPI_SPEED_10MHZ:
spi->CR0 |= (0 << 8); /* Actual : 12MHz */
break;
}
/* Set mode and 8-bit transfer */
spi->CR0 |= 0x07 | (conf << 6);
/* Enable SPI */
spi->CR1 |= (1 << 1);
/* Wait while the BUSY flag is set */
while(spi->SR & (1 << 4)) {}
/* Clear the RX FIFO */
while(spi->SR & (1 << 2)) {
spi->DR;
}
return 0;
return spi_config[bus].dev;
}
int spi_init_slave(spi_t dev, spi_conf_t conf, char (*cb)(char data))
static inline void poweron(spi_t bus)
{
/* Slave mode not supported */
return -1;
/* de-assert SPIx, enable clock and set clock div */
LPC_SYSCON->PRESETCTRL |= (spi_config[bus].preset_bit);
LPC_SYSCON->SYSAHBCLKCTRL |= (spi_config[bus].ahb_bit);
}
int spi_conf_pins(spi_t dev)
static inline void poweroff(spi_t bus)
{
switch (dev) {
#if SPI_0_EN
case SPI_0:
LPC_SYSCON->SYSAHBCLKCTRL &= ~(spi_config[bus].ahb_bit);
LPC_SYSCON->PRESETCTRL &= ~(spi_config[bus].preset_bit);
}
void spi_init(spi_t bus)
{
/* check device */
assert(bus <= SPI_NUMOF);
/* initialize device lock */
mutex_init(&locks[bus]);
/* set clock div for all SPI devices to 1 -> 48MHz */
LPC_SYSCON->SSP0CLKDIV = 1;
LPC_SYSCON->SSP1CLKDIV = 1;
/* trigger the pin configuration */
spi_init_pins(bus);
/* power on the bus for the duration of initialization */
poweron(bus);
/* reset configuration */
dev(bus)->CR1 = 0;
/* configure base clock frequency to 12 MHz CLOCK_CORECLOCK / 4 */
dev(bus)->CPSR = 4;
/* and power off the bus again */
poweroff(bus);
}
void spi_init_pins(spi_t bus)
{
/* this is hacky as hell -> integrate this into the GPIO module */
switch (bus) {
case SPI_DEV(0):
/* SPI0 : MISO */
LPC_IOCON->PIO0_8 |= 1;
/* SPI0 : MOSI */
@ -120,128 +88,69 @@ int spi_conf_pins(spi_t dev)
/* SPI0 : SCK */
LPC_IOCON->SWCLK_PIO0_10 |= 2;
break;
#endif
#if SPI_1_EN
case SPI_1:
case SPI_DEV(1):
/* SPI1 : MISO */
LPC_IOCON->PIO1_21 |= 2;
/* SPI1 : MOSI */
LPC_IOCON->PIO0_21 |= 2;
/* SPI1 : SCK */
LPC_IOCON->PIO1_20 |= 2;
#endif
default:
return -1;
}
return 0;
}
int spi_acquire(spi_t dev)
{
if ((unsigned int)dev >= SPI_NUMOF) {
return -1;
}
mutex_lock(&locks[dev]);
return 0;
}
int spi_release(spi_t dev)
{
if ((unsigned int)dev >= SPI_NUMOF) {
return -1;
}
mutex_unlock(&locks[dev]);
return 0;
}
int spi_transfer_byte(spi_t dev, char out, char *in)
{
char tmp;
LPC_SSPx_Type *spi;
switch (dev) {
#if SPI_0_EN
case SPI_0:
spi = LPC_SSP0;
break;
#endif
#if SPI_1_EN
case SPI_1:
spi = LPC_SSP1;
break;
#endif
default:
return 0;
}
/* Wait while the BUSY flag is set */
while(spi->SR & (1 << 4)) {}
/* Put byte in the TX Fifo */
*((volatile uint8_t *)(&spi->DR)) = (uint8_t)out;
/* Wait until the current byte is transfered */
while(!(spi->SR & (1 << 2)) ) {}
/* Read the returned byte */
tmp = *((volatile uint8_t *)(&spi->DR));
/* 'return' response byte if wished for */
if (in) {
*in = tmp;
}
return 1;
}
void spi_transmission_begin(spi_t dev, char reset_val)
int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
{
/* Slave mode not supported */
/* lock an power on the bus */
mutex_lock(&locks[bus]);
poweron(bus);
/* configure bus clock and mode and set to 8-bit transfer */
dev(bus)->CR0 = ((clk << 8) | (mode << 6) | 0x07);
/* enable the bus */
dev(bus)->CR1 = (1 << 1);
/* wait until ready and flush RX FIFO */
while(dev(bus)->SR & (1 << 4)) {}
while(dev(bus)->SR & (1 << 2)) {
dev(bus)->DR;
}
return SPI_OK;
}
void spi_poweron(spi_t dev)
void spi_release(spi_t bus)
{
switch (dev) {
#if SPI_0_EN
case SPI_0:
/* De-assert SPI0 */
LPC_SYSCON->PRESETCTRL |= (1 << 0);
/* Enable SPI0 clock */
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11);
/* Clock div : 48MHz */
LPC_SYSCON->SSP0CLKDIV = 1;
break;
#endif
#if SPI_1_EN
case SPI_1:
/* De-assert SPI1 */
LPC_SYSCON->PRESETCTRL |= (1 << 2);
/* Enable SPI1 clock */
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18);
/* Clock div : 48MHz */
LPC_SYSCON->SSP1CLKDIV = 1;
break;
#endif
/* disable device, power off and release lock */
dev(bus)->CR1 = 0;
poweroff(bus);
mutex_unlock(&locks[bus]);
}
void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
const void *out, void *in, size_t len)
{
uint8_t *out_buf = (uint8_t *)out;
uint8_t *in_buf = (uint8_t *)in;
assert(out_buf || in_buf);
if (cs != SPI_CS_UNDEF) {
gpio_clear((gpio_t)cs);
}
for (size_t i = 0; i < len; i++) {
uint8_t tmp = (out_buf) ? out_buf[i] : 0;
while(dev(bus)->SR & (1 << 4)) {} /* wait for BUSY clear */
*((volatile uint8_t *)(&dev(bus)->DR)) = tmp;
while(!(dev(bus)->SR & (1 << 2))) {} /* wait RXNE */
tmp = *((volatile uint8_t *)(&dev(bus)->DR));
if (in_buf) {
in_buf[i] = tmp;
}
}
if ((!cont) && (cs != SPI_CS_UNDEF)) {
gpio_set((gpio_t)cs);
}
}
void spi_poweroff(spi_t dev)
{
switch (dev) {
#if SPI_0_EN
case SPI_0:
/* Assert SPI0 */
LPC_SYSCON->PRESETCTRL &= ~(1 << 0);
/* Disable SPI0 clock */
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11);
break;
#endif
#if SPI_1_EN
case SPI_1:
/* Assert SPI1 */
LPC_SYSCON->PRESETCTRL &= ~(1 << 2);
/* Disable SPI1 clock */
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 18);
break;
#endif
}
}
#endif /* SPI_NUMOF */

3
cpu/lpc1768/cpu.c
View File

@ -18,6 +18,7 @@
*/
#include "cpu.h"
#include "periph/init.h"
/**
* @brief Initialize the CPU, set IRQ priorities
@ -26,4 +27,6 @@ void cpu_init(void)
{
/* initialize the Cortex-M core */
cortexm_init();
/* trigger static peripheral initialization */
periph_init();
}

17
cpu/lpc2387/include/periph_cpu.h
View File

@ -74,11 +74,26 @@ typedef enum {
* @brief Declare needed generic SPI functions
* @{
*/
#define PERIPH_SPI_NEEDS_TRANSFER_BYTES
#define PERIPH_SPI_NEEDS_INIT_CS
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
/* @} */
/**
* @brief Override SPI clock speed values
* @{
*/
#define HAVE_SPI_CLK_T
typedef enum {
SPI_CLK_100KHZ = 100, /**< drive the SPI bus with 100KHz */
SPI_CLK_400KHZ = 400, /**< drive the SPI bus with 400KHz */
SPI_CLK_1MHZ = 1000, /**< drive the SPI bus with 1MHz */
SPI_CLK_5MHZ = 5000, /**< drive the SPI bus with 5MHz */
SPI_CLK_10MHZ = 10000 /**< drive the SPI bus with 10MHz */
} spi_clk_t;
/** @} */
/* @} */
#ifdef __cplusplus
}

248
cpu/lpc2387/periph/spi.c
View File

@ -1,9 +1,10 @@
/*
* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
* 2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
@ -13,22 +14,25 @@
* @file
* @brief Low-level SPI driver implementation
*
* This implementation is very basic and only supports a single SPI device with
* limited configuration options.
*
* @todo This implementation needs a major rework
*
* @author Kaspar Schleiser <kaspar@schleiser.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "mutex.h"
#include "periph/gpio.h"
#include "assert.h"
#include "periph/spi.h"
#include "periph_conf.h"
#include "board.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
#if SPI_0_EN
#define SPI_TX_EMPTY (SSP0SR & SSPSR_TFE)
#define SPI_BUSY (SSP0SR & SSPSR_BSY)
#define SPI_RX_AVAIL (SSP0SR & SSPSR_RNE)
@ -36,178 +40,94 @@
/**
* @brief Array holding one pre-initialized mutex for each SPI device
*/
static mutex_t locks[] = {
#if SPI_0_EN
[SPI_0] = MUTEX_INIT,
#endif
#if SPI_1_EN
[SPI_1] = MUTEX_INIT,
#endif
#if SPI_2_EN
[SPI_2] = MUTEX_INIT
#endif
};
static mutex_t lock = MUTEX_INIT;
int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
void spi_init(spi_t bus)
{
(void ) conf;
if (dev) {
return -1;
}
assert(bus == SPI_DEV(0));
uint32_t f_baud = 0;
switch(speed)
{
case SPI_SPEED_100KHZ:
f_baud = 100;
break;
case SPI_SPEED_400KHZ:
f_baud = 400;
break;
case SPI_SPEED_1MHZ:
f_baud = 1000;
break;
case SPI_SPEED_5MHZ:
f_baud = 5000;
break;
case SPI_SPEED_10MHZ:
f_baud = 10000;
break;
}
#if 0
/* TODO */
switch(conf)
{
case SPI_CONF_FIRST_RISING:
/**< first data bit is transacted on the first rising SCK edge */
cpha = 0;
cpol = 0;
break;
case SPI_CONF_SECOND_RISING:
/**< first data bit is transacted on the second rising SCK edge */
cpha = 1;
cpol = 0;
break;
case SPI_CONF_FIRST_FALLING:
/**< first data bit is transacted on the first falling SCK edge */
cpha = 0;
cpol = 1;
break;
case SPI_CONF_SECOND_FALLING:
/**< first data bit is transacted on the second falling SCK edge */
cpha = 1;
cpol = 1;
break;
}
#endif
/* Power*/
PCONP |= PCSSP0; /* Enable power for SSP0 (default is on)*/
/* PIN Setup*/
spi_conf_pins(dev);
/* Interface Setup*/
/* interface setup */
SSP0CR0 = 7;
/* configure pins */
spi_init_pins(bus);
/* power off the bus (default is on) */
PCONP &= ~(PCSSP0);
}
/* Clock Setup*/
void spi_init_pins(spi_t bus)
{
PINSEL3 |= (BIT8 | BIT9); /* SCLK */
PINSEL3 |= (BIT14 | BIT15); /* MISO */
PINSEL3 |= (BIT16 | BIT17); /* MOSI */
}
int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
{
uint32_t pclksel;
uint32_t cpsr;
lpc2387_pclk_scale(CLOCK_CORECLOCK / 1000, f_baud, &pclksel, &cpsr);
/* only support for mode 0 at the moment */
if (mode != SPI_MODE_0) {
return SPI_NOMODE;
}
/* lock bus */
mutex_lock(&lock);
/* power on */
PCONP |= (PCSSP0);
/* configure bus clock */
lpc2387_pclk_scale(CLOCK_CORECLOCK / 1000, (uint32_t)clk, &pclksel, &cpsr);
PCLKSEL1 &= ~(BIT10 | BIT11); /* CCLK to PCLK divider*/
PCLKSEL1 |= pclksel << 10;
SSP0CPSR = cpsr;
/* Enable*/
SSP0CR1 |= BIT1; /* SSP-Enable*/
/* enable the bus */
SSP0CR1 |= BIT1;
/* clear RxFIFO */
int dummy;
while (SPI_RX_AVAIL) { /* while RNE (Receive FIFO Not Empty)...*/
dummy = SSP0DR; /* read data*/
}
(void) dummy; /* to suppress unused-but-set-variable */
/* Clear RxFIFO:*/
while (SPI_RX_AVAIL) { /* while RNE (Receive FIFO Not Empty)...*/
dummy = SSP0DR; /* read data*/
return SPI_OK;
}
void spi_release(spi_t bus)
{
/* disable, power off, and release the bus */
SSP0CR1 &= ~(BIT1);
PCONP &= ~(PCSSP0);
mutex_unlock(&lock);
}
void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
const void *out, void *in, size_t len)
{
uint8_t *out_buf = (uint8_t *)out;
uint8_t *in_buf = (uint8_t *)in;
assert(out_buf || in_buf);
if (cs != SPI_CS_UNDEF) {
gpio_clear((gpio_t)cs);
}
/* to suppress unused-but-set-variable */
(void) dummy;
return 0;
}
int spi_init_slave(spi_t dev, spi_conf_t conf, char (*cb)(char))
{
(void)dev;
(void)conf;
(void)cb;
printf("%s:%s(): stub\n", RIOT_FILE_RELATIVE, __func__);
/* TODO */
return -1;
}
void spi_transmission_begin(spi_t dev, char reset_val)
{
(void)dev;
(void)reset_val;
printf("%s:%s(): stub\n", RIOT_FILE_RELATIVE, __func__);
/* TODO*/
}
int spi_acquire(spi_t dev)
{
if (dev >= SPI_NUMOF) {
return -1;
}
mutex_lock(&locks[dev]);
return 0;
}
int spi_release(spi_t dev)
{
if (dev >= SPI_NUMOF) {
return -1;
}
mutex_unlock(&locks[dev]);
return 0;
}
int spi_transfer_byte(spi_t dev, char out, char *in)
{
(void) dev;
while (!SPI_TX_EMPTY) {}
SSP0DR = out;
while (SPI_BUSY) {}
while (!SPI_RX_AVAIL) {}
char tmp = (char)SSP0DR;
if (in != NULL) {
*in = tmp;
for (size_t i = 0; i < len; i++) {
uint8_t tmp = (out_buf) ? out_buf[i] : 0;
while (!SPI_TX_EMPTY) {}
SSP0DR = tmp;
while (SPI_BUSY) {}
while (!SPI_RX_AVAIL) {}
tmp = (uint8_t)SSP0DR;
if (in_buf) {
in_buf[i] = tmp;
}
}
return 1;
}
void spi_poweron(spi_t dev)
{
(void) dev;
}
void spi_poweroff(spi_t dev)
{
(void) dev;
(void) dev;
}
int spi_conf_pins(spi_t dev)
{
switch (dev) {
case 0:
PINSEL3 |= BIT8 + BIT9; /* SCLK */
PINSEL3 |= BIT14 + BIT15; /* MISO */
PINSEL3 |= BIT16 + BIT17; /* MOSI */
return 0;
default:
return -1;
if ((!cont) && cs != SPI_CS_UNDEF) {
gpio_set((gpio_t)cs);
}
}
#endif /* SPI_0_EN */

40
cpu/msp430fxyz/include/periph_cpu.h
View File

@ -45,6 +45,11 @@ typedef uint16_t gpio_t;
*/
#define GPIO_PIN(x, y) ((gpio_t)(((x & 0xff) << 8) | (1 << (y & 0xff))))
/**
* @brief No support for HW chip select...
*/
#define SPI_HWCS(x) (SPI_CS_UNDEF)
#ifndef DOXYGEN
/**
* @brief Override flank selection values
@ -57,6 +62,40 @@ typedef enum {
GPIO_BOTH = 0xab /**< not supported -> random value*/
} gpio_flank_t;
/** @} */
/**
* @brief Override SPI mode selection values
*/
#define HAVE_SPI_MODE_T
#ifndef SPI_USE_USCI
typedef enum {
SPI_MODE_0 = (USART_TCTL_CKPH), /**< CPOL=0, CPHA=0 */
SPI_MODE_1 = 0, /**< CPOL=0, CPHA=1 */
SPI_MODE_2 = (USART_TCTL_CKPL | USART_TCTL_CKPH), /**< CPOL=1, CPHA=0 */
SPI_MODE_3 = (USART_TCTL_CKPL) /**< CPOL=1, CPHA=1 */
} spi_mode_t;
#else
typedef enum {
SPI_MODE_0 = (USCI_SPI_CTL0_CKPH), /**< CPOL=0, CPHA=0 */
SPI_MODE_1 = 0, /**< CPOL=0, CPHA=1 */
SPI_MODE_2 = (USCI_SPI_CTL0_CKPL | USCI_SPI_CTL0_CKPH), /**< CPOL=1, CPHA=0 */
SPI_MODE_3 = (USCI_SPI_CTL0_CKPL) /**< CPOL=1, CPHA=1 */
} spi_mode_t;
#endif
/** @} */
/**
* @brief Override SPI clock speed selection values
*/
#define HAVE_SPI_CLK_T
typedef enum {
SPI_CLK_100KHZ = 100000, /**< 100KHz */
SPI_CLK_400KHZ = 400000, /**< 400KHz */
SPI_CLK_1MHZ = 1000000, /**< 1MHz */
SPI_CLK_5MHZ = 5000000, /**< 5MHz */
SPI_CLK_10MHZ = 0, /**< not supported */
} spi_clk_t;
/** @} */
#endif /* ndef DOXYGEN */
/**
@ -83,6 +122,7 @@ void gpio_periph_mode(gpio_t pin, bool enable);
* @brief declare needed generic SPI functions
* @{
*/
#define PERIPH_SPI_NEEDS_INIT_CS
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS

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