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124 lines
3.4 KiB
C
124 lines
3.4 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc430
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* @{
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*
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* @file
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* @brief Cortex CMSIS style definition of CC430 registers
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*
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* @todo This file is incomplete, not all registers are listed. Further
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* There are probably some inconsistencies throughout the MSP430
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* family which need to be addressed.
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef CC430_REGS_H
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#define CC430_REGS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Shortcut to specify 8-bit wide registers
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*/
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#define REG8 volatile uint8_t
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/**
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* @brief Shortcut to specify 16-bit wide registers
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*/
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#define REG16 volatile uint16_t
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/**
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* @brief Timer module registers
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*/
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typedef struct {
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REG16 CTL; /**< timer control */
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REG16 CCTL[7]; /**< capture compare channel control */
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REG16 R; /**< current counter value */
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REG16 CCR[7]; /**< capture compare channel values */
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REG16 reserved[7]; /**< reserved */
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REG16 IV; /**< interrupt vector */
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REG16 EX0; /**< expansion 0 */
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} msp_timer_t;
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/**
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* @brief Timer Control register bitmap
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* @{
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*/
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#define CTL_IFG (0x0001)
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#define CTL_IE (0x0002)
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#define CTL_CLR (0x0004)
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#define CTL_MC_MASK (0x0030)
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#define CTL_MC_STOP (0x0000)
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#define CTL_MC_UP (0x0010)
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#define CTL_MC_CONT (0x0020)
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#define CTL_MC_UPDOWN (0x0030)
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#define CTL_ID_MASK (0x00c0)
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#define CTL_ID_DIV1 (0x0000)
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#define CTL_ID_DIV2 (0x0040)
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#define CTL_ID_DIV4 (0x0080)
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#define CTL_ID_DIV8 (0x00c0)
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#define CTL_TASSEL_MASK (0x0300)
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#define CTL_TASSEL_TCLK (0x0000)
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#define CTL_TASSEL_ACLK (0x0100)
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#define CTL_TASSEL_SMCLK (0x0200)
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#define CTL_TASSEL_INV_TCLK (0x0300)
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/** @} */
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/**
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* @brief Timer Channel Control register bitmap
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* @{
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*/
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#define CCTL_CCIFG (0x0001)
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#define CCTL_COV (0x0002)
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#define CCTL_OUT (0x0004)
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#define CCTL_CCI (0x0008)
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#define CCTL_CCIE (0x0010)
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#define CCTL_OUTMOD_MASK (0x00e0)
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#define CCTL_OUTMOD_OUTVAL (0x0000)
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#define CCTL_OUTMOD_SET (0x0020)
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#define CCTL_OUTMOD_TOG_RESET (0x0040)
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#define CCTL_OUTMOD_SET_RESET (0x0060)
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#define CCTL_OUTMOD_TOGGLE (0x0080)
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#define CCTL_OUTMOD_RESET (0x00a0)
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#define CCTL_OUTMOD_TOG_SET (0x00c0)
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#define CCTL_OUTMOD_RESET_SET (0x00e0)
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#define CCTL_CAP (0x0100)
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#define CCTL_CLLD_MASK (0x0600)
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#define CCTL_SCS (0x0800)
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#define CCTL_CCIS_MASK (0x3000)
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#define CCTL_CM_MASK (0xc000)
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/** @} */
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/**
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* @brief Base register address definitions
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* @{
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*/
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#define TIMER_A0_BASE ((uint16_t)0x0340)
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#define TIMER_A1_BASE ((uint16_t)0x0380)
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/** @} */
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/**
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* @brief Typing of base register objects
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* @{
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*/
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#define TIMER_A0 ((msp_timer_t *)TIMER_A0_BASE)
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#define TIMER_A1 ((msp_timer_t *)TIMER_A1_BASE)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CC430_REGS_H */
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/** @} */
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