cpu/cc430: added peripheral timer implementation

cpu/cc430/Makefile.include

@@ -2,4 +2,4 @@ INCLUDES += -I$(RIOTBASE)/cpu/cc430/include/
 
 include $(RIOTCPU)/msp430-common/Makefile.include
 
-export USEMODULE += periph
+export USEMODULE += periph hwtimer_compat

cpu/cc430/include/cc430_regs.h

@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2015 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_cc430
+ * @{
+ *
+ * @file
+ * @brief       Cortex CMSIS style definition of CC430 registers
+ *
+ * @todo        This file is incomplete, not all registers are listed. Further
+ *              There are probably some inconsistencies throughout the MSP430
+ *              family which need to be addressed.
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ */
+
+#ifndef CC430_REGS_H
+#define CC430_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief   Shortcut to specify 8-bit wide registers
+ */
+#define REG8                volatile uint8_t
+
+/**
+ * @brief   Shortcut to specify 16-bit wide registers
+ */
+#define REG16               volatile uint16_t
+
+/**
+ * @brief   Timer module registers
+ */
+typedef struct {
+    REG16   CTL;            /**< timer control */
+    REG16   CCTL[7];        /**< capture compare channel control */
+    REG16   R;              /**< current counter value */
+    REG16   CCR[7];         /**< capture compare channel values */
+    REG16   reserved[7];    /**< reserved */
+    REG16   IV;             /**< interrupt vector */
+    REG16   EX0;            /**< expansion 0 */
+} msp_timer_t;
+
+/**
+ * @brief   Timer Control register bitmap
+ * @{
+ */
+#define CTL_IFG                 (0x0001)
+#define CTL_IE                  (0x0002)
+#define CTL_CLR                 (0x0004)
+#define CTL_MC_MASK             (0x0030)
+#define CTL_MC_STOP             (0x0000)
+#define CTL_MC_UP               (0x0010)
+#define CTL_MC_CONT             (0x0020)
+#define CTL_MC_UPDOWN           (0x0030)
+#define CTL_ID_MASK             (0x00c0)
+#define CTL_ID_DIV1             (0x0000)
+#define CTL_ID_DIV2             (0x0040)
+#define CTL_ID_DIV4             (0x0080)
+#define CTL_ID_DIV8             (0x00c0)
+#define CTL_TASSEL_MASK         (0x0300)
+#define CTL_TASSEL_TCLK         (0x0000)
+#define CTL_TASSEL_ACLK         (0x0100)
+#define CTL_TASSEL_SMCLK        (0x0200)
+#define CTL_TASSEL_INV_TCLK     (0x0300)
+/** @} */
+
+/**
+ * @brief   Timer Channel Control register bitmap
+ * @{
+ */
+#define CCTL_CCIFG              (0x0001)
+#define CCTL_COV                (0x0002)
+#define CCTL_OUT                (0x0004)
+#define CCTL_CCI                (0x0008)
+#define CCTL_CCIE               (0x0010)
+#define CCTL_OUTMOD_MASK        (0x00e0)
+#define CCTL_OUTMOD_OUTVAL      (0x0000)
+#define CCTL_OUTMOD_SET         (0x0020)
+#define CCTL_OUTMOD_TOG_RESET   (0x0040)
+#define CCTL_OUTMOD_SET_RESET   (0x0060)
+#define CCTL_OUTMOD_TOGGLE      (0x0080)
+#define CCTL_OUTMOD_RESET       (0x00a0)
+#define CCTL_OUTMOD_TOG_SET     (0x00c0)
+#define CCTL_OUTMOD_RESET_SET   (0x00e0)
+#define CCTL_CAP                (0x0100)
+#define CCTL_CLLD_MASK          (0x0600)
+#define CCTL_SCS                (0x0800)
+#define CCTL_CCIS_MASK          (0x3000)
+#define CCTL_CM_MASK            (0xc000)
+/** @} */
+
+/**
+ * @brief   Base register address definitions
+ * @{
+ */
+#define TIMER_A0_BASE           ((uint16_t)0x0340)
+#define TIMER_A1_BASE           ((uint16_t)0x0380)
+/** @} */
+
+/**
+ * @brief   Typing of base register objects
+ * @{
+ */
+#define TIMER_A0                ((msp_timer_t *)TIMER_A0_BASE)
+#define TIMER_A1                ((msp_timer_t *)TIMER_A1_BASE)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CC430_REGS_H */
+/** @} */

cpu/cc430/include/periph_cpu.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2015 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup         cpu_cc430
+ * @{
+ *
+ * @file
+ * @brief           CPU specific definitions for internal peripheral handling
+ *
+ * @author          Hauke Petersen <hauke.peterse@fu-berlin.de>
+ */
+
+#ifndef CPU_PERIPH_H_
+#define CPU_PERIPH_H_
+
+#include "cpu.h"
+#include "cc430_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* more to come here... */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CPU_PERIPH_H_ */
+/** @} */

cpu/cc430/periph/Makefile

@@ -1 +1,3 @@
+MODULE = periph
+
 include $(RIOTBASE)/Makefile.base

cpu/cc430/periph/timer.c

@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2015 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_cc430
+ * @{
+ *
+ * @file
+ * @brief       Low-level timer driver implementation
+ *
+ * This implementation does only support one fixed timer, as defined in the
+ * boards periph_conf.h file.
+ *
+ * @todo        Generalize to handle more timers and make them configurable
+ *              through the board's `periph_conf.h`
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ *
+ * @}
+ */
+
+#include "cpu.h"
+#include "periph_cpu.h"
+#include "periph_conf.h"
+#include "periph/timer.h"
+
+/**
+ * @brief   Save reference to the timer callback
+ */
+static void (*isr_cb)(int chan);
+
+
+int timer_init(tim_t dev, unsigned int us_per_tick, void (*callback)(int))
+{
+    /* using fixed TIMER_DEV for now */
+    if (dev != 0) {
+        return -1;
+    }
+    /* TODO: configure time-base depending on us_per_tick value */
+    if (us_per_tick != 1) {
+        return -1;
+    }
+
+    /* reset the timer A configuration */
+    TIMER_DEV->CTL = CTL_CLR;
+    /* save callback */
+    isr_cb = callback;
+    /* configure timer to use the SMCLK with prescaler of 8 */
+    TIMER_DEV->CTL = (CTL_TASSEL_SMCLK | CTL_ID_DIV8);
+    /* configure CC channels */
+    for (int i = 0; i < TIMER_CHAN; i++) {
+        TIMER_DEV->CCTL[i] = 0;
+    }
+    /* start the timer in continuous mode */
+    TIMER_DEV->CTL |= CTL_MC_CONT;
+    return 0;
+}
+
+int timer_set(tim_t dev, int channel, unsigned int timeout)
+{
+    uint16_t target = TIMER_DEV->R + (uint16_t)timeout;
+    return timer_set_absolute(dev, channel, (unsigned int)target);
+}
+
+int timer_set_absolute(tim_t dev, int channel, unsigned int value)
+{
+    if (dev != 0 || channel > TIMER_CHAN) {
+        return -1;
+    }
+    TIMER_DEV->CCR[channel] = value;
+    TIMER_DEV->CCTL[channel] &= ~(CCTL_CCIFG);
+    TIMER_DEV->CCTL[channel] |=  (CCTL_CCIE);
+    return 0;
+}
+
+int timer_clear(tim_t dev, int channel)
+{
+    if (dev != 0 || channel > TIMER_CHAN) {
+        return -1;
+    }
+    TIMER_DEV->CCTL[channel] &= ~(CCTL_CCIE);
+    return 0;
+}
+
+unsigned int timer_read(tim_t dev)
+{
+    return (unsigned int)TIMER_DEV->R;
+}
+
+void timer_start(tim_t dev)
+{
+    TIMER_DEV->CTL |= CTL_MC_CONT;
+}
+
+void timer_stop(tim_t dev)
+{
+    TIMER_DEV->CTL &= ~(CTL_MC_MASK);
+}
+
+void timer_irq_enable(tim_t dev)
+{
+
+    /* TODO: not supported, yet
+     *
+     * Problem here: there is no means, of globally disabling timer interrupts.
+     * We could just enable the interrupts for all CC channels, but this would
+     * mean, that we might enable interrupts for channels, that are not active.
+     * I guess we need to remember the interrupt state of all channels before
+     * disabling and then restore this state when enabling again?! */
+}
+
+void timer_irq_disable(tim_t dev)
+{
+    /* TODO: not supported, yet */
+}
+
+void timer_reset(tim_t dev)
+{
+    TIMER_DEV->R = 0;
+}
+
+ISR(TIMER_ISR_CC0, isr_timer_a_cc0)
+{
+    __enter_isr();
+
+    TIMER_DEV->CCTL[0] &= ~(CCTL_CCIE);
+    isr_cb(0);
+
+    __exit_isr();
+}
+
+ISR(TIMER_ISR_CCX, isr_timer_a_ccx_isr)
+{
+    __enter_isr();
+
+    int chan = (int)(TIMER_DEV->IV >> 1);
+    TIMER_DEV->CCTL[chan] &= ~(CCTL_CCIE);
+    isr_cb(chan);
+
+    __exit_isr();
+}