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82 lines
1.9 KiB
C
82 lines
1.9 KiB
C
/*
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* Copyright (C) 2018 Freie Universität Berlin
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* 2017 OTA keys S.A.
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* 2018-2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Default STM32F4 clock configuration for 84MHz boards
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H
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#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H
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#include "f2f4f7/cfg_clock_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock PLL settings (84MHz)
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* @{
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*/
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/* The following parameters configure a 84MHz system clock with HSE (8MHz or
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16MHz) or HSI (16MHz) as PLL input clock */
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#ifndef CONFIG_CLOCK_PLL_M
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#define CONFIG_CLOCK_PLL_M (4)
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#endif
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#ifndef CONFIG_CLOCK_PLL_N
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
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#define CONFIG_CLOCK_PLL_N (168)
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#else
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#define CONFIG_CLOCK_PLL_N (84)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_P
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#define CONFIG_CLOCK_PLL_P (4)
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#endif
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#ifndef CONFIG_CLOCK_PLL_Q
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#define CONFIG_CLOCK_PLL_Q (7)
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#endif
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#ifndef CONFIG_CLOCK_PLL_R
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#define CONFIG_CLOCK_PLL_R (0)
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#endif
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/** @} */
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/**
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* @name Clock bus settings (APB1 and APB2)
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*/
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (2) /* max 42MHz */
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#endif
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (1) /* max 84MHz */
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#include "f2f4f7/cfg_clock_values.h"
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#if CLOCK_CORECLOCK > MHZ(84)
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#error "SYSCLK cannot exceed 84MHz"
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#endif
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#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H */
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/** @} */
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