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75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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* Copyright (C) 2015 PHYTEC Messtechnik GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup cpu_k64f Freescale K64F MCU
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* @ingroup cpu
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* @brief CPU specific implementations for the Freescale K64F
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* Kinetis Cortex-M4 MCU.
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* @{
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*
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* @file
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* @brief Implementation specific CPU configuration options
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*
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* @author Hauke Petersen <hauke.peterse@fu-berlin.de>
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* @author Johann Fischer <j.fischer@phytec.de>
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*/
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#ifndef __CPU_CONF_H
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#define __CPU_CONF_H
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#ifdef CPU_MODEL_MK64FN1M0VLL12
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#include "MK64F12.h"
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#else
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#error "undefined CPU_MODEL"
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#endif
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#include "mcg.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @brief ARM Cortex-M specific CPU configuration
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* @{
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#define CPU_IRQ_NUMOF (86U)
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#define CPU_FLASH_BASE (0x00000000)
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/** @} */
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/**
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* @brief Length for reading CPU_ID in octets
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*/
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#define CPUID_ID_LEN (16)
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/**
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* @brief Pointer to CPU_ID
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*/
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#define CPUID_ID_PTR ((void *)(&(SIM_UIDH)))
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/**
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* @brief MCU specific Low Power Timer settings.
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*/
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#define LPTIMER_CLKSRC LPTIMER_CLKSRC_LPO
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#define LPTIMER_DEV (LPTMR0) /**< LPTIMER hardware module */
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#define LPTIMER_CLKEN() (SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK) /**< Enable LPTMR0 clock gate */
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#define LPTIMER_CLKDIS() (SIM->SCGC5 &= ~SIM_SCGC5_PTMR_MASK) /**< Disable LPTMR0 clock gate */
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#define LPTIMER_CNR_NEEDS_LATCHING 1 /**< LPTMR.CNR register do not need latching */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CPU_CONF_H */
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/** @} */
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